A Statistical Study of the Effectiveness of BIST Jitter Measurement Techniques

A Statistical Study of the Effectiveness of BIST Jitter Measurement Techniques David Bordoley, Hieu guyen, Mani Soma Department of Electrical Engineering, University of Washington, Seattle WA {bordoley, hieun, soma} @ee.washington.edu Abstract This paper describes a statistical study of the effectiveness of state-of-the-art built-in-self-test (BIST) jitter measurement techniques. Many BIST solutions under-sample the signal under test, estimating the jitter in a system based upon a subset of the total number of clock edges. In this paper, we explore how under-sampling affects the accuracy of jitter measurements, and demonstrate a technique for estimating the actual jitter using a Gaussian distribution estimation. Our theoretical results were verified through a simulation study and comparison to experimental data collected from a 400 MHz phase-locked loop supplied by an industry sponsor. Keywords: jitter, built-in-self-test, phase-locked loops. 1. Introduction The push by consumers for microprocessor and communication systems with ever increasing speed and performance has led to the increase of clock frequencies into the multi-ghz range. At such high frequencies, the effect of even single digit pico-second jitter can quickly become a major system performance issue for designers and may even cause system failure. Furthermore, multi-ghz signals present many new obstacles to jitter testing. Traditionally, jitter has been measured off-chip using automated testing equipment (ATE), but at such high frequencies this is becoming increasingly expensive and impractical. This dilemma has led many test designers to suggest a move to built-in-selftest (BIST) on-chip methods. Various BIST strategies for measuring jitter exist, such as those mentioned in [1], [], [3], and [4]. One potential pitfall of many proposed BIST jitter measurement techniques is that they do not measure the jitter between every clock edge. Rather they under-sample the edges of a clock signal and fit the measured jitter to a probability density function to estimate the actual jitter in the system [1]. Until now, it has been widely accepted but not proven that under-sampling clock edges should not significantly affect the amount of measured jitter. However, the use of under-sampling has led many industry designers to question the quality of proposed BIST solutions as accurate jitter measurement techniques. In particular, concern has been expressed that these techniques may underestimate the actual jitter in the system by failing to consider jitter in between the sampled cycles. In this paper we seek to quantize the impact of under-sampling on the measured RMS cycle-to-cycle jitter, and present a method for more accurate jitter estimation.. Measuring cycle-to-cycle jitter Jitter is the time domain realization of frequency domain phase noise and is intrinsic to all electronic systems. It results in a variation of the clock edge from the ideal time location and can lead to degradation of system performance, potentially leading to system failure. Several forms of jitter exist such as timing and period jitter; however cycle-to-cycle jitter is of particular importance to communication and digital system designers and is the focus of this study. Cycle-to-cycle jitter is the instantaneous change in the period of a signal per cycle [5]. Figure 1 illustrates the effect of cycle-to-cycle jitter on a typical clock signal. Figure 1. Illustration of cycle-to-cycle jitter [5]. Cycle-to-cycle jitter can be expressed mathematically in terms of the difference of the periods of two adjacent cycles as shown in (1): Jcc, (1) n = Tn Tn 1 where T n is the period of the nth clock cycle. While the instantaneous value of the cycle-to-cycle jitter is an important metric of system performance, the RMS value of the cycle-to-cycle jitter collected over a long period of time proves useful in determining the effective jitter in a system and can be computed using (). n 1 tot JccRMS = ( Jcc n ) () n tot n = 1 Ideally, the measured RMS cycle-to-cycle jitter would be based upon the instantaneous cycle-to-cycle jitter measured between every cycle of operation over a long 0-7803-954-X/05/$0.00 005 IEEE. 100

period time. However, this is not possible or practical using currently available BIST measurement techniques due to the multi-ghz frequency of the signals under test. Instead, these methods measure the cycle-to-cycle jitter using an under-sampling technique where only 1 out of edges is sampled during measurement (Figure ). JccRMS measured = n tot / 1 ( T n T n 1) (3) n / tot n= 1 where is the subdivision ratio. Since T n and T n-1 are both IID random variables, this equation can be reduced to the form in (4). JccRMS measured = 1 n tot n tot ( Tn Tn 1) n= 1 (4) Figure. Zero-crossing locations used to measure jitter for = 1, and 4. The use of under-sampling presents several theoretical problems that must be addressed before BIST jitter measurement techniques are widely adopted in industry. Of particular concern is the potential of missing jitter that occurs in between measured edges due to both periodic and random noise in the signal under test. 3. Modeling jitter Jitter is a statistical variation in the edge of a clock signal and can therefore be modeled as a statistical process. The total jitter in a system can be expressed as the convolution of two distinct types of jitter: deterministic jitter and random jitter. Deterministic clock jitter occurs due to periodic noise sources in a circuit, such as duty cycle distortion and tends to be non- Gaussian distributed and periodic. Random jitter is attributed to the random motion of particles within a device or transmission medium [6] and tends to be Gaussian distributed. It is interesting to note that in the absence of deterministic jitter, jitter in a system can be treated as Gaussian distributed. One method that claims to model both deterministic and random jitter is the Tailfit model proposed in [6] and [7]. This model is used in several industry applications and will be used as a point of reference in this study. 4. Theoretical analysis Since the random component of jitter is purely Gaussian distributed, we can easily decompose the theoretical effects of under-sampling if deterministic jitter is ignored. This mathematical simplification allows us to assume that the individually measured periods in (1) are independent and identically distributed (IID) random variables. The measured RMS cycle-to-cycle jitter using under-sampling is: Substituting in, the actual RMS jitter can then be estimated from the measured RMS jitter using (5). JccRMS actual = JccRMS (5) measured The accuracy of the estimated actual RMS cycle-tocycle jitter is governed by the law of large numbers. Given a large enough sample size the estimation can be made arbitrarily accurate. Furthermore, the work in [8] shows that the Gaussian estimation can be fairly accurate representation of the actual jitter in a system if the frequency of periodic noise is significantly slower than the frequency of the signal under test. 5. Study method In order to quantize the effect of under-sampling upon RMS cycle-to-cycle random jitter measurements, a method and implementation were developed to produce a realistic jittery clock signal. 1. Generate a digital clock signal with frequency F for C cycles.. Use a statistical jitter noise model to generate a variation in each edge of the signal. 3. Measure the arrival time of every rising edge in the signal. 4. Choose the desired under-sampling ratio,, and measure the cycle-to-cycle between every cycles for the desired number of clock cycles. 5. Compute the RMS cycle-to-cycle jitter based on under-sampling. 6. Compare with exact RMS cycle-to-cycle jitter result, and verify the correction factor in (5). This method, while relatively simple, can be used to very accurately simulate the effect of under-sampling on the measured cycle-to-cycle jitter. In particular, it is a very robust technique due to the fact that any statistical jitter noise model can be used to perturb the signal edge. In performing this study, we took advantage of this fact by simulating with three different models of jitter: 101

uniform random, Gaussian random and the Tailfit model [6, 7]. 6. Simulation setup A Matlab simulation was conducted to test the effect of under-sampling on the measured RMS cycle-to-cycle jitter using the method described in section 3. A 6 GHz ideal digital clock signal was used for testing purposes as it is well within the expected clock frequency range of state-of-the-art phase-locked loops. Three different noise models were used to create the jittery clock edge, each applying jitter within the single digit pico-second range. The first noise model treated clock jitter as a uniform random variable. While this does not accurately represent the jitter distribution in real systems, it does provide an interesting point of reference. For this simulation a uniform random amount of jitter ranging from +/- 10 ps was applied to the test waveform. This jitter distribution is illustrated in Figure 3. Figure 4. ormalized histogram of the Gaussian jitter distribution. µl =.5 ps, σ l = 1 ps µr = 7.5 ps, σ r = 1 ps Figure 5. ormalized histogram of the Tailfit jitter distribution. Figure 3. ormalized histogram of the uniform random jitter distribution. The second jitter model treated jitter in the system as Gaussian distributed. As noted in [6], this model fairly accurately models jitter when ignoring the effects of deterministic jitter. For this simulation, a Gaussian distribution of jitter was applied to the waveform with a mean value of zero and standard deviation of 10 ps as shown in Figure 4. Finally, a simulation was conducted using the Tailfit model. The authors of [6, 7] claim this model accurately represents both random and deterministic jitter. For the purpose of simulation, we assumed a jitter distribution as shown in Figure 5. A zero-crossing technique was used to measure the arrival time of each rising edge. This method was chosen due to the strictly digital nature of the signals being tested, and was adequate for our purpose. For each jitter model, RMS cycle-to-cycle jitter was calculated using under-sampling ratios of = 1,, 4, 8 and 16, with the number of cycles varying from 100 to 10,000. 7. Simulation results Figures 6 through 8 show the measured RMS cycle-tocycle jitter on simulated 6 GHz clock signals with uniform distributed, Gaussian distributed and Tailfit distributed jitter respectively. For each distribution, RMS cycle-to-cycle jitter was calculated over 100, 1000 and 10,000 clock cycles varying the under-sampling ratio,, from 1 to 16. The calculated values are equivalent to the measured RMS cycle-to-cycle jitter using under-sampling without a correction factor. Tables 1 through 9 show comparisons of the calculated RMS cycle-to-cycle jitter for each undersampling ratio, as well as the actual jitter after the correction factor in (5) is applied. Finally each table provides the percentage error between the measurement with no under-sampling and the measurement made when using under-sampling with a correction factor. A positive error indicates an over estimation of the actual jitter, while a negative error indicates an under estimation. 10

7.1 Simulated results for uniform random distribute jitter As shown in Figure 6 and Tables 1,, and 3, significant amounts of jitter are missed when calculating the RMS cycle-to-cycle jitter of uniform random distributed jitter using under-sampled measurements. However, it is possible to accurately predict the actual jitter in the signal when using the correction factor in (5). As expected the accuracy of the correction factor is highly dependent on the number of samples collected. For instance, when measuring over 100 cycles it was possible to predict the actual jitter within a nine-percent error of the measurement made with no under-sampling using an under-sampling ratio of = (Table 1). Measuring over 1000 cycles, it was possible to predict actual jitter within a single percentage point with =, and the = 4 measurement varied by only fourteen percent from the measurement made with no under-sampling (Table ). Similar results were seen when measuring over 10,000 cycles, where under-sampling with = 8 still yielded only a single-digit percentage error, and = 16 had only a thirteen percent error (Table 8). It is worth noting some of the statistical inaccuracies in the raw data. These inaccuracies are most prevalent when measuring over 100 and 1000 cycles with large sampling ratios. The obvious source of these inaccuracies is lack of a large enough data set in the RMS cycle-tocycle calculation, preventing the measurement from converging to the expected value. RMS Cycle-to-Cycle 10 8 6 4 0 100 1000 10000 umber of Cycles = 1 = = 4 = 8 = 16 Figure 6: Measured RMS cycle-to-cycle jitter on a 6 GHz signal with uniform random distributed jitter. Table 1. jitter vs. actual jitter with correction factor measured over 100 cycles for uniform random distributed jitter. RMS 1 8.868 A A 5.685 8.040-9.331 4 3.989 7.978-10.034 8 3.17 8.844-0.69 16 6.54 5.014 18.081 Table. jitter vs. actual jitter with correction factor measured over 1000 cycles for uniform random distributed jitter. RMS 1 8.66 A A 5.89 8.43-0.74 4 3.568 7.135-13.679 8.11 5.973-7.747 16 1.107 4.49-46.4 Table 3. jitter vs. actual jitter with correction factor measured over 10,000 cycles for uniform random distributed jitter. RMS 1 8.15 A A 5.711 8.076-0.596 4 4.086 8.171 0.571 8.841 8.036-1.09 16 1.759 7.038-13.379 7. Simulation results for Gaussian distributed jitter The results for Gaussian distributed jitter were even more encouraging than those observed for uniform distributed jitter. The improvement in accuracy over the uniform distributed jitter is to be expected as our theoretical correction factor is based upon an assumption of Gaussian distributed jitter. For instance, with a 100 cycles and an under-sampling ratio of two, it was possible to predict the actual jitter within five percent of the measurement made with no under-sampling (Table 4). Measuring over 1000 cycles, it was again possible to predict the actual jitter within a single-digit percentage point using =, and with = 4 the percentage error was only eight percent (Table 5). The results measured over 10,000 cycles were the most encouraging though. With both = and = 4, it was possible to predict the actual jitter within a single percentage point, while both = 8 and = 16 yielded only four percent error (Table 6). RMS Cycle-to-Cycle 16 14 1 10 8 6 4 0 100 1000 10000 umber of Cycles = 1 = = 4 = 8 = 16 Figure 7: Measured RMS cycle-to-cycle jitter on a 6 GHz signal with Gaussian distributed jitter. 103

Table 4. jitter vs. actual jitter with correction factor measured over 100 cycles for Gaussian distributed jitter. RMS 1 14.78 A A 10.616 15.013 5.150 4 13.517 7.034 89.340 8 5.95 14.976 4.886 16 4.914 19.654 37.65 Table 5. jitter vs. actual jitter with correction factor measured over 1000 cycles for Gaussian distributed jitter. RMS 1 15.097 A A 10.583 14.967-0.864 4 6.939 13.878-8.077 8 3.98 11.111-6.401 16 3.77 13.107-13.183 Table 6. jitter vs. actual jitter with correction factor measured over 10,000 cycles for the Gaussian distributed jitter. RMS 1 14.3 A A 10.17 14.3 0.631 4 7.167 14.333 0.71 8 5.58 14.87 4.494 16 3.705 14.8 4.143 7.3 Simulation results for Tailfit distributed jitter The results obtained from measurements made on a clock signal with Tailfit distributed jitter mostly mirrored those made with uniform and Gaussian distributed jitter. As shown in Table 7, with 100 cycles of data, it was possible to predict the actual jitter within 10 percent of the actual jitter measured with no under-sampling with = (Table 7). Measuring over 1000 cycles, it was possible to predict within two percent of the actual jitter using both = and = 4 (Table 8). Measuring over 10,000 cycles also yielded similar results (Table 9). RMS Cycle-to-Cycle 10 8 6 4 0 100 1000 10000 umber of Cycles = 1 = = 4 = 8 = 16 Figure 8: Measured RMS cycle-to-cycle jitter on a 6 GHz signal with Tailfit distributed jitter. Table 7. jitter vs. actual jitter with correction factor measured over 100 cycles for Tailfit distributed jitter. RMS 1 7.439 A A 5.777 8.169 9.87 4.364 4.77-36.450 8 1.998 5.650-4.043 16 1.787 7.147-3.91 Table 8. jitter vs. actual jitter with correction factor measured over 1000 cycles for Tailfit distributed jitter. RMS 1 8.06 A A 5.794 8.194 1.641 4 4.105 8.10 1.838 8.438 6.895-14.478 16 1.515 6.058-4.855 Table 9. jitter vs. actual jitter with correction factor measured over 10,000 cycles for the Tailfit distributed jitter. RMS 1 7.931 A A 5.631 7.963 0.403 4 3.831 7.66-3.388 8.600 7.354-7.75 16.07 8.90 4.53 8. Experimental results based on real phaselocked-loop (PLL) data Data provided by an industry sponsor from a commercially available 400 MHz phase-locked loop is used as a point comparison to validate our method and simulation models. Figure 9 shows a segment of the waveform and Figure 10 shows a histogram of the period 104

distribution in the signal. otice that the distribution of periods appears to be Gaussian. Time (ns) Figure 9. Waveform segment of the 400 MHz PLL signal. Periods (ns) Figure 10. ormalized histogram of the period distribution of the 400 MHz PLL signal. Cycle-to-cycle jitter was measured for both 100 and 1000 clock cycles with under-sampling ratios of equal to 1,, 4, 8 and 16. ot enough data was provided to test 10,000 cycles. Figure 11 shows the resulting RMS cycleto-cycle jitter that was measured for each test case. Tables 10 and 11 show the estimated jitter given a correction factor and the percentage error from the actual RMS cycle-to-cycle jitter. RMS Cycle-to-Cycle Voltage (V) 14 1 10 8 6 4 0 100 1000 umber of Cycles = 1 = = 4 = 8 = 16 Figure 11. Measured RMS Cycle-to-Cycle Jitter on the 400 MHz PLL Signal. Table 10. jitter vs. actual jitter with correction factor measured over 100 cycles on the 400 MHz PLL signal. RMS 1 1.636 A A 7.911 11.188-11.46 4 4.41 8.841-30.030 8 3.886 10.990-13.07 16 1.87 7.309-4.156 Table 11. jitter vs. actual jitter with correction factor measured over 1000 cycles on the 400 MHz PLL signal. RMS 1 13.03 A A 8.381 11.85-9.055 4 6.966 13.931 6.898 8 4.973 14.065 7.96 16.865 11.458-1.078 The resulting data collected from the PLL data, confirms the results obtained through simulation. Measuring over 1,000 cycles, a 1 percent error existed between the estimated jitter based upon the measured cycle-to-cycle jitter with an under-sampling ratio of 16 and the actual ideal measured value. Given the mostly Gaussian distribution of period widths in the signal, this result is to be expected and is consistent with the percentage error measured using Gaussian distributed jitter over 1000 cycles as shown in Table 5. Furthermore, our results were confirmed by our industry sponsor who indicated that the noise during this specific test was indeed Gaussian. This indicates that the use of a Gaussian estimation in the derivation of the correction factor is indeed accurate enough to predict the actual jitter in a system. 9. Future Work As mentioned in Section 1, most state-of-the-art BIST jitter measurement solutions do not compute RMS jitter directly, but instead use a probability density function (PDF) generated from the individual cycle-tocycle jitter measurements to estimate the amount of jitter in a system. Going forward with this research we plan to adapt our technique to allow estimation of jitter based on an under-sampled PDF, which will be presented in a follow up to this paper. Initial results collected from the real PLL data used in Section 8 do suggest that under-sampling has a significant effect on the measure jitter PDF. Figures 1 and 13 show the PDFs of the cycle-to-cycle jitter measured with = 1 and =, respectively. It is clear that significant amounts of jitter (ignoring the fundamental) are missed 105

using only a small under-sampling ratio. Similar results were seen for other under-sampling ratios as well. This visual observation is confirmed by comparing the measured ideal standard deviation to the standard deviations of the under-sampled measurements as show in Table 1. It is interesting to note that it is possible to fairly accurately predict the standard deviation from an under-sampled measurement using the same correction factor proposed for RMS cycle-to-cycle jitter as shown Table 1. This observation can most likely be attributed to the fact that the proposed correction factor is based upon a Gaussian estimation and the jitter on this signal appears to be Gaussian as shown in Figure 1. While further work is needed to provide a theoretically basis for these observations, these results seem to correlate with our observations of the effect of under-sampling on measured jitter and the correction factor used in measuring RMS cycle-to-cycle jitter. Figure 1. Cycle-to-cycle normalized jitter distribution on the 400 MHz PLL signal. Table 1. jitter standard deviation vs. actual jitter standard deviation measured over 1000 cycles on the 400 MHz PLL signal. Standard Deviation (ps) % Error Predicted Actual Standard Deviation with Correction Factor (ps) % Error 1 13.60 A A A 9.504-8.33 13.440 1.36 4 6.494-51.03 1.988 -.05 8 5.171-61.01 14.65 10.9 16 4.6-67.86 17.049 8.58 10. Conclusion In this paper we presented a statistical study of the effectiveness of BIST jitter measurement techniques that use under-sampling of the clock edges to measure cycleto-cycle jitter. In particular, we showed that undersampling has a significant effect upon the amount of cycle-to-cycle jitter measured versus the actual cycle-tocycle jitter in the signal under test. We verified our simulated results by comparison to data collected from a commercially available 400 MHz phase-locked loop. Finally, we have provided a metric for estimating the actual cycle-to-cycle jitter in a signal based upon an under-sampled measurement. While this metric is based upon a Gaussian estimation of jitter, the method used to derive the metric can be extended to use any mathematical model for jitter. 11. Acknowledgements The authors of this paper would like to thank the following companies and organizations for their support of this research. Semiconductor Research Corporation, Task# 1186.001 ational Science Foundation, Contract# CCR008603 ational Semiconductor Corporation Motorola, Inc. 1. References [1] S. Sunter, A. Roy, BIST for Phase-Locked Loops in Digital Applications, Proc. IEEE International Test Conference, pp. 53-540, 1999 Figure 13. Cycle-to-cycle normalized jitter distribution on the 400 MHz PLL signal, using an under-sampling ratio of =. [] A. H. Chan, G. W. Roberts, A Jitter Characterization System Using Component-Invariant Vernier Delay Line, IEEE Transactions on VLSI Systems, Vol. 1, o. 1, pp. 79-95, January 004 [3] H. Lin, K. Taylor, A. Chong, E. Chan, M. Soma, H. Haggag, J. Huard, and J. Braatz, CMOS Built-In Test Architecture for High-Speed Jitter Measurement, Proc. IEEE International Test Conference, pp. 67-76, 003 [4] P.M. Levine, G.W. Roberts, A High-Resolution Flash Time-To- Digital Converter and Calibration Scheme, Proc. IEEE International Test Conference, pp. 1148 1157, 004 [5] T.J. Yamaguchi, M. Soma, D. Halter, R Raina, J. issen, and M. Ishida, A Method of Measuring the Cycle-to-Cycle Period Jitter of High 106

Frequency Clock Signals, VLSI Test Symposium, 19 th IEEE Proceedings on., pp. 10-100 April, 9 th May 3 rd, 001 [6] M. Li, J. Wilstrup, R. Jessen, D. Petrich, A ew Method for Jitter Decomposition Through Its Distribution Tail Fitting, Proc. IEEE International Test Conference, pp. 788 794, 1999 [7] M. Li, J. Wilstrup, Paradigm Shift for Jitter and oise in Design and Test > GB/s Communication Systems, Proc. of the International conference on Computer Desing, pp. 467-47, 003 [8] C. Ong, D. Hong, K. Cheng, L. Wang, Random Jitter Extraction Technique in a Multi-Gigahertz Signal, Proceeding of the Design Automation and Test in Europe Conference, pp. 86 91, 004 About the Authors David Bordoley is currently an electrical engineering graduate student at the University of Washington. He recently completed his masters, and is beginning work on his Ph.D. with Professor Mani Soma. His academic interests include BIST for mixed-signal and RF applications. Hieu guyen is a Ph.D. student at University of Washington studying under Professor Soma. His research interests include BIST applications for jitter measurement in mixed-signal and RF systems. Mani Soma is a professor of electrical engineering at University of Washington. He heads the Design, Test and Reliability Research Laboratory at UW and is also currently serving as acting dean of the College of Engineering at UW. 107

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