. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3) 4 + (22.3) 4 = (23.2) 4 (iii) (77) 8 (7) 8 Octal Table X 2 3 4 5 6 7 2 3 4 5 6 7 2 2 4 6 2 4 6 3 3 6 4 7 22 25 4 4 4 2 24 3 34 5 5 2 7 24 3 36 43 6 6 4 22 3 36 44 52 7 7 6 25 34 43 52 6 77 7 67 + 77 66 octal addition (7 + 7 = 6) Note : Add octal addition = octal multiplication table. Octal Addition Octal Multiplicaiton + 2 3 4 5 6 7 2 3 4 5 6 7 2 3 4 5 6 7 2 3 4 5 6 7 2 3 4 5 6 7 2 2 3 4 5 6 7 2 2 2 4 6 2 4 6 2 3 3 4 5 6 7 2 3 3 3 6 4 7 22 25 3 4 4 5 6 7 2 3 4 4 4 4 2 24 3 34 4 5 5 6 7 2 3 4 5 5 5 2 7 24 3 36 43 5 6 6 7 2 3 4 5 6 6 6 4 22 3 36 44 52 6 7 7 2 3 4 5 6 7 7 7 6 25 34 43 52 6 7 2 3 4 5 6 7 2 2 3 4 5 6 7 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
: S.E. DLDA. (b) (iv) () 2 () 2 Quotient = () 2 Reminder = () 2 (i) A AB ABC ABCD A + B + AB(C CD) ( A + AB = A + B) A + B + AB(C D) ( A (B + C) = AB + AC) A + B + ABC ABD A + ABC B BAD A + BC B AD A + AD B BC A + D + B + C A + B + C + D (ii) A[BC(ABAC)] = A [B + C (AB.AC)] (De-Morgan 2 law = AB AB) = A [B + C (A B). (A C)] (De-Morgan law = AB A B) = A [B + C (A.A A.B A.C B.C)] = A [B + C ( A.B A.C B.C)] (A.A ) = A [B + C. + A.BC A.CC B.CC] (A. = ) = A [B + + A.BC ] = AB + A.A.B.C = AB + = AB 2 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
Prelim Question Paper Solution. (c) D in : 4 Demux 2 Y Y 3 O/Ps Data input D in : 4 Demux S 3 S 2 D in D in D in : 4 Demux 3 : 4 Demux 4 : 4 Demux 5 In all five : 4 Demux ICs are used. S S S 2 S 3 are the four select lines. D in is the data input and Y Y 5 are the 6 outputs of the :6 demux. The truth table of :6 Demux is shown in below table. Select inputs Output S 3 S 2 S S Y = D in S 3 S 2 = : : : Demux 2 is selected : : : Y 3 = D in Y 4 = D in S 3 S 2 = : : : Demux 3 is selected : : : Y 7 = D in Y 8 = D in S 3 S 2 = : : : Demux 4 is selected : : : Y = D in Y 2 = D in S 3 S 2 = : : : Demux 5 is selected : : : Y 5 = D in Y 4 Y 7 Y 8 Y Y 2 Y 5 O/Ps O/Ps O/Ps S S 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 3
: S.E. DLDA. (d) The "Race Around Condition" that we are going to explain occurs when J = K = i.e. when the latch is in the toggle mode. Refer figure which shows the waveforms for the various modes, when a rectangular waveform is applied to the "Enable" input Waveforms for various modes of a JK latch. Interval t -t During this interval J =, K = and E =. Hence the latch is disabled and there is no change in Q. Interval t -t 2 During this interval J =, K = and E = l. Hence this is a set condition and Q becomes. Interval t 2 -t 3 : Race Around At instant t 2, J = K = and E = Hence the JK latch is in the toggle mode and Q becomes low () and Q = l. These changed outputs get applied at the inputs of NAND gates 3 and 4 of the JK latch. Thus the new inputs to Gates 3 and 4 are : NAND-3 : J =, E = l, Q = NAND-4 : K =, E =, Q =. Hence R' will become and S' will become. Therefore after a time period corresponding to the propagation delay, the Q and Q outputs will change to, Q = and Q =. These changed output again get applied to the inputs of NAND-3 and 4 and the outputs will toggle again. Thus as long as J = K = and E =, the outputs will keep toggling indefinitely as shown in figure. This multiple, toggling in the J-K latch is called as Race Around condition. It must be avoided. Interval t 3 -t 4 During this interval J =, K = and E =. Hence it is the reset condition. So Q becomes zero. 4 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
Prelim Question Paper Solution 2. (a) Given F(A, B, C, D) = m (, 2, 3, 6, 7, 8, 9, 2, 3) = m (, 4, 5,,, 4, 5) Step : Arranging minterms in groups of s Group (No. of s) Minterm A B C D 4 2 5 3 4 4 5 Step 2: Arranging minterms to form pairs Minterm Group pairs 5 4 5 2 4 3 5 4 5 A B C D Step 3: Arranging minterms to form Quads Prime Implicants ACD ABC Groups Quad pairs A B C D Prime implicants 4 5 AC 4 5 Table of prime implicants Prime Given minterm Minterm Implicants 4 5 4 5 ACD, 5 ABC 4, 5 AC,, 4, 5 can t ignore F(A,B,C,D) = ACD ABC AC F(A,B,C,D) = = ACD ABC AC = (ACD)(ABC)(AC) (ACD)(ABC)(AC) 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 5
: S.E. DLDA Implementation using NAND gates A B C D ACD 2. (b) Full Adder using Half Adder Fig. The full adder circuit can be constructed using two half adders as shown in fig. and the detail circuit is shown in fig.2. A full adder can be implemented using two half adders and the OR gate as shown in fig.2. Fig.2 Now let us prove that this circuit acts as a full adder. Truth table ABC AC (ACD)(ABC)(AC) = F = ACD ABC AC 6 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
3. (a) Proof : Refer Fig. 2 and write the expression for sum output as, S = (A B) C in = A B C in This expression is same as that obtained for the full adder. Now write the expression for carry output C as C = (A B) C in + AB C = (AB AB)C AB in = in in ABC ABC AB = in in in Prelim Question Paper Solution ABC ABC AB( C ) = ABCin ABCin AB ABCin = in in BC (A A) ABC AB = BCin ABCin AB = in in in BC ABC AB( C ) = BCin ABCin AB ABCin = in in BC AB AC (B B) C = BC in AB AC in This expression is same that for a full adder. Thus we have proved that circuit shown in fig.2 really behaves like a full adder. Applications of Full Adder The full adder acts as the basic building block of the 4 bit/8 bit binary/bcd adder ICs such as 7483. The NAND and NOR gates are called as Universal Gates Because it is possible to implement any Boolean expression with the help of only NAND or only NOR gates. Hence a user can build any combinational circuit with the help of only NAND gates or only NOR gates. This is a great advantage because a user will have to make a stock of only NAND or NOR gate ICs. Universal Property NAND Gate The NAND gate can be used to generate the NOT function, the AND function, the OR function, and the NOR function. NOT Function: An inverter can be made from a NAND gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Fig., for a twoinput gate: Fig. : NOT function using NAND gates 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 7
: S.E. DLDA AND Function : An AND function can be generated using only NAND gates. It is generated by simply inverting output of NAND gate; i.e. AB = AB. Fig. 2 shows the two input AND gate using NAND gates. A B AB A B AB AB Table : Truth Table OR Function OR function is generated using only NAND gates as follows : We know that Boolean expression for OR gate is Y = A + B = AB Rule 9 : [AA] Theorem Fig. 2 : AND function using NAND gates = A.B DeMorgan s The above equation is implemented using only NAND gates as shown in the Fig. 3. Fig. 3 : OR function using only NAND gates Note : Bubble at the input of NAND gate indicates inverted input. A B A+B A B A.B A.B Table : Truth table 8 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
Prelim Question Paper Solution NOR Function NOR function is generated using only NAND gates as follows : We know that Boolean expression for NOR gate is Y = AB = A.B = A.B DeMorgan s Theorem 2 Rule 9 : [A A] The above equation is implemented using only NAND gates, as shown in the fig. 4. Fig. 4 : NOR function using only NAND gates A B A B A B A.B A.B A.B Table : Truth Table NOR Gate Similar to NAND gate, the NOR gate is also a universal gate, since it can be used to generate the NOT, AND, OR and NAND functions. NOT Function An inverter can be made from a NOR gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Fig. 5. Fig. 5 : NOT function using NOR gate 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 9
: S.E. DLDA OR Function An OR function can be generated using only NOR gates. It can be generated by simply inverting output of NOR gate; i.e. A B = A + B. Fig. 6 shows the two input OR gate using NOR gates. Fig. 6 : OR function using NOR gates A B A+B A B A B A B Table : Truth table AND Function AND function is generated using only NOR gates as follows : We know that Boolean expression for AND gate is Y = A. B = A.B Rule 9 : [A A] = A B DeMorgan s Theorem 2 The above equation is implemented using only NOR gates as shown in the Fig. 7. Fig. 7 : AND function using NOR gates A B A+B A B A B A B Table : Truth table 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
Prelim Question Paper Solution NAND Function NAND function is generated using only NOR gates as follows : We know that Boolean expression for NAND gate is Y = A.B = A B DeMorgan s Theorem = A B Rule 9 : [A A] The above equation is implemented using only NOR gates, as shown in the Fig. 8. Fig. 8 : NAND function using only NOR gates A B A+B A B A B A B A B Table : Truth table 3. (b) Flip-flops required : 2 n N N = 6 n = 3 i.e., three flip-flops required. Fig. : MOD-6 synchronous p counter FF-A acts as a toggle FF since J A = K A =. Q A output of FF-A is applied to J B as well as K B. Hence if Q A = at the instant of triggering, then FF-B will toggle but if Q A = then FF-B will not change its state. Q A and Q B are ANDed and the output of AND gate is applied to J C and K C. Hence when Q A and Q B both are simultaneously high, then J C = K C = and FF-C will toggle. Otherwise there is no change in the state of FF-3. 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
: S.E. DLDA So in general we can say that each FF should have its J and K inputs connected such that they are high only when the outputs of all lower order FFs are in the high state. Operation Initially all the FFs are in their rest state. Q C Q B Q A = st clock pulse FF-A toggles and Q A changes to from. But since Q A = at the instant o application of st falling clock edge, J B = K B = and Q B does not change state. Q B remains. Similarly Q C also does not change state. Q C = Q C Q B Q A = after st clock pulse 2 nd clock pulse FF-A toggles and Q A becomes. But at the instant of application of 2 nd falling clock edge Q A was equal to. Hence J B = K B =. Hence FF-B will toggle and Q B becomes. Output of AND gate is at the instant of negative clock edge. So J C = K C =. Hence Q C remains. Q C Q B Q A = after the 2 nd clock pulse 3 rd clock pulse After the 3 rd clock pulse, the outputs are Q C Q B Q A =. 4 th clock pulse Note that Q B = Q A =. Hence output of AND gate = and J C = K C =, at the instant of application of 4 th negative edge of the clock. Hence on application of this clock pulse, FF-C will toggle and Q C changes from to. FF-A toggles as usual and Q A becomes. Since Q A was equal to earlier, FF-B will also toggle to make Q B =. Q C Q B Q A = after the 4 th clock pulse Thus the counting progresses. After the 7 th clock pulse the output is and after the 8 th clock pulse, all the flip-flops toggle and change their outputs to. Hence Q C Q B Q A = after the 8 th pulse and the operation repeats. Clock Q C Q B Q A st () 2 nd () 3 rd () 4 th () 5 th () 6 th () 7 th () Fig. 2 2 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
4. (a) Prelim Question Paper Solution Below figure shows the implementation of given Boolean function with 8 : multiplexer. 4. (b) D D D 2 D 3 D 4 D 5 D 6 D 7 A 2 3 4 5 6 7 A 8 9 2 3 4 5 A A A A D D D 2 D 3 D 4 D 5 D 6 D 7 8 : MUX (i) Design a D flip Flop from a RS Flop Next state Q n + S R Inputs Outputs D Present state Q n X X Entries from excitation table of D FF Entries from excitation table of SR FF (ii) JK to T J and K are the actual inputs of the flip flop and T is taken as the external input for conversion. Four combinations are produced with T and Q p. J and K are expressed in terms of T and Q p. The conversion table, K-maps, and the logic diagram are given below. y 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 3
: S.E. DLDA J-K Flip Flop to T Flip-Flop 5. (a) Conversion Table T input Outputs J-K inputs Q p Q p + J K (i) Firstly we have to prepare a table where we have binary (4 bitts, B 3 B 2 B B ) inputs and gray (4 bits G 3 G 2 G G ) outputs (ii) Truth table is, (iii) Now the next step is very simple. You draw Kmaps for G 3, G 2, G and G separately. 4 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
Prelim Question Paper Solution (iv) Kmaps : (v) Circuit : ) A shift register which can shift the data in only one direction is called as a unidirectional shift register. 2) A shift register which can shift the data in both the directions is called as a bidirectional shift register. 3) Applying the same logic, a shift register which can shift the data in both the directions (shift right or left) as well as load it parallely, then it is called as a universal shift register. 5. (b) 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 5
: S.E. DLDA Figure shows the logic diagram of a universal shift register. This shift register is capable of performing the following operations : ) Parallel loading (parallel input parallel output) 2) Left shifting 3) Right shifting The Mode control input is connected to Logic for parallel loading operation whereas it is connected to for serial shifting. With mode control pin connected to ground, the universal shift register acts as a bi-directional register. For serial left operation, the input is applied to the serial input which goes to AND gate- in Figure. Whereas for the shift right operation, the serial input is applied to D input (input of AND gate 8). The well-known example of universal shift register in the IC form is IC7495. Fig. : Logic diagram of a universal shift register 4) Universal Shift Register IC 7495 : General description : IC 7495 is a TTL MSI shift register. It is a 4-bit shift register with serial and parallel synchronous operating modes. Because of its capability to operate in all the possible modes, it is called as a universal shift register. 6 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
Prelim Question Paper Solution Serial Shift Right Operation The connection diagram for serial shift right mode is shown in Figure 2. Make mode control =, therefore AND gates, 3, 5, 7 will be enabled and AND gate 2, 4, 6, 8 will get disabled. Hence the ABCD inputs become don t care. The data input to FF-A is now the serial input. Clock 2 input is don t care. This is because AND gate 9 is enabled and gate is disabled. Apply CLOCK input to clock. A HIGH to low transition on enabled clock input transfers data serially from serial input to Q A, Q A to Q B, Q B to Q C to Q D respectively (right shift). Serial Shift Left Operation The connection diagram of 7495 for the shift left operation is shown in figure 3. Note that Q D is connected to C, Q C to B and Q B to A and the serial data is applied at input D. Clock Serial input 9 CLK 2 7495 Q A Q B Q C Q D 3 2 Fig. 3: 7495 connected for serial shift left operation Mode control is connected to. Hence the AND gates 2, 4, 6, 8 are enabled whereas, 3, 5 and 7 are disabled. This will make the serial input (pin no. ) a don t care input. The serial data is applied to D which will be routed through the enabled AND gates 2, 4, 6, 8 to facilitate the right shifting operation. As M =, AND gate is enabled and gate 9 is disabled. So clock becomes a don t care input. Apply clock pulses to CLK 2 (shift left). Each high to low transition of clock will transfer data from D to Q D, Q D to Q C, Q C to Q B and Q B to Q A. Thus the shift left operation is performed. 6 Mode control = Direction of data shifting Fig. 2: 7495 connected for serial right shifting CLK 2 7495 A Q B B Q B C Q D M D +V CC Mode control = Serial input 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 7
: S.E. DLDA 6. (a) High Speed CMOS The high speed CMOS devices have silicon gates instead of metal gates. This improved version of CMOS ICs has higher switching speeds and higher output current capacity. The high speed CMOS devices are pin compatible and functionally equivalent to TTL ICs with the same device numbers. Comparison of CMOS and TTL Families Parameter CMOS TTL Silicon gate Metal gate 74 74LS 74AS 74ALS CMOS CMOS V IH (min) 3.5 3.5 2. 2. 2. 2. V IL (max)..5.8.8.8.8 V OH (min) 4.9 4.95 2.4 2.7 2.7 2.7 V OL (max)..5.4.5.5.4 V NH.4.45.4.7.7.7 V NL.9.45.4.3.3.4 Propagation Delay (ns) 8 5.5 4 Power per gate (mw).7. 2 8.5 Speed power product or figure or merit.4 pj.5 pj pj 2 pj 2.8 pj 4 pj Input connection Input cannot be left open. It Input can be left open. It is has to be connected to, or treated as logic high input. to V DD or to the another input. More than CMOS. It is Power Very less, but increases with constant, does not depend dissipation increase in switching speed on switching speed. Fan out Fanout is more than TTL typically 5 Fanout for TTL is. Noise More susceptible to noise Less susceptible to noise. 6. (b) De Morgan's theorem : The two theorems suggested by De-Morgen and which are extremely useful in Boolean algebra are as follows : Theorem : AB A B : NAND = Bubbled OR This theorem states that the complement of a product is equal to addition of the complements. This rule is illustrated Fig.. The left hand side (LHS) of this theorem represents a NAND gate with inputs A and B whereas the right hand side (RHS) of the theorem represents an OR gate with inverted inputs. This OR gate is called as "Bubbled OR". Thus we can state De-Morgans first theorem as, NAND = Bubbled OR 8 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
Prelim Question Paper Solution Fig. : Illustration of De-Morgan's first theorem. This theorem can be verified by writing a truth table as shown in Fig.2. A B AB A B A B LHS AB A B RHS Fig. 2 : Verification of the theorem AB A B Theorem 2 : AB A.B : NOR = Bubbled AND The LHS of this theorem represents a NOR gate with inputs A and B whereas the RHS represents an AND gate with inverted inputs. This AND gate is called as "Bubbled AND". Thus we can state De-Morgan's second theorem as : NOR = Bubbled AND Fig. 3 : Illustration of De-Morgan's second theorem. This theorem can be verified by writing a truth table for both the sides of the theorem statement. This truth table is shown in Fig. 4, which shows that LHS = RHS. A B A B A B A.B LHS ABA.B RHS Fig.4 : Truth table to verify De-Morgan's theorem 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 9
: S.E. DLDA 6. (c) Difference between CPLDs & FPGAs CPLDs FPGAs Architecture Large, wide fan-in blocks of AND-OR logic Array of small logic blocks surrounded by I/O Applications Bus interfaces complex state machines fast memory interfaces wide decoders PAL-device integration Logic consolidation board integration replace obsolete devices simple state machines complex controllers / interfaces Key Attributes Fast pin-to-pin performance Predictable timing Easy to use Very high density lots of I/Os and flip-flops generally lower power SRAM devices are reprogrammable. Gate Capacity 3-6, gates 8-, gates Design Timing Fixed, PAL-like very fast pinto-pin performance Application dependent very high shift frequencies Number of I/Os Number of Flip-flops Process Technology In-System Programmable One-Time Programmable (OTP) Power Consumption 3-2 5-4 3-2 -5,5 EPROM EEPROM FLASH Some EEPROM- and FLASH-based devices EPROM devices in plastic packages. Some EEPROMand FLASH-based devices.5-2.w static.5-4.w dynamic SRAM Anti-fuse EEPROM SRAM-based devices and some EEPROM-based devices All anti-fuse-based devices Very low static dynamic consumption is application dependent,.-2w typical 6. (d) () Canonical is a word used to describe a condition of a switching equation. In normal use the work means conforming to a general rule. The rule, for switching logic, is that each term used in a switching equation must contain all of the available input variables. Two formats generally exist for expressing switching equations in a canonical form: Sums of minterms and products of maxterms. (2) Canonical sum of products A canonical sum of products is a complete set of minterms that defines when an output variable is a logical. Each minterm corresponds to the row in the truth table where the output function is ; that is, the SOP for the output M is M = a bms + ab ms + abms (3) Canonical product of sums : A canonical product of sums is a complete set of maxterms that defines when an output is a logical. Each maxterm 2 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln
Prelim Question Paper Solution corresponds to a row in the truth table where the output is a ; that is, the POS for the output O is O = (C + C 2 + C 3 ) (C + C 2 + C 3 ) (C + C 2 + C 3 ) (C + C 2 + C 3 ) (C + C 2 + C 3 ) (4) To place a SOP equation into canonical form using Boolean algebra, we do the following : (i) Identify the missing variable(s) in each AND term. (ii) AND the missing term and its complement with the original AND term, xy(z+z ). Because (Z+Z) =, the original AND term value is not changed. (iii) Expand the term by application of the property of distribution, xyz+xyz. (5) To place POS equation into canonical form using Boolean algebra, we do this : (i) Identify the mission variable(s) in each OR term. (ii) OR the missing term(s) and its complement with the original OR term, x+y+zz. Because zz =, the original OR term value is not changed. (iii) Expand the term by application of distributive property, (x+y+z)(x+y+z). (6) P = f(a, b, c) = ab + ac + bc (SOP) (i) First term, ab, is missing the variable c. So we AND (c+c) with ab: ab = ab (c + c) = abc + abc (ii) Second term, ac, is missing the variable b. So we AND (b+b) with ac. ac = ac (b+b) = abc + abc (iii) Third term is missing the variable a. So we AND (a+a) with bc. bc = bc (a+a) = abc + abc (iv) The final canonical SOP form is P = abc + abc + abc + abc + abc + abc Note that two terms, the second and the fourth, are identical. Only one is needed, because any variable or group of variables ORed with itself is redundant : x + x = x (property of idempotency or sameness). The final equation becomes P = abc + abc + abc + abc + abc (7) (c) T = f(a,b,c) = (a + b)(b + c) (POS) (i) The variable c is missing from the first term. a + b + cc = (a + b + c)(a + b + c) (ii) The variable a is missing from the second term. b + c + aa = (a + b + c)(a + b + c) (iii) The complete equation is T = f(a, b, c) = (a + b + c)(a + b + c)(a + b + c) Features of VHDL (Derived from Capabilities) VHDL has powerful constructs VHDL language supports hierarchy (i.e modelled using a set of interconnected components) 6. (e) 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln 2
: S.E. DLDA VHDL is not case sensitive VHDL supports both synchronous and asynchronous timing models. Concurrency timing and clocking can be modeled using VHDL VHDL is target independent VHDL supports design library VHDL has flexible design methodologies i.e. TOP DOWN, BOTTOM UP, MIXED The logical behavior and timing behavior of the design can be modeled using VHDL. VHDL is not technology specific i.e. VHDL is not dependent on the specific manufacturer i.e. XILINX or LATTICE. VHDL s technology specific feature allows to specify components from various vendors VHDL also allows the user to specify his own data type and component VHDL is publicly available and has no proprietary. 22 3/Engg/SE/Pre Pap/23/CMPN/DLDA_Soln