CpE358/CS38 Switching Theory and Logical Design Class 6 CpE358/CS38 Summer- 24 Copyright 24-585
Today Fundamental concepts of digital systems (Mano Chapter ) inary codes, number systems, and arithmetic (Ch ) oolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch ) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata CpE358/CS38 Summer- 24 Copyright 24-586
Consider This Sequential System: x Input Sequential System S z Output Questions to ask: Is S operating as intended? Was the design correct? Has a failure occurred? Is S the simplest design that generates z for a given x? Are all states necessary? Can S be forced to go to a given state? Are two systems, S and S 2 distinguishable from each other? Reference for today s material: Hennie, Finite State Models for Logical Machines CpE358/CS38 Summer- 24 Copyright 24-587
A Specific Sequential Design Issue Design Verification Does system meet intended system requirements? Does it perform properly over a range of operational conditions? Testing in Manufacture Are there any faults in the product as produced? Field Diagnostics Is the system still working properly? If there is a fault, can it be localized? For each case, how much testing is needed? How much is practical? CpE358/CS38 Summer- 24 Copyright 24-588
X n inputs Sequential Design Testing Combinational Circuit Z m outputs Storage Element(s) k state variables Clock How many tests need to be performed to find all possible faults in system? CpE358/CS38 Summer- 24 Copyright 24-589
X n inputs Sequential Design Testing Combinational Circuit Z m outputs Storage Element(s) k state variables Clock How many tests need to be performed to find all possible faults in system? All storage elements need to be exercised All combinatorial circuit elements need to be tested CpE358/CS38 Summer- 24 Copyright 24-59
X n inputs Sequential Design Testing Combinational Circuit Z m outputs Storage Element(s) k state variables Clock How many tests need to be performed to find all possible faults in system? All storage elements need to be exercised Testing all 2 k states Testing all 2 k! possible state-state transitions All combinatorial circuit elements need to be tested Testing all 2 n input combinations Testing all 2 n input combinations in all 2 k states CpE358/CS38 Summer- 24 Copyright 24-59
X n inputs Sequential Design Testing Combinational Circuit Z m outputs Storage Element(s) k state variables Clock How many tests need to be performed to find all possible faults in system? All storage elements need to be exercised Testing all 2 k states Testing all 2 k! possible state-state transitions ut internal state All combinatorial circuit elements need to be tested is generally not Testing all 2 n input combinations observable! Testing all 2 n input combinations in all 2 k states CpE358/CS38 Summer- 24 Copyright 24-592
Sequential Design Testing d d d 2 d k- a a a 2 a N- N-bit to 2 N line decoder R/W o o o 2 o k- CpE358/CS38 Summer- 24 Copyright 24-593
Sequential Design Testing Do select lines operate correctly? d d d 2 d k- a a a 2 a N- N-bit to 2 N line decoder R/W o o o 2 o k- CpE358/CS38 Summer- 24 Copyright 24-594
Sequential Design Testing Do data lines operate correctly? d d d 2 d k- a a a 2 a N- N-bit to 2 N line decoder R/W o o o 2 o k- CpE358/CS38 Summer- 24 Copyright 24-595
Sequential Design Testing Do output lines operate correctly? d d d 2 d k- a a a 2 a N- N-bit to 2 N line decoder R/W o o o 2 o k- CpE358/CS38 Summer- 24 Copyright 24-596
Sequential Design Testing Are there any cell-to-cell interactions? d d d 2 d k- a a a 2 a N- N-bit to 2 N line decoder R/W o o o 2 o k- CpE358/CS38 Summer- 24 Copyright 24-597
Sequential Design Testing ->= Are there any lingering data effects? ->=.9 d d d ->=.2 2 d k- ->= a a a 2 a N- N-bit to 2 N line decoder R/W o o o 2 o k- CpE358/CS38 Summer- 24 Copyright 24-598
Sequential Design Testing Are there any data pattern effects? d d d 2 d k- a a a N-bit to 2 2 N line decoder a N- R/W o o o 2 o k- CpE358/CS38 Summer- 24 Copyright 24-599
Sequential Design Testing How many test conditions are there for a 2 N word x K-bit memory array? d d d 2 d k- a a a 2 a N- N-bit to 2 N line decoder R/W o o o 2 o k- CpE358/CS38 Summer- 24 Copyright 24-6
Sequential Design Testing How many test conditions are there for a 2 N word x K-bit memory array? 2 NK states, (2 NK )! single state-to-single state transitions d d d 2 d k- a a a 2 a N- N-bit to 2 N line decoder R/W o o o 2 o k- CpE358/CS38 Summer- 24 Copyright 24-6
State Diagram/State Table / Present State Next State/Output Next State/Output A (input ) (input ) A C/ A/ / / A/ C/ C C/ / / C / / Reference for today s material: Hennie, Finite State Models for Logical Machines, Wiley, 968 CpE358/CS38 Summer- 24 Copyright 24-62
Finite State Machine Model X n inputs Combinational Circuit Z m outputs Storage Element(s) Clock CpE358/CS38 Summer- 24 Copyright 24-63
Finite State Machine Model X(t) Input Present state Delayless Combinational Circuit Next state Z(t) Output s(t) Delay, D s(t+) CpE358/CS38 Summer- 24 Copyright 24-64
Finite State Machine Model X(t) Input Present state Delayless Combinational Circuit Next state Z(t) Output s(t) Delay, D s(t+) CpE358/CS38 Summer- 24 Copyright 24-65
Finite State Machine Model X(t) Input Present state Delayless Some Combinational arbitrary combinatorial Circuit logic along with system state information Next state Z(t) Output s(t) Logic functions =? Number Delay, of states =? State transitions D =? s(t+) CpE358/CS38 Summer- 24 Copyright 24-66
Finite State Machine Model X(t) Input Present state Delayless Combinational Circuit Next state Z(t) Output s(t) Delay, D s(t+) x Machine M z CpE358/CS38 Summer- 24 Copyright 24-67
Fundamental Properties of FSMs Accessibility Is state S accessible? x Machine M z / A / / / / / D C / CpE358/CS38 Summer- 24 Copyright 24 / -68
Fundamental Properties of FSMs Distinguishability Can M be distinguished from M 2? A / x z / / / Machine M C / / x z Machine M 2 / / / R S T / / CpE358/CS38 Summer- 24 Copyright 24 / -69
Combinations of Machines x z Machine M Combinational Logic z Machine M 2 z 2 CpE358/CS38 Summer- 24 Copyright 24-6
Combinations of Machines x z Machine M Combinational Logic z Machine M 2 z 2 x Machine M 2 z CpE358/CS38 Summer- 24 Copyright 24-6
Combinations of Machines x Machine M z Recognize String A Machine M 2 z 2 Recognize String Combinational Logic z x Machine M 2 z Recognize Strings A, jointly CpE358/CS38 Summer- 24 Copyright 24-62
Combinations of Machines Recognize strings that have an odd number of s and contain a block of four contiguous s CpE358/CS38 Summer- 24 Copyright 24-63
Combinations of Machines Recognize strings that have an odd number of s and contain a block of four contiguous s State A A A CpE358/CS38 Summer- 24 Copyright 24-64
Combinations of Machines Recognize strings that have an odd number of s and contain a block of four contiguous s State State A A A A A A C C A D D A E E E E CpE358/CS38 Summer- 24 Copyright 24-65
Combinations of Machines Recognize strings that have an odd number of s and contain a block of four contiguous s State State State A A A A AA AA A A C A AC C A D A A A D A E AC AA D E E E A AA C D A AE C A AD AE AE E AD AA E E E AE CpE358/CS38 Summer- 24 Copyright 24-66
Combinations of Machines Recognize strings that have an odd number of s and contain a block of four contiguous s State State State A A A A AA AA A A C A AC C A D A A A D A E AC AA D E E E A AA C D A AE C A AD Machines designed as compositions of two or more machines may be easier to design and maintain AE AD E AE AA E E E AE CpE358/CS38 Summer- 24 Copyright 24-67
Capabilities of FSMs Transform an input signal into an output pattern An arbitrarily long string of periodic inputs must eventually produce a periodic output Systems that do not have this property cannot be built using FSMs Recognize the occurrence of a specific input signal or pattern Intermediate outputs are not important, only the final output CpE358/CS38 Summer- 24 Copyright 24-68
Capabilities of FSMs Transform an input signal into an output pattern An arbitrarily long string of periodic inputs must eventually produce a periodic output Systems that do not have this property cannot be built using FSMs WHY? Recognize the occurrence of a specific input signal or pattern Intermediate outputs are not important, only the final output CpE358/CS38 Summer- 24 Copyright 24-69
Deterministic vs. Nondeterministic FSMs Deterministic: A C D State A C D C C D D D C A Out Known starting state, unique successor states Nondeterministic: A C D State A C C C D,D - Out D D A Unknown/nonunique starting state, nonunique successor states, incomplete specification of machine CpE358/CS38 Summer- 24 Copyright 24-62
Use for Nondeterministic Machines Recognize a sequence that ends with or using a deterministic machine CpE358/CS38 Summer- 24 Copyright 24-62
Use for Nondeterministic Machines Recognize a sequence that ends with or using a deterministic machine Generate basic sequences to be recognized easy to do / b / d / f / h a / c / e / h CpE358/CS38 Summer- 24 Copyright 24-622
Use for Nondeterministic Machines Recognize a sequence that ends with or using a deterministic machine Generate basic sequences to be recognized easy to do Add all other transitions not so simple / / / / b / d / f / h a / / / / / c / e / g / / CpE358/CS38 Summer- 24 Copyright 24-623
Use for Nondeterministic Machines Recognize a sequence that ends with or using a deterministic machine Generate basic sequences to be recognized easy to do Add all other transitions not so simple Derive state table straightforward State / / / a b b b c d / b / d / f / h c d b f e e a / / c / / / / e / / g / e f g h g b b f e h d e CpE358/CS38 Summer- 24 Copyright 24-624
Use for Nondeterministic Machines Recognize a sequence that ends with or using a deterministic machine Generate basic sequences to be recognized easy to do Add all other transitions not so simple Derive state table straightforward Eliminate equivalent states State / / / a b b b c d / / D / F / H c d b f e e A / / C / / / / E / / G / e f g h g b b f e h d e CpE358/CS38 Summer- 24 Copyright 24-625
Use for Nondeterministic Machines Recognize a sequence that ends with or using a deterministic machine Generate basic sequences to be recognized easy to do Add all other transitions not so simple Derive state table straightforward Eliminate equivalent states State / / a b b b c d A / / / C / / / / D / E F / c d e f b f b b e e e d / CpE358/CS38 Summer- 24 Copyright 24-626
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine CpE358/CS38 Summer- 24 Copyright 24-627
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do H I J K G L M N CpE358/CS38 Summer- 24 Copyright 24-628
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do, H I J K G L M N CpE358/CS38 Summer- 24 Copyright 24-629
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do State Convert to deterministic system - mechanical G GH Out, H I J K G L M N CpE358/CS38 Summer- 24 Copyright 24-63
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do State Convert to deterministic system - mechanical G GH GL Out, H I J K G L M N CpE358/CS38 Summer- 24 Copyright 24-63
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do State Convert to deterministic system - mechanical G GH GL Out GH GH, H I J K G L M N CpE358/CS38 Summer- 24 Copyright 24-632
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do State Convert to deterministic system - mechanical G GH GL Out GH GH GIL, H I J K G L M N CpE358/CS38 Summer- 24 Copyright 24-633
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do State Convert to deterministic system - mechanical G GH GL Out GH GH GIL GL GH GLM, H I J K GIL GLM GHJ GHN GLM GLM G GHJ GHN GH GH GILK GIL L M N GILK GHJ GLM CpE358/CS38 Summer- 24 Copyright 24-634
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do State Convert to deterministic system mechanical G GH Eliminate redundant states mechanical GH GH GL GIL Out GL GH GLM, H I J K GIL GLM GHJ GHN GLM GLM G GHJ GHN GH GH GILK GIL L M N GILK GHJ GLM CpE358/CS38 Summer- 24 Copyright 24-635
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do State Convert to deterministic system mechanical G GH Eliminate redundant states mechanical GH GH GL GIL Out GL GH GLM, H I J K GIL GLM GHJ GH GLM GLM G GHJ GH GIL L M N CpE358/CS38 Summer- 24 Copyright 24-636
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do State Convert to deterministic system mechanical A (G) Eliminate redundant states mechanical (GH, GHN) Convert from Moore to Mealy machine, rename states C (GL) C D E, H I J K D (GILK, GIL) E (GLM) F E E G F (GHJ) D L M N CpE358/CS38 Summer- 24 Copyright 24-637
Use for Nondeterministic Machines Recognize a sequence that ends with or using a nondeterministic machine Generate basic sequences to be recognized easy to do Add nondeterministic transitions easy to do State Convert to deterministic system mechanical A (G) Eliminate redundant states mechanical (GH, GHN) Convert from Moore to Mealy machine, rename states C (GL) C D E, H I J K D (GILK, GIL) E (GLM) F E E G F (GHJ) D L M N State a b b b c d Results in equivalent machine with less effort c b e d f e e b e CpE358/CS38 Summer- 24 Copyright 24 f b d -638
Experiments on FSMs Synchronizing Sequences Consider the machine with the state table: State A C D E A C C C D E E C What is the final state if the input is? CpE358/CS38 Summer- 24 Copyright 24-639
Experiments on FSMs Synchronizing Sequences Consider the machine with the state table: State A C D E A C C C D E E C What is the final state if the input is for each initial state? A: A CpE358/CS38 Summer- 24 Copyright 24-64
Experiments on FSMs Synchronizing Sequences Consider the machine with the state table: State A C D E A C C C D E E C What is the final state if the input is for each initial state? A: A > > > : > > > C: C > A > > D: D > C > A > E: E > C > A > CpE358/CS38 Summer- 24 Copyright 24-64
Experiments on FSMs Synchronizing Sequences Consider the machine with the state table: State A C D E A C C C D E E C What is the final state if the input is for each initial state? A: A > > > : > > > C: C > A > > D: D > C > A > E: E > C > A > is a synchronizing sequence for this machine, always leading it to state CpE358/CS38 Summer- 24 Copyright 24-642
Experiments on FSMs Homing Sequences Given a user selected input sequence X i, observing only Z i, can the final state of M be determined? If X i exists, it is a homing sequence x Machine M z Homing sequences can be used to test the behavior of M CpE358/CS38 Summer- 24 Copyright 24-643
Experiments on FSMs Distinguishing Sequences Given a user selected input sequence X i, observing only Z i, can the initial state of M be determined? If X i exists, it is a distinguishing sequence x Machine M z Distinguishing sequences can be used to test the behavior of M CpE358/CS38 Summer- 24 Copyright 24-644
Distinguishing vs. Homing Sequences Every distinguishing sequence is a homing sequence Not all homing sequences are distinguishing sequences CpE358/CS38 Summer- 24 Copyright 24-645
Distinguishing vs. Homing Sequences Every distinguishing sequence is a homing sequence x D z allows determination of S Machine M S with input x D > S F Not all homing sequences are distinguishing sequences CpE358/CS38 Summer- 24 Copyright 24-646
Distinguishing vs. Homing Sequences Every distinguishing sequence is a homing sequence x D z allows determination of S Machine M S with input x D > S F Not all homing sequences are distinguishing sequences x H Machine M z allows determination of S F S A with input x H > S F, but S with input x H > S F, CpE358/CS38 Summer- 24 Copyright 24-647
Distinguishing vs. Homing Sequences Consider: State A C D E D D E E C E A C CpE358/CS38 Summer- 24 Copyright 24-648
Distinguishing vs. Homing Sequences Consider: State Initial State Output for input Final State A C A D E C C D A C C D E D C E E C E Each output is different, depending on the initial state. is a distinguishing sequence. It is also a homing sequence final state is known CpE358/CS38 Summer- 24 Copyright 24-649
Distinguishing vs. Homing Sequences Consider: State Initial State Output for input Final State A C A D E C C D A C E D E D E E C E Each output is NOT different, depending on the initial state (e.g., states A and D). is a NOT distinguishing sequence. ut it is a homing sequence final state is known CpE358/CS38 Summer- 24 Copyright 24-65
Machine Identification Checking Sequences Are M X, a machine as observed, equivalent to M D, a machine whose operation is known? Is M X operating as designed (M D )? x Machine M X z x Machine M D z CpE358/CS38 Summer- 24 Copyright 24-65
Machine Identification Checking Sequences Are M X, a machine as observed, equivalent to M D, a machine whose operation is known? Is M X operating as designed (M D )? x Machine M X z x Machine M D z It is not always possible to distinguish two different machines The checking sequence can quickly become unmanageable CpE358/CS38 Summer- 24 Copyright 24-652
Checking Sequences Consider: M : State A A A M x is either M or M 2. M 2 : State A A C C C CpE358/CS38 Summer- 24 Copyright 24-653
Checking Sequences Consider: M : State A A A M x is either M or M 2. Starting state M 2 : State input ut: M (A,S) = M 2 (,S) A A C C C CpE358/CS38 Summer- 24 Copyright 24-654
Checking Sequences Consider: M : State A A A M x is either M or M 2. Starting state M 2 : State input ut: M (A,S) = M 2 (,S) A A C C C Without knowing starting state, M and M 2 cannot be distinguished CpE358/CS38 Summer- 24 Copyright 24-655
Checking Sequences Can the state table of a system be completely determined without internal knowledge of the system? CpE358/CS38 Summer- 24 Copyright 24-656
Checking Sequences Can the state table of a system be completely determined without internal knowledge of the system? Generally, no: Any test sequence of length N that allows determination of a state table of machine M A can be recognized by M with more states it takes an infinitely long sequence to avoid this possibility. CpE358/CS38 Summer- 24 Copyright 24-657
Summary Fundamental concepts of digital systems (Mano Chapter ) inary codes, number systems, and arithmetic (Ch ) oolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch ) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata CpE358/CS38 Summer- 24 Copyright 24-658
Homework 6 due in Class 8 There is no class 8 CpE358/CS38 Summer- 24 Copyright 24-659