Nanoelectronics Research Initiative Sanjay Banerjee Director, Microelectronics Research Center and SWAN University of Texas Jeff Welser, Director, NRI Ralph Cavin, SRC NRI Goals Case Study: SWAN NRI-NSF Collaboration
The Other Energy Crisis!
Semiconductor Research Corporation A Family of Distinct, Related Program Entities New & Emerging Research Initiatives Global Research Collaboration Ensuring vitality of current industry Focus Center Research Program Breaking down barriers to extend CMOS to its limits Nanoelectronics Research Initiative Beyond CMOS identifying next information element Energy Research Initiative Emphasis on Photovoltaic and Smart Grid technologies National Institute for Nano- Engineering Nanoengineering collaboration with Sandia Education Alliance Attracting and educating the next generation of innovators and technology leaders 3
Beyond CMOS Logic: What to look for? To beat the power problem requires: A device with a lower energy, room temperature switching mechanism or A system that operates out of equilibrium or recovers operation energy as part of the logic computation Required characteristics: Scalability Performance Energy efficiency Gain Operational reliability Room temp. operation Preferred approach: CMOS process compatibility CMOS architectural compatibility Alternative state variables Spin electron, nuclear, photon Phase Quantum state Magnetic flux quanta Mechanical deformation Dipole orientation Molecular state 4
ITRS- Emerging Research Devices http://www.itrs.net/links/2005itrs/home2005.htm SWAN
NRI Primary Research Vectors NEW DEVICE Device with alternative state vector NEW WAYS TO CONNECT DEVICES Non-charge data transfer NEW METHODS FOR COMPUTATION Non-equilibrium systems B A C Out NEW METHODS TO MANAGE HEAT Nanoscale phonon engineering NEW METHODS OF FABRICATION Directed self-assembly devices 6
NRI Funded Universities Finding the Next Switch Notre Dame Illinois-UC Michigan Cornell Purdue Penn State UT-Dallas GIT SUNY-Albany GIT Harvard Purdue RPI Columbia Caltech MIT NCSU Yale UVA (co-funds all 4 centers) UC Los Angeles UC Berkeley UC Irvine UC Santa Barbara Stanford U. Denver Portland State U. Iowa U. Nebraska-Lincoln U. Wisconsin-Madison UT-Austin Rice Texas A&M UT-Dallas ASU Notre Dame U. Maryland NCSU Illinois UC Over 35 Universities in 22 States Brown Caltech Columbia Harvard Illinois-UC MIT/U. Virginia Nebraska-Lincoln Northwestern Penn State Princeton / UT-Austin Purdue Stanford U. Alabama UC Berkeley U. Maryland 8
Post CMOS Device Examples Graphene Bilayer pseudospin FET UT Austin Graphene PN Junction SUNY Albany All-Spin Logic Purdue U. V n V Gn B F C z y U= 0 A U = 1 x (a) V p V Gp Nanomagnet Logic Notre Dame, Berkeley A C 0.000 Spin-Torque Device UCLA H 12 o Co 60 Fe 20 B 20 MgO Co 40 Fe 40 B 20 Ru Co 70 Fe 30 PtMn +I dc B R ( k ) D 8 7 6 5 4 Heterojunction TFET Penn. State, Notre Dame T = 100 K H = 1.4 koe 3-100 0 100 200 8 6 Direct current ( A) T = 100 K H = 1.4 koe 9
Phonon Frequency (cm -1 ) South West Academy of Nanoelectronics Task 1: Logic Devices with Alternate State Variables Task 2:Novel Materials and Structures A B Out x Pseudospintronics on Graphene: UT, UTD, Maryland A=0 DMS: A&M, Maryland, UT C MQCA:ND Precession of phase + C A=0, B=0 C=0 B=0 A=0, B=1 C=1 A=1, B=0 C=1 A=1, B=1 C=0 Phasetronics: UT Path Integral Monte Carlo: ASU, UT Task 3: Nanoscale Thermal Management UIUC, NCSU Graphene Monolayer Task 4: Nano plasmonic interconnects Rice Task 5: Nanoscale Characterization UTD Γ K M Γ
Bilayer pseudospin FET Room temp. condensation in graphene a perfect storm of material properties: electron-hole symmetry low DOS gapless mono-atomically thin layers Simulated devices and basic logic gates in SPICE Inverter with complementary BiSFET design simulated at f CLK = 100 GHz V DD = 25 mv E inverter = 0.008 aj just 2x the Landauer limit 11
Coulomb Drag in Graphene Bilayers Positive drag resistance for electron-hole pairing, negative resistance for e-e or h-h momentum transfer Drag ( ) 2 1 0-1 250K 200K 150K 100K 077K 050K 020K 004K Coulomb drag results repeated for multiple BiSFET samples at room temperature Weaker temperature dependence of drag resistance instead of T 2 dependence predicted by Fermi liquid theory suggestive of disorder in graphene -2-20 -10 0 10 20 V BG (V)
NRI Benchmarking: Sample Data 1E-25 1E-26 1E-27 1E-28 1E-29 Preferred Corner 1E-30 Lines of EDP Equivalence 15
NRI Benchmarking: Device vs Transport Delay Metric * * Characteristic transport delay over 10 um 16
NRI-NIST Collaborations NRI Projects at NIST Labs PI Center Project NIST Collaborator Alan Seabaugh Graphene and III-V TFET Metrology (Qin Zhang) John Suehle & Curt Richter Gary Bernstein SEMPA measurements on nanomagnets Unguris Eric Pop Noise measurements in carbon nanotubes Curt Richter Suman Datta High Speed TFET Id-Vgs measurements John Suehle Bob Wallace Correlation TFET interface and electrical properties John Suehle & Curt Richter Michael Flatte Semiconductor Spin FET Devices Paul Haney & Mark Stiles Barry Zink Measuring Thermal Spin Currents and Torques Matt Pufall Jim Harris Coupled Spin Torque Devices for Logic Glenn Solomon Ji Ung Lee STM Characterization of Graphene PN Junctions Joseph Stroscio Karl Berggren He Ion Microscope for sub-10nm Lithography & Metrology Andras Vladar & Mike Postek Alain Diebold Brillouin Light Scattering Ward Johnson Phillip First Atomic-scale electrical metrology of nano-patterned graphene Joseph Stroscio Allan MacDonald STM Studies of Bilayer Graphene Joseph Stroscio NIST-sponsored post-doc from MIND working at NIST on tunnel-device metrology 17
NSF-NRI Projects Co-funding 18 Projects at 15 NSF Centers Brown MRSEC Caltech MRSEC Columbia NSEC Harvard NSEC Illinois-Urbana Champaign NSEC MIT MRSEC (UVA) Nebraska-Lincoln MRSEC Northwestern MRSEC Penn State MRSEC Princeton MRSEC (UT-Austin) Purdue NCN Stanford NSEC U Alabama MRSEC UC-Berkeley NSEC U Maryland MRSEC 2009: Direct Write Synthesis of Graphene Devices 2008: Graphene Atomic Switches for Ultracompact Logic Devices and NV Memory 2008: Graphene Devices: Electron Wavefunction Focusing & Pseudospin Switching 2010: Graphene Hybrid Devices: Implementing Novel Quantum Switches 2008: Tunable Ultra-fast Conductance Switching through External Fields 2010: Anisotropic and Environment-Limited Thermal Conduction in Flexible Nanotube Arrays and Graphene Sheets 2009: Reconfigurable Array Magnetic Automata (RAMA) 2010: Study and Control of Intrinsic Magnetization at the Boundary of a Magnetoelectric Material for Electrically Switchable Magnetic Nanostructures 2009: Generating, Probing, and Manipulating Excitons in Carbon Nanomaterials 2010: Very Low Energy Dissipation Computing using Inter-band Tunneling Injected Non-equilibrium Ballistic Carriers 2010: Quantum Coherence in Graphene Bilayers 2008: Experimental Realization of Low-power Transistors with Negative Capacitors 2009: Exploration of Novel All-Spin Logic (ASPL) for Device-Circuit-Architecture 2008: (UI-UC) Ultra-Low Power Pseudospintronic Switching in Bilayer Graphene 2010: Info Processing & Cognitive Computing with Neuromorphic Elec. Synapses 2009: Spintronic Logic Devices 2009: Spin-Oscillators for Non-Charge Based Ultra Low Power Logic and Comm. 2008: Controlling the Electronic Properties of Graphene
NRI Benchmarking General Observations: Benchmarking is a Tool not a Weapon! Information Token Spin waves Spin (Single / Few) Magnetic Field (Collective Spin) PseudoSpin Heat Excitons Plasmons Charge Drift Transport Mechanism Diffusion Ballistic Transport Spin Conduction Electromagnetic Waves Simple Conduction Band Transport EM quasi-particle in surface plasmonpolariton mode Maturing of devices over the past year; more understanding of intrinsic responses Substantial clustering of data across multiple tokens Token transfer (interconnect) becoming even more important Can influence relative device value NRI Architecture results make clear the emerging need for parallelism Important for teams to add circuit designers and to consider non-von Neumann and/or application-specific architectures Positive Sign: Schematics and SPICE now regularly appear in PI reports No clear winner but clearer understanding of device capability has emerged Primary advantages: Power, Area; Primary challenges: Speed Increased focus on circuit implementations to take advantage of novel device attributes (e.g. non-volatility, complex functions) required Will continue to refine benchmark process to include relevant parameters not eliminating ideas based solely on our current CMOS-based metrics 19
New NRI-NSF NIRT Solicitation http://www.nsf.gov/pubs/2010/nsf10614/nsf10614.htm?org=nsf NRI-NSF preparing a joint solicitation to support the NNI s Signature Initiative on Nanoelectronics for 2020 and Beyond (http://www.nano.gov/html/research/signature_initiatives.html) Three NSF Directorates: Engineering (ENG), Mathematical and Physical Sciences (MPS), and Computer & Information Science & Engineering (CISE) Three primary thrusts, building off NRI s mission and recent NSF workshop on Interdisciplinary Challenges beyond the Scaling Limits of Moore's Law. (http://www.nnin.org/nnin_nsf_workshop_2010.html) 1. Exploring New Chemistries and Materials for Nanoelectronics 2. Exploring Alternative State Variables and Heterogeneous Integration for Nanoelectronic Devices and Systems 3. Exploring Novel Paradigms of Computing Awards will be for Nanoscale Interdisciplinary Research Teams (NIRTs) NIRT is typically a small university team (3-4 PI's) working on a joint research project, where the members must come from more than one discipline Total funding: $20.1M over 4 years Award size is ~$1-2M per team over 4 years ($250-500K/yr) 10-15 awards 20
New NRI-NSF NIRT Solicitation http://www.nsf.gov/pubs/2010/nsf10614/nsf10614.htm?org=nsf Solicitation Schedule: Program Solicitation Dissemination September 2010 Proposal deadline January 19, 2011 Proposal Panels April/May 2011 Jackets to DGA June 2011 Date of awards August 2011 NRI-NSF Joint Management Plan for award selection Program selection will include NSF peer review panels, as well as consultation with NRI No connection to NSF or NRI existing centers is necessary; no NRI recommendation letter is needed NRI and NSF will jointly oversee the jointly-funded NIRTs Annual reports to be delivered to NSF and NRI Submission of all publications to NRI website Annual visit from NRI Liaison Team Participation in the NRI annual review 21
Nanoelectronics Research Initiative 2010 Transition to Next Phase NRI Mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe Thousand Flowers Bloom (2005-2010) Phase 1: Many, moderate-size projects exploring new science/technology Cultivating Flowers (2011 and beyond) Phase 1.5: Choose 8-10 promising devices/architectures for more focused research (2011-2012) Phase 2: Focus on 1-2 devices for larger-scale work (2013-) NRI finishing its final year of Phase 1.0 (4/1/10-3/31/11) NRI-NIST centers focusing well on specific device areas NRI-NSF projects continue to support the centers and maintain breadth Working NRI Phase 1.5 Extension All industry members and NIST & NSF plan to continue Completing Benchmarking effort and Onsite Reviews to jointly choose most promising NRI devices for increased focus (~2-3 per NRI center) 22
NRI Extension: Phase 1.5 RFP Content Phase 1.5 Technical Plan: Each center focuses on 2-3 specific devices with expanded teams to cover all areas to implement computation Novel materials development, growth, and characterization Specific work on self-assembly or novel fabrication techniques, if required Physics theory and experimental verification of key phenomena, including work on phonon / heat flow for novel cooling and/or non-equilibrium behavior Device modeling, design, fabrication and characterization Novel circuit & architecture work to take advantage of unique device properties (e.g. non-volatility / built-in memory) for low-energy or energyrecovery during operation Phase 1.5 desired outcome: Produce sufficient data on each device to see if it could pose a viable option for extending scaling beyond CMOS Proposal Timetable Event Deadline Publication of Request for Proposal August 1, 2010 Deadline to Submit Proposals to NERC October 16, 2010 Awards Announced December, 2010 Award Start Date First quarter, 2011 23