ECEN 610 Mixed-Signal Interfaces

ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 014 S. Hoyos-ECEN-610 1

Sample-and-Hold Spring 014 S. Hoyos-ECEN-610

ZOH vs. Track-and-Hold V(t) Zero acquisition time Infinite bandwidth 0 T T T t Not realistic V(t) H T H T H T H T H T 0 T T T/ t T/ acquisition time Finite bandwidth Practical Spring 014 S. Hoyos-ECEN-610 3

A Simple T/H Ф V i R S C S R on V Tp PMOS NMOS V Tn R 1 on C ox W L V DD V th V i CMOS 0 V i V DD MOS technology is naturally suitable for implementing T/H. The lowpass SC network determines the tracking bandwidth of the T/H. Top-plate sampling leads to signal-dependent switch on-resistance. Spring 014 S. Hoyos-ECEN-610 4

Tracking Bandwidth (TBW) R S R on Ron V i C S TBW 1 R R S on CS 0 V i V DD Tracking bandwidth determines how promptly can follow V i. Typically TBW is many times greater than the max signal bandwidth. Spring 014 S. Hoyos-ECEN-610 5

Dispersion H(jω) 1 Magnitude response Non-uniform phase delay 0 ω 0 ω Non-uniform group delay H(jω) 0-45 -90 ω 0 ω Phase delay : H j t p Group delay : t g dh j d Spring 014 S. Hoyos-ECEN-610 6

Dispersion R S R on V i C S t t Waveform distortion mainly due to non-uniform phase- and group-delay. Shape of waveform not very sensitive to the lowpass magnitude response as long as the signal bandwidth is on the order of the TBW. Spring 014 S. Hoyos-ECEN-610 7

Signal-Dependent R on Ф V i R S C S R on V Tp PMOS NMOS V Tn R 1 on C ox W L V DD V th V i CMOS 0 V i V DD Top-plate sampling leads to signal-dependent switch on-resistance signal-dependent TBW extra waveform distortion. Signal-dependent R on and dispersion are both insignificant if TBW is sufficiently large (>> f in, depending on the T/H accuracy). Spring 014 S. Hoyos-ECEN-610 8

Ideal T/H V(t) Hold Track Hold t Sufficient tracking bandwidth negligible tracking error Well-defined sampling instant (asserted by clock rising/falling edge) Zero track- and hold-mode offset errors Spring 014 S. Hoyos-ECEN-610 9

T/H Errors (Track Mode) V(t) δ 1 δ Droop Δt Hold Track Hold t Finite tracking bandwidth tracking error, T/H memory Track-mode offset (can be signal-dependent) Spring 014 S. Hoyos-ECEN-610 10

Acquisition Time (t acq ) R S R on Accuracy t acq V i C S 1% (7b) 5 0.1% (10b) 7 1 TBW R R S on CS 0.01% (13b) 9 R on C ox W L 1 V V V ox DD th i ch DD th i C L WL V V V L Q Short L, thin t ox, large W, large v, small V i all help reduce R on. Spring 014 S. Hoyos-ECEN-610 11

T/H Errors (T-to-H Transition) V(t) δ 1 δ Droop Δt Hold Track Hold t Pedestal error (often signal-dependent) resulted from switch turn-off nonidealities (clock feedthrough and charge injection). Aperture delay the delay Δt b/t the hold command and the hold action Aperture jitter the random variation in Δt (i.e., sampling clock jitter) Spring 014 S. Hoyos-ECEN-610 1

Sampling Switch CF and CI Ф Z i C gs C gd ut Ф V DD 0 V in +V th V in Q ch C S Switch on Switch off Fast turn-off Slow turn-off Clock feedthrough Cgs V C C C gs S V DD Charge injection V C ox WL V C gs V Vin V V 0 th Cgs CS DD gs V C th S V in Spring 014 S. Hoyos-ECEN-610 13

Spring 014 S. Hoyos-ECEN-610 14 T/H Pedestal Error th DD S gs ox DD S gs gs i S gs ox o os i o V V C C WL C V C C C V C C WL C V V V V 1 1 1 1 th S gs gs i S gs gs o os i o V C C C V C C C V V V V 1 1 Slow turn-off: Fast turn-off:

T/H Speed-Accuracy Tradeoff Pedestal error: 1 V Q C ch S TBW: TBW 1 Q R C L C on S ch S Therefore: V TBW 1 Q C ch S L CS L Q ch Technology scaling improves T/H performance! Spring 014 S. Hoyos-ECEN-610 15

Aperture Delay (Δt) CH 1 Φ 1 V Φ 1 in CH Φ Φ Fixed aperture delay is usually not of problem in a single-channel T/H. Non-uniform aperture delay among interleaved T/H channels are the dominant sampling error source (Δt 1, Δt are also called sampling clock skew) Spring 014 S. Hoyos-ECEN-610 16

Aperture Jitter V(t) dv dt δv Track δt Hold t Ref: M. Shinagawa, Y. Akazawa, and T. Wakimoto, "Jitter analysis of high-speed sampling systems," IEEE Journal of Solid-State Circuits, vol. 5, pp. 0-4, issue 1, 1990. Spring 014 S. Hoyos-ECEN-610 17

Aperture Jitter V i t Asin t t Asint cost Acost sint Asin Asin t 1 sin Acost t t Acost for smallt. t V t Asint t Acost i T A t 1 T t t A cost 0 t dt A t t sin cos t "Cyclostationary" SNR A 1 t t A Spring 014 S. Hoyos-ECEN-610 18

Aperture Jitter 140 10 100 = 0.1ps t t = 1ps = 10ps t = 100ps t SNR [db] 80 60 40 0 SNR 0 LOG10 πfσ t 0 10 6 10 7 10 8 10 9 Input Freq [Hz] Spring 014 S. Hoyos-ECEN-610 19

T/H Errors (Hold Mode) V(t) δ 1 δ Droop Δt Hold Track Hold t Hold-mode droop caused by off-switch/diode/gate leakage Hold-mode input feedthrough (i.e., due to capacitive coupling) Spring 014 S. Hoyos-ECEN-610 0

Evaluating T/H Performance kt/c noise: V N 4kTR 0 1 1 jf RC S df kt C S T = 300K C S kt/c SNDR: SNDR V i V N A t V 1pF 100pF 10fF 64μV 6.4μV 640μV Noise Jitter Distortion Spring 014 S. Hoyos-ECEN-610 1

CMOS S/H Spring 014 S. Hoyos-ECEN-610

Top-Plate Sampling R S Ф V i C S Pros Simple, minimum number of devices Wideband, zero track-mode offset Cons Signal-dependent tracking bandwidth Signal-dependent charge injection and clock feedthrough Signal-dependent aperture delay (sampling point) Spring 014 S. Hoyos-ECEN-610 3

CMOS Switch Ф R on PMOS NMOS V i V Tp V Tn Ф C S CMOS 0 V i V DD R on of the NMOS and PMOS devices complement each other. R on still depends on V in and is sensitive to N/P matching. Large parasitic capacitance due to PMOS switch. Spring 014 S. Hoyos-ECEN-610 4

Clock Bootstrapping Φ Φ R on In V DD M 1 Out 0 V i V DD Constant gate overdrive voltage V GS = V DD for the switch. R on to the first order does not depend on V in. NMOS device only, less parasitic capacitance. Spring 014 S. Hoyos-ECEN-610 5

Clock Bootstrapping Ref: A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline ADC," IEEE Journal of Solid-State Circuits, vol. 34, pp. 599-606, issue 5, 1999. Spring 014 S. Hoyos-ECEN-610 6

Dummy Switch Ф Ф V i W W L C S L Initial size of dummy chosen with the assumption of a 50/50 split of Q ch ; usually (W/L) dummy < ½(W/L) switch in practice. The nonlinear dependence of CI on Z i, C S, and clock slew rate makes it difficult to achieve a precise cancellation. Ф_ rising edge must trail Ф falling edge. Spring 014 S. Hoyos-ECEN-610 7

Balanced Switch + Dummy Ф Ф V i C S W W L C S L TBW Parasitics Ref: L. A. Bienstman and H. J. De Man, "An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling," IEEE Journal of Solid-State Circuits, vol. 15, pp. 1051-9, issue 6, 1980. Spring 014 S. Hoyos-ECEN-610 8

Signal-Dependent Aperture Delay V DD Ф V th (V i ) Switch on 0 V i +V th (V i ) Switch off V V i o t t Asin t, V i Asin t SR t Non-uniform sampling due to signal-dependent aperture delay causes distortion. Large slew-rate (SR) of clock edge and small V in mitigate the effect. Spring 014 S. Hoyos-ECEN-610 9

Signal Distortion V o t Vi Asin t SR Asin V SR Asin V SR V i o SR Asin t t Acos SR i t cos Acost i i t Acost for small. i t V t V t Acost SR Vi sin SR V SR 1 t A sint nd -order SDR A A SR A SR Spring 014 S. Hoyos-ECEN-610 30

Fully-Differential T/H Ф V i + M 1 C S + + f in 0.5GHz V DD 1.8V t f 0.1ns V i - M C S - - A 0.5V SDR (SE) 4.dB SDR (DIFF)? All even-order distortions are cancelled, including the signal-dependent aperture delay-induced distortion. Actual cancellation is limited by the P/N mismatch (1-10% typically). Spring 014 S. Hoyos-ECEN-610 31

Bottom-Plate Sampling Ф C S X V i Ф Ф e Ф e Ф Bottom-plate switch opens slightly earlier than the top-plate switches. CF and CI of switch Φ e are much less signal-dependent! Bootstrapping the top-plate switch further helps. For A/D converters of more than 8-bit resolution. Less tracking bandwidth due to more switches in series. Signal swing at node X is not completely zero! Spring 014 S. Hoyos-ECEN-610 3

Sample-and-Hold Amplifier (SHA) Spring 014 S. Hoyos-ECEN-610 33

Flip-Over SHA V i + Ф 1 C S + Ф 1e Ф + Ф 1 Ф 1e V i - Ф 1 C S - Ф 1e Ф - Ф T H CMFB not shown Non-inverting, 1X closed-loop gain Nonoverlapping two-phase clock with early sampling phase CF and CI to the 1 st order independent of V in and cancelled differentially Large open-loop gain of op-amp ensures the linearity of the SHA. Spring 014 S. Hoyos-ECEN-610 34

Inverting SHA C H + V i + V i - Ф 1 Ф Ф 1 C S + C S - Ф 1e Ф 1 Ф 1 Ф Ф + - CMOS or bootstrapped switches are required when passing signals with large swing C H - Closed-loop gain determined by the ratio C S /C H (mismatch?) Ref: R. C. Yen and P. R. Gray, A MOS switched-capacitor instrumentation amplifier, IEEE Journal of Solid-State Circuits, vol. 17, pp. 1008-1013, issue 6, 198. Spring 014 S. Hoyos-ECEN-610 35

Inverting SHA (Track-Mode) C H + V i + V i - Ф 1 C S + C S - Ф 1e Ф 1 Ф 1e W L Ф 1e W L/ W L/ Ф 1 Ф 1 C H - CF and CI to the 1 st order independent of V in and cancelled differentially Φ 1e switch is equivalent to two switches of L/ channel length. Spring 014 S. Hoyos-ECEN-610 36

Inverting SHA (Hold-Mode) C H + Ф C S + C S - Ф Ф + - CM DM C H - For 1X gain, the feedback factor (β) is half that of the flip-over SHA. Floating switch Φ in hold-mode flexible input common mode Useful for single-ended to differential conversion Spring 014 S. Hoyos-ECEN-610 37

Equivalent Circuits (Hold-Mode) C H Ф C H Ф C S C S V i,dm A dm + Ф + V i,cm A cm DM CM Floating switch Φ in hold-mode flexible input common mode Useful for single-ended to differential conversion Spring 014 S. Hoyos-ECEN-610 38

AZ Flip-Around SHA Ф 1 + C Ф S Ф 1e + + V i s V i - Ф 1 C S - Ф Ф 1e - Bottom-plate sampling Op-amp offset compensated by autozeroing Stability in track-mode and fast settling in hold-mode Spring 014 S. Hoyos-ECEN-610 39

Closed-Loop SHA Ф Ф C S V i A 1 X A A two-stage Miller-compensated op-amp well-known design CF and CI to the 1 st order independent of V in if A is large (V X 0) always active and valid Large slew-rate of A 1 needed for fast tracking Ref: K. R. Stafford et al., "A complete monolithic sample/hold amplifier," IEEE Journal of Solid-State Circuits, vol. 9, pp. 381-387, issue 6, 1974. Spring 014 S. Hoyos-ECEN-610 40

Open-Loop SHA Ф Ф Ф 1 Ф C S V i W L C S W L 1X V i Ф 1 Ф 1e 1X Top-plate sampling Bottom-plate sampling Typically 1X buffer gain to widen the TBW Can utilize either top-plate (faster) or bottom-plate sampling Suitable for very high-speed, low-resolution S/H applications. Spring 014 S. Hoyos-ECEN-610 41

Interpolation Spring 014 S. Hoyos-ECEN-610 4

Interpolation V i V R 1 V R 1 1 3 V R 3 3 V R 1 V R V R 3 Uniformly spaced zero-crossings in flash ADCs Ref: R. van de Grift, I. W. J. M. Rutten, and M. van der Veen, "An 8-bit video ADC incorporating folding and interpolation techniques," IEEE Journal of Solid-State Circuits, vol., pp. 944-953, issue 6, 1987. Spring 014 S. Hoyos-ECEN-610 43

Resistive Interpolation V i V R 1 1 1 3 V R 3 3 V R 1 V R V R 3 Intermediate zero-crossings are recovered by interpolation. DNL is improved by voltage interpolation. Requires overlapped linear regions b/t adjacent preamps. Spring 014 S. Hoyos-ECEN-610 44

Interpolation Nonlinearity A V A V B /4+V A *3/4 V A /+V B / V B *3/4+V A /4 A B B V B Nonlinear TF of preamps cause errors in the interpolated zero-crossings. Interpolation nonlinearity directly translates into DNL and INL. Impedance mismatch due to interpolation also causes dynamic errors. Spring 014 S. Hoyos-ECEN-610 45

Interpolation Nonlinearity A R R/4 R/4 V A V B /4+V A *3/4 V A /+V B / V B *3/4+V A /4 Interpolation factor of 4 Latch input bandwidth equalized Critical if input SHA is not used B R V B Nonlinear interpolation errors remain Ref: R. J. van de Plassche and P. Baltus, "An 8-bit 100-MHz full-nyquist analog-todigital converter," IEEE Journal of Solid-State Circuits, vol. 3, pp. 1334-1344, issue 6, 1988. Spring 014 S. Hoyos-ECEN-610 46

Interpolation Nonlinearity A V A B V B /4+V A *3/4 V A /+V B / V B *3/4+V A /4 V B Resistive mesh network improves impedance matching at latch input. X interpolation avoids the interpolation error. Ref: P. Vorenkamp and R. Roovers, "A 1-b, 60-MSample/s cascaded folding and interpolating ADC," IEEE Journal of Solid-State Circuits, vol. 3, pp. 1876-1886, issue 1, 1997. Spring 014 S. Hoyos-ECEN-610 47

Capacitive Interpolation K. Kusumoto, JSSC, Dec. 1993 Spring 014 S. Hoyos-ECEN-610 48

Current Interpolation Less accurate than voltage interpolation due to mismatch of current mirrors Ref: M. Steyaert, R. Roovers, and J. Craninckx, "100 MHz 8 bit CMOS interpolating A/D converter," in Proceedings of IEEE Custom Integrated Circuits Conference, 1993, pp. 8.1.1-8.1.4. Spring 014 S. Hoyos-ECEN-610 49

Features of Interpolation Reduces the total number of preamps by the interpolation factor. Total number of latches stay the same. Reduces the total input capacitance (larger input BW). More area- and power-efficient than straight flash ADC. Voltage interpolation improves DNL. Loading of interpolation network decreases the preamp gain/bw. Subject to preamp nonlinearities. Spring 014 S. Hoyos-ECEN-610 50

Averaging Spring 014 S. Hoyos-ECEN-610 51

Averaged Output Flash ADC Ref: A Technique For Reducing Differential Non-linearity Errors In Flash A/D Converters, Kattmann, K.; Barrow, J.; Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International 13-15 Feb. 1991 Page(s):170-171 Spring 014 S. Hoyos-ECEN-610 5

Improved Performance Spring 014 S. Hoyos-ECEN-610 53

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