CMSC 33 Lecture 6 nnouncement: no office hours today. Good-bye ssembly Language Programming Overview of second half on Digital Logic DigSim Demo UMC, CMSC33, Richard Chang <chang@umbc.edu>
Good-bye ssembly Language What a pain! Understand pointers better Execution environment of Unix processes the stack virtual memory Linking & loading UMC, CMSC33, Richard Chang <chang@umbc.edu>
-3 ppendix : Digital Logic Some Definitions Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs. e.g. an adder. Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs. e.g. a memory unit. Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state. e.g. a vending machine controller. Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-4 ppendix : Digital Logic The Combinational Logic Unit Translates a set of inputs into a set of outputs according to one or more mapping functions. Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, and, and, or 5 V and V for example. The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. set of inputs i i n are presented to the CLU, which produces a set of outputs according to mapping functions f f m. i i i n... Combinational logic unit... f (i, i ) f (i, i 3, i 4 ) f m (i 9, i n ) Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
3-6 Ripple Carry dder Chapter 3: rithmetic Two binary numbers and are added from right to left, creating a sum and a carry at the outputs of each full adder for each bit position. b 3 a 3 c 3 b 2 a 2 c 2 b a c b a c Full adder Full adder Full adder Full adder c 4 s 3 s 2 s s Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-45 ppendix : Digital Logic Classical Model of a Finite State n FSM is composed of a combinational logic unit and delay elements (called flip-flops) in a feedback path, which maintains state information. Inputs Machine i o i k...... Combinational logic unit Q D... Q n D n... s Synchronization n signal Delay elements (one per state bit) s... f o f m Outputs State bits Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-7 ppendix : Digital Logic Vending Machine State Transition Q/ dime is inserted Diagram / = Dispense/Do not dispense merchandise N/ D/ / = Return/Do not return a nickel in change / = Return/Do not return a dime in change N/ D Q/ D/ 5 5 Q/ Q/ D/ Principles of Computer rchitecture by M. Murdocca and V. Heuring D/ N/ C N/ N = Nickel D = Dime Q = Quarter 999 M. Murdocca and V. Heuring
CMSC 33, Computer Organization & ssembly Language Programming, Section Fall 24 Course Syllabus We will follow two textbooks: Principles of Computer rchitecture, by Murdocca and Heuring, and Linux ssembly Language Programming, by Neveln. The following schedule outlines the material to be covered during the semester and specifies the corresponding sections in each textbook. Date Topic M&H Neveln ssign Due Th 9/2 Introduction & Overview.-.8.-.6 Tu 9/7 Data Representation I 2.-2.2, 3.-3.3 2.4-2.7, 3.6-3.8 HW Th 9/9 Data Representation II Tu 9/4 i386 ssembly Language I 3.-3.3, 4.-4.8 HW2 HW Th 9/6 i386 ssembly Language II 6.-6.5 Proj Tu 9/2 i386 ssembly Language III HW2 Th 9/23 i386 ssembly Language IV Proj2 Proj Tu 9/28 Examples Th 9/3 Machine Language 5.-5.7 Proj3 Proj2 Tu /5 Compiling, ssembling & Linking 5.-5.3 Th /7 Subroutines 7.-7.4 Tu /2 The Stack & C Functions Th /4 Linux Memory Model 7.7 8.-8.8 Proj4 Proj3 Tu /9 Interrupts & System Calls 9.-9.8 Th /2 Cache Memory 7.6 Proj4 Tu /26 Midterm Exam Th /28 Introduction to Digital Logic.-.3 3.-3.3 DigSim Tu /2 Transistors & Logic Gates.4-.7 Th /4 Circuits for ddition 3.5 HW3 DigSim Tu /9 Combinational Logic Components. Th / Circuit Simplification I.-.2 HW4 HW3 Tu /6 Flip Flops I. Th /8 Flip Flops II DigSim2 HW4 Tu /23 Finite State Machines.2-.3 Th /25 Thanksgiving break Tu /3 Circuit Simplification II.3 HW5 DigSim2 Th 2/2 Finite State Machine Design Tu 2/7 Registers & Memory.4-5, 7.-7.5 DigSim3 HW5 Th 2/9 I/O 8.-8.3 Tu 2/4 T DigSim3 Tu 2/2 Final Exam :3am-2:3pm
-5 ppendix : Digital Logic Truth Table Developed in 854 by George oole. Further developed by Claude Shannon (ell Labs). Outputs are computed for all possible input combinations (how many input combinations are there?) Consider a room with two light switches. How must they work? GND Inputs Output Hot Light Z Z Switch Switch Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-6 ppendix : Digital Logic lternate ssignment of Outputs to Switch Settings We can make the assignment of output values to input combinations any way that we want to achieve the desired input-output behavior. Inputs Output Z Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-7 ppendix : Digital Logic Truth Tables Showing ll Possible Functions of Two inary Variables Inputs Outputs The more frequently used functions have names: ND, XOR, OR, NOR, XOR, and NND. (lways use upper case spelling.) False ND XOR OR Inputs Outputs NOR XNOR + + NND True Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-8 ppendix : Digital Logic Logic Gates and Their Symbols Logic symbols shown for ND, OR, buffer, and NOT oolean functions. F F Note the use of the inversion bubble. F = F = + (e careful about the nose of the gate when drawing ND vs. OR.) ND F OR F F = F = uffer NOT (Inverter) Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
ppendix : Digital Logic -9 Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring Logic Gates and their Symbols (cont ) F NND F NOR F = F = + F Exclusive-OR (XOR) F = F Exclusive-NOR (XNOR) F =.
- ppendix : Digital Logic Variations of Logic Gate Symbols C F = C F = + (a) (b) + + (c) (a) 3 inputs (b) Negated input (c) Complementary outputs Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-4 ppendix : Digital Logic Tri-State uffers Outputs can be,, or electrically disconnected. C F ø ø C F ø ø C F = C or F = ø C F = C or F = ø Tri-state buffer Tri-state buffer, inverted control Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-8 ppendix : Digital Logic Sum-of-Products Form: The Majority Function The SOP form for the 3-input majority function is: M = C + C + C + C = m3 + m5 + m6 + m7 = Σ (3, 5, 6, 7). Each of the 2 n terms are called minterms, ranging from to 2 n -. Note relationship between minterm number and boolean value. Minterm Index 2 3 4 5 6 7 C F -side -side balance tips to the left or right depending on whether there are more s or s. Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-9 ppendix : Digital Logic ND-OR Implementation of Majority C Gate count is 8, gate input count is 9. C C F C C Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-2 ppendix : Digital Logic Notation Used at Circuit Intersections Connection No connection Connection No connection Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
Sum of Products (a.k.a. disjunctive normal form) OR (i.e., sum) together rows with output ND (i.e., product) of variables represents each row e.g., in row 3 when x = ND x 2 = ND x 3 = or when x x 2 x 3 = MJ3(x, x 2, x 3 ) = x x 2 x 3 +x x 2 x 3 +x x 2 x 3 +x x 2 x 3 = m(3, 5, 6, 7) x x 2 x 3 MJ3 2 3 4 5 6 7
Product of Sums (a.k.a. conjunctive normal form) ND (i.e., product) of rows with output OR (i.e., sum) of variables represents negation of each row e.g., NOT in row 2 when x = OR x 2 = OR x 3 = or when x + x 2 + x 3 = MJ3(x, x 2, x 3 ) = (x +x 2 +x 3 )(x +x 2 +x 3 )(x +x 2 +x 3 )(x +x 2 +x 3 ) = M(,, 2, 4) x x 2 x 3 MJ3 2 3 4 5 6 7 2
-2 ppendix : Digital Logic OR-ND Implementation of Majority C + + C + + C F + + C + + C Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
Equivalences Every oolean function can be written as a truth table Every truth table can be written as a oolean formula (SOP or POS) Every oolean formula can be converted into a combinational circuit Every combinational circuit is a oolean function Later you might learn other equivalencies: finite automata regular expressions computable functions programs 3
Universality Every oolean function can be written as a oolean formula using ND, OR and NOT operators. Every oolean function can be implemented as a combinational circuit using ND, OR and NOT gates. Since ND, OR and NOT gates can be constructed from NND gates, NND gates are universal. 4
-7 ppendix : Digital Logic ll-nnd Implementation of OR NND alone implements all other oolean logic gates. + + Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
-6 ppendix : Digital Logic DeMorgan s Theorem = = + + DeMorgan s theorem: + = + = F = + F = Principles of Computer rchitecture by M. Murdocca and V. Heuring 999 M. Murdocca and V. Heuring
DigSim Java applet/application that simulates digital logic Not for industrial use, good enough for us dvantages: FREE, runs on most platforms Disadvantages: slow, timing issues, saving issues UMC, CMSC33, Richard Chang <chang@umbc.edu>
CMSC 33, Computer Organization & ssembly Language Programming Section Fall 24 DigSim ssignment : Getting Started Due: Thursday November 4, 24 Objective The objective of this assignment is to make sure that everyone has access to DigSim and, most importantly, can save DigSim circuits for submission. ssignment Using DigSim, wire up the following circuit diagram, play with the switches, create a text box with your name, and save the circuit diagram. Turning in your program The file which has your circuit diagram should be a plain text file that starts with something like: # Digsim file version describe component ThreeOrPort pos 3 5 Use a text editor to look at the file and make sure that the file is not empty and has some data similar to the above. Next, use DigSim to load the file and make sure that this still works. If all is well, submit the circuit file using the Unix submit command as in previous assignments. The submission name for this assignment is :digsim.the UNIX command to do this should look something like: submit cs33_ digsim majority3.sim
Transistors & Gates Next time UMC, CMSC33, Richard Chang <chang@umbc.edu>