K.T. Tim Cheng, 4_fault_sim, v. Outline Fault Simulation Applications of fault simulation Fault coverage vs product quality Fault simulation scenarios Fault simulation algorithms Fault sampling K.T. Tim Cheng, 4_fault_sim, v. 2
What is the Fault Simulation Problem? Given : A circuit A test (sequence of test vectors) A fault model Determine: Fault coverage (the fraction of modeled faults detected) Undetected faults K.T. Tim Cheng, 4_fault_sim, v. 3 Applications of Fault Simulation Determine fault coverage of a given test sequence Fault coverage = # of detected faults total # of faults Measure of test quality Approximate defect coverage Defect coverage: the probability that the test sequence detects any physical defect in the ckt. Determine undetected faults for test generation K.T. Tim Cheng, 4_fault_sim, v. 4 2
Use of Fault Simulation in Test Generation System Verified design netlist Verification input stimuli Fault simulator Test vectors Modeled fault list Remove tested faults Test compactor Delete vectors Fault Low coverage? Adequate Stop Test generator Add vectors Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2 K.T. Tim Cheng, 4_fault_sim, v. 5 Applications of Fault Simulation-Cont d Construct fault dictionary for diagnosis Use a fault simulator to compute & store the response for every fault If the output response of the circuit under test matches any of the response in the fault dictionary, the fault location is identified K.T. Tim Cheng, 4_fault_sim, v. 6 3
Yield & Defect Level Let: Y (yield) : probability that a manufactured circuit is defect-free DL (defect level) : probability of shipping a defective product d (defect coverage) : the defect coverage of the test used to check for manufacturing defects DL = - Y -d [ William & Brown, 98. Trans. on Computers] K.T. Tim Cheng, 4_fault_sim, v. 7 High Fault Coverage: Why? Y = manufacturing yield DL = defect level d = defect coverage DL = - Y -d Defect level.8.6.4 Y =. Y =. Y =.25 Y =.5.2 - - Y =.75 Y =.9 2 4 6 8 Defect coverage (%) K.T. Tim Cheng, 4_fault_sim, v. 8 4
High Fault Coverage: Why? 25 2 Y =.3 Defect level (DPM) 5 Y =.5 Y =.8-98 98.5 99 99.5 Defect coverage (%) Y =.5 Coverage Defect Level 99 698 99.5 99.6 346 2769 Too pessimistic!! 99.7 277 99.8 385 99.9 693 K.T. Tim Cheng, 4_fault_sim, v. 9 Fault Coverage vs. Defect Coverage High fault coverage (measured for single stuck-at faults) is : necessary but not sufficient for high defect coverage. Also need: Parametric testing Delay-fault testing Bridging-fault testing Technology-specific-fault testing (e.g., CMOS stuck-open/-short faults) K.T. Tim Cheng, 4_fault_sim, v. 5
Fault Simulation Scenario Circuit model: mixed-level Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults Signal states: logic Two (, ) or three (,, X) states for purely Boolean logic circuits Four states (,, X, Z) for sequential MOS circuits Timing: Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback K.T. Tim Cheng, 4_fault_sim, v. Fault Simulation Scenario cont d Faults models: typically single-sa & transition faults Transistor (stuck-open/-short) fault and path-delay fault simulators are not in common use Equivalence fault collapsing of single SA faults is in common use (no dominance collapsing why?) CPU runtime and memory usage are major limitations for large ckts Fault-dropping - a fault once detected is dropped from consideration as more vectors are simulated; faultdropping may be suppressed for diagnosis Fault sampling - a random sample of faults is simulated when the circuit is large K.T. Tim Cheng, 4_fault_sim, v. 2 6
Fault Simulation Algorithms Serial Parallel Deductive Concurrent Parallel-pattern single-fault propagation Differential K.T. Tim Cheng, 4_fault_sim, v. 3 Serial Fault Simulation For every fault Modify the fault-free circuit to inject the fault Rerun logic simulation Compare the output response to a stored output for detection Easy to implement CPU time is large for big circuits But, to simulate N faults, the total fault simulation time is not N T T is logic (fault-free) simulation time of same test Why? K.T. Tim Cheng, 4_fault_sim, v. 4 7
Parallel Fault Simulation Compiled code simulation Exploits inherent parallelism of logic instructions Storage: one word per signal for binary simulation Multi-pass simulation Each pass simulates (w-) new faults w: the machine word length K.T. Tim Cheng, 4_fault_sim, v. 5 Parallel Fault Simulation - An Example Fault - free circuit Circuit with c stuck at Circuit with f stuck at Bit : 2 a b x c sa - e g d x f sa - K.T. Tim Cheng, 4_fault_sim, v. 6 8
Parallel Fault Simulation - Multiple Values Three signal values : {,, u } Two bits per signal encoding A A A u K.T. Tim Cheng, 4_fault_sim, v. 7 Word Operations for Basic Functions Two words per signal AND OR NOT x y z x y z X Z Z = X * Y Z = X * Y * bit-wise AND Z = X + Y Z = X + Y + bit-wise OR Z = X Z = X - bit-wise NOT K.T. Tim Cheng, 4_fault_sim, v. 8 9
Parallel Fault Simulation CPU increases with the number of faults Fixed low memory requirement Simulate many faulty circuits at once Easy to implement fixed-delay timing model Elements must have logical operation K.T. Tim Cheng, 4_fault_sim, v. 9 Deductive Fault Simulation One-pass simulation for all faults A list of faults attached to each signal by simulation Fault F in list L k F causes signal k be sensitized Derive rules to compute output fault list from input fault lists of a gate; rules depend on both gate type and input values K.T. Tim Cheng, 4_fault_sim, v. 2
Deductive Simulation - Examples A B Z Any fault causes an error at A or B (change A or B from to ) will cause Z to be erroneously. L Z = L A L B { Z s-a-} A B Z Any fault that causes A to be without changing B, will cause Z to be in error ; i.e Z = L Z = (L A L B ) { Z s-a-} = (L A -L B ) { Z s-a-} K.T. Tim Cheng, 4_fault_sim, v. 2 Deductive Fault Simulation - Rules Gate Z I: set of inputs c: controlling value i : inversion S: set of inputs with value c The fault list of Z: if S = φ then L Z = { L j } { Z s-a- (c i)} ---- () j I else L Z = { L j } - { L j } { Z s-a-(c i)} ---------- (2) j S j I-S () If no input has value c, any fault effect on any input propagates to the output. (2) If some inputs have value c, only a fault effect that affects all the inputs at c without affecting any of the inputs at c propagates to the output. K.T. Tim Cheng, 4_fault_sim, v. 22
Deductive Fault Simulation - An Example {a} a {b} b {b, c} c d L e = L a L c { e } = { a, b, c, e } e {b, d, f} {b, d} f L g = L e L f { g } = { a, c, e, g } g K.T. Tim Cheng, 4_fault_sim, v. 23 Deductive Fault Simulation - Algorithm Pre-processing: Levelize ckt from inputs to outputs Step : Read in a test vector Step 2: Perform logic simulation Step 3: Perform list intersection, inversion, union level by level from inputs towards outputs; Step 4: determine and drop detected faults Go to step K.T. Tim Cheng, 4_fault_sim, v. 24 2
Concurrent Fault Simulation (Ref: Ulrich & Baker, Computer 975) Requires good circuit simulation plus only those parts of a faulty circuit which differ from the good circuit Fault-free and all faulty circuits are simulated in one pass Record differences between a faulty circuit and the faultfree circuit Store the differences in lists (one list per gate) An element in the list of a gate iff the input/output values of the faulty circuit are different from the the fault-free values K.T. Tim Cheng, 4_fault_sim, v. 25 Concurrent Simulation - An Example a bo c e a b c d e f a g b c e d f g b d f K.T. Tim Cheng, 4_fault_sim, v. 26 3
Concurrent Fault Simulation - Cont d An element contains: Fault index Fault state Input values Output values Event-driven: events include value changes in both fault-free and faulty circuits. K.T. Tim Cheng, 4_fault_sim, v. 27 Concurrent Simulation - Convergence a => b => c => e => a b c d => => => e f => a => g b c e => d => f => g b d f K.T. Tim Cheng, 4_fault_sim, v. 28 4
Concurrent Simulation - Divergence b c a e a b c e g d f b d f a e g b d f K.T. Tim Cheng, 4_fault_sim, v. 29 Advantages and Disadvantages of Deductive & Concurrent Algorithms Advantage: Single-pass simulation for all faults Disadvantage: Large memory to record the status of all machines Dynamic memory, (linked lists) Evaluation overhead on the linked lists Performance overhead in memory management K.T. Tim Cheng, 4_fault_sim, v. 3 5
Parallel-Pattern Single-Fault Propagation (Waicukauski et al, ITC, 985) For combinational circuits only Single-fault propagation (serial fault simulation) Parallel-pattern evaluation (). Parallel fault-free simulation of a group of W vectors (2). Undetected faults are serially injected and the faulty values are computed in parallel for the same set of vectors (3). Propagation of the fault effects continues as long as faulty values different from the good values in at least vector K.T. Tim Cheng, 4_fault_sim, v. 3 Random Fault Sampling The computational requirements ( CPU & memory) of fault simulation increase with the number of simulated faults. Fault sampling: a technique that reduces the cost of fault simulation by simulating only a random sample of total faults Problem statement: to determine a sample size m<<m s.t. we can be confident (with a specified confidence level c) that the error in the estimated fault coverage is bounded by a given e max K.T. Tim Cheng, 4_fault_sim, v. 32 6
Fault Sampling Problem Formulation M: total number of collapsed faults M K: number of faults detected by the K evaluated test sequence T k m: number of faults randomly selected k: number of detected faults in m m Actual fault coverage : F = K/M Regard k as a random variable P k (m, M, K): the probability that T will detect k faults from a random sample of size m, given that it detects K faults from the entire set of M faults K.T. Tim Cheng, 4_fault_sim, v. 33 Fault Sampling Deriving the Formula P k (m, M, K) = It s hypergeometric distribution: K mean: μ k = m = mf M variance: σ k 2 = K M K k m k M m K K M m m M M M m mf M ( F ) K M k m K.T. Tim Cheng, 4_fault_sim, v. 34 7
Deriving the Formula Cont d For large M, it can be approximated by a normal distribution with mean μ k and standard deviation σ k The estimated fault coverage f: a random variable with normal distribution μ f = μ k /m = F σ 2 f = σ k2 /m 2 = (/m) F(-F) (-m/m) With a confidence level of 99.7%, the estimated fault coverage f [F-3σ f, F+3σ f ] e max =3σ f = m 3 F( F ) M m If m<<m, e max 3 F ( F ) m - independent of M!! K.T. Tim Cheng, 4_fault_sim, v. 35 Prediction Error As a Function of Fault Coverage and Sample Size Maximum error emax.7 m=5.6.5.4 m=.3 m=2.2..2.4.6.8 Fault coverage F K.T. Tim Cheng, 4_fault_sim, v. 36 8
Summary Fault Simulation Fault simulator is an essential for test development Fault simulation is a memory- and computationexpensive process Several efficient algorithms Parallel Deductive Concurrent Parallel-pattern single-fault propagation For large ckts, accuracy of random fault sampling only depends on sample size, and not on circuit size. The method could save substantial amount of CPU runtime and memory usage K.T. Tim Cheng, 4_fault_sim, v. 37 9