Mitigating Semiconductor Hotspots The Heat is On: Thermal Management in Microelectronics February 15, 2007 Seri Lee, Ph.D. (919) 485-5509 slee@nextremethermal.com www.nextremethermal.com 1
Agenda Motivation Embedded ThermoElectric Cooler (etec) Applications Summary 2
Localized High Heat Flux Areas Create Hot Spots Hot spots adversely impact Reliability Performance Leakage power Yield Hot spots get worse as CMOS scales sensitive to small changes in temperature Source: Debendra Mallik, Intel, MEPTEC (2/06) 3
CMOS Scaling Increases Total and Nonuniform Power Dissipation Total power dissipation increases Higher dynamic power More transistors and interconnects Faster clock frequencies Higher leakage power Nonuniform power dissipation becomes more pronounced 4
Thermal Stack-Up (Typical Case Example) Air Thermal Resistance ( o C/W) Heat Sink TIM Package Θ JA = T J T A TDP Al Fins Cu Base Thermal Grease IHS TIM Nonuniform power Hot spots significantly reduce the total cooling capability Source: Intel (MEPTEC 2/06) Die 5
Uniform vs. Non-Uniform Hot-Spot Cooling Uniform Cooling Conventional components (TIMs, spreaders, heat sinks ) - Available improvements already made - Further improvements are quite costly Reduces temp everywhere across chip Shifts all temperatures down Inefficient for just hot-spot cooling (overcools rest of chip) Hot-Spot Cooling Nextreme's etec Lops-off top of hot spot #1 Provides "new knob" for improving TDP in increments T hot spot #1 T hot spot #2 T junction limit T hot spot X T hot spot #1 T hot spot #2 Temperature (ºC) T average T hot spot #2 T average T average 6
Hot-Spot Cooling (Example with 60W TDP) Reduces Overall Power Consumption By Not Cooling Background Heat Profile Cooling + = Profile Resulting Thermal Profile Thermal = Load at Heat-sink 58W (COP = 1) + 60W = = 120W 2W Uniform Cooling Entire Chip Hot-Spot Cooling (COP = 1) 58W 2W + = 2W Hot spot only = 62W Hot-spot cooling requires a fraction of power 7
Cool Hot Spots To Increase Chip Performance 1) Increase chip performance within existing TDP (Thermal Design Power is cooling capacity / thermal envelop) Support Windows Vista and mobile / compact systems Handle new ICs with more pronounced hot spots Extend use of current thermal components (sinks, TIM, spreader ) 2) Increase chip performance by allowing significantly increased TDP In conjunction with new thermal components Performance-intensive apps are thermally clock gated (CPU runs at less than rated frequency) New High- Performance Bin Core Cooling Unit Price Sustained Frequency Rated Frequency Speed (GHz) 8
Nextreme s Embedded Thermoelectric Cooler (etec) Miniature Heat Pump Positioned Close To Heat Source Thermoelectrics Technology Applications Thermoelectrics Solid-state heat pump Heat or Cool Power Generation Converts heat into electricity Nextreme s unique etec Nano-engineered thin-films (vs. conventional bulk TEC) Very thin Very thin High heat flux High heat flux Very fast Efficient Solid-state Microfabrication scalability 9
Product: Micro Thermoelectric Module Solid State Heat Pump Size: 2.5mm x 2.5mm x 100 μm Embedded semiconductor cooling High performance & efficiency Cooling PN couple (0.32 mm sq.) Heat Spreader Ground Maximum cooling: 40 C Maximum Pumping: 175 W/cm 2 Demonstrated in-package hot spot cooling: 7 C, up to 14 C Power etec (7x7) 2.5 mm sq. Tiny, Thin and Flexible Form-Factor Factor 10
etec Performance Advantage Enables Hot Spot Cooling Conventional discrete TEC (Bulk) etec (4x4) 65 55 40 ΔT (ºC) etec (Next Generation) etec Load Line (as measured) Process Improvements - Reduce contact resistance - Improve PN materials - Reduce parasitics Bulk Performance Thin Film Chip Cooling Performance Space Advantage Heat Flux (W/cm 2 ) 10 175 300+ 11
IC Package Applications For Hot Spot Cooling Processors, Graphics, ASICs, DSPs Lidded Servers Lidded and Lidless Game Boxes Desktop PCs Lidless Cell Phones Add-in Cards Mobile PCs 12
In-Package Hot Spot Cooling Embedded Thermoelectric Cooler (etec) Heat Sink TIM2 Substrate IHS TIM1 Die etec Demonstrated: up to 14 o C etec Cools Hot Spot Only Demonstrated Increased yield, reliability & performance Complementary to traditional, uniform cooling solutions 13
Applications: CMOS ICs in Lidless Packages ICs GPUs GPUs CPUs, GPUs, ASICs Implementation Add-in cards Add-in cards Motherboards System Desktop PCs Notebook PCs MoDT* & Notebook PCs System cooling Heat sink & fan Heat sink & fan Heat pipe, heat sink and fan Heat Sink/Cold Plate TIM Die Substrate etec *MoDT = Mobile on Desktop 14
etec Fits Between Die and Cold Plate For Lidless Chip Applications Cold plate or heat-sink base Direct bond etec TIM IC die Substrate etec's Power Connector Flip Chip BGA PCB 15
Cool Hot Spots on Backside of Die by ~5 º C Die back side Core 2 Die front side Core 1 Cache Die back side Cool hot spots by ~5 º C Die front side 16
etec Hot-Spot Cooling (Simulation) 180 160 100 Power Density (cm2) 140 120 100 80 60 40 20 0 0.3 2.8 5.4 x (mm) Power Map 8.0 10.6 8.2 6.2 4.2 2.2 y (mm) 0.2 Temperature ('C) 96 92 88 84 80 76 72 68 64 60 0.3 2.8 5.4 x (mm) 8.0 10.6 4.2 6.2 2.2 y (mm) 0.2 8.2 Temperatures without etec 100 96 Temperature ('C) 92 88 84 80 76 72 68 64 60 0.3 2.8 5.4 x (mm) 8.0 10.6 8.2 6.2 4.2 2.2 y (mm) 0.2 Temperatures with etec 17
etec Heat Pumping Performance (25 PN Couples at 85 º C) Qc (W) 16 14 12 10 8 6 4 2 DT = 0 ºC DT = 10 ºC DT = 19 ºC DT = 29 ºC DT = 38 ºC 0 0 2 4 6 8 10 I (A) Q c = N(IST c KΔT - ½ I 2 R) I max = S T c / R Conduction Q max = ½ S 2 T c 2 / R Joule heating N = number of PN couples S = S p S n (Seebeck coef) ΔT = T h T c A = area of thermoelectric l = thickness of thermoelectric K = k A / l R = ρ l / A 18
etec ΔT Performance (25 PN Couples at 85 º C) Delta T (ºC) 50 40 30 20 10 Qc = 0 W Qc = 3 W Qc = 6 W Qc = 9 W Qc = 12 W 0 0 2 4 6 8 10 I (A) (I S T c ½I 2 R - Q c ) ΔT = K ΔT max = ½ S 2 T 2 c / K R S = S p S n (Seebeck coef) ΔT = T h T c A = area of thermoelectric l = thickness of thermoelectric K = k A / l R = ρ l / A 19
etec Loadlines (i.e. 25 PN Couples at 85 º C) 30 25 COP=0.3 I = 0.9 A I = 1.7 A Delta T (ºC) 20 15 10 0.6 0.8 2.3 1.3 1.9 I = 2.6 A 5 3.7 2.5 0 0 1 2 3 4 5 6 7 50 100 Q (W) Q (W/cm 2 ) etec cools ~75 W/cm 2 by ~5 º C with High COP 20
etec COP Performance (25 PN Couples at 85 º C) COP 5 4 3 2 DT = 5 ºC DT = 10 ºC DT = 19 ºC DT = 29 ºC DT = 38 ºC 1 0 0 2 4 6 8 10 I (A) Coefficient of Performance Heat pumped COP = Power input I S T = c K ΔT - ½ I 2 R I S ΔT + I 2 R S = S p S n (Seebeck coef) ΔT = T h T c A = area of thermoelectric l = thickness of thermoelectric K = k A / l R = ρ l / A 21
etec Performance (T H = 85 º C) 5 ΔT = 5 º C 5 ΔT = 10 º C 4 Next Gen 4 COP 3 2 Current 3 2 Next Gen 1 1 Current 0 0 50 100 150 200 250 300 Q' (W/cm 2 ) 0 0 50 100 150 200 250 300 Q' (W/cm 2 ) 22
Summary New embedded thermoelectric cooler (etec) provides localized, hotspot cooling in close proximity to the die etec complements uniform platform-level chip cooling approaches Advantages include high heat-flux, fast response time and small & thin size etecs are optimized for small area, high heat-flux with modest ΔT Applications are high-performance CMOS ICs, Photonics, Edge- Emitting Lasers, etc. Benefits are enhancing chip performance, reliability and yield 23