Roger L. Tokheim. Chapter 8 Counters Glencoe/McGraw-Hill

Similar documents
CHW 261: Logic Design

Digital Circuits ECS 371

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

Digital Fundamentals

DE58/DC58 LOGIC DESIGN DEC 2014

Digital Electronics Final Examination. Part A

LOGIC CIRCUITS. Basic Experiment and Design of Electronics

LOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.

Counters. We ll look at different kinds of counters and discuss how to build them

ELCT201: DIGITAL LOGIC DESIGN

Digital Fundamentals

Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution

EET 310 Flip-Flops 11/17/2011 1

Chapter 14 Sequential logic, Latches and Flip-Flops

Gates and Flip-Flops

Chapter 5 Synchronous Sequential Logic

ELCT201: DIGITAL LOGIC DESIGN

6 Synchronous State Machine Design

ECE 341. Lecture # 3

SIR C.R.REDDY COLLEGE OF ENGINEERING ELURU DIGITAL INTEGRATED CIRCUITS (DIC) LABORATORY MANUAL III / IV B.E. (ECE) : I - SEMESTER

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

Lab 3 Revisited. Zener diodes IAP 2008 Lecture 4 1

Synchronous Sequential Logic

PGT104 Digital Electronics. PGT104 Digital Electronics

Digital Logic Design - Chapter 4

ECE/Comp Sci 352 Digital Systems Fundamentals. Charles R. Kime Section 2 Fall Logic and Computer Design Fundamentals

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) State any two Boolean laws. (Any 2 laws 1 mark each)

Sequential Circuits Sequential circuits combinational circuits state gate delay

Experiment 9 Sequential Circuits

I. Motivation & Examples

S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques

Vidyalankar S.E. Sem. III [EXTC] Digital Electronics Prelim Question Paper Solution ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD = B

Sequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science

S.Y. Diploma : Sem. III [CO/CM/IF/CD/CW] Digital Techniques

EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters)

10/12/2016. An FSM with No Inputs Moves from State to State. ECE 120: Introduction to Computing. Eventually, the States Form a Loop

Sample Test Paper - I

EECS150 - Digital Design Lecture 18 - Counters

EECS150 - Digital Design Lecture 18 - Counters

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

EE 209 Logic Cumulative Exam Name:

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Q: Examine the relationship between X and the Next state. How would you describe this circuit? A: An inverter which is synched with a clock signal.

Digital Electronic Meters

Digital Circuits and Systems

COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University

Layout of 7400-series Chips Commonly Used in. CDA 3101: Introduction to Computer Hardware and Organization

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

Chapter 7 Sequential Logic

Introduction EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN. Lecture 6: Sequential Logic 3 Registers & Counters 5/9/2010

Written reexam with solutions for IE1204/5 Digital Design Monday 14/

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

Synchronous 4 Bit Counters; Binary, Direct Reset

Synchronous Sequential Logic Part I. BME208 Logic Circuits Yalçın İŞLER

CS221: Digital Design. Dr. A. Sahu. Indian Institute of Technology Guwahati

Menu. Part 2 of 3701: Sequential Digital Machines Latches and Flip-Flops: >S-R latches >D latches >T latches. Comb. n. Logic. m Q.

Sequential vs. Combinational

MOSIS REPORT. Spring MOSIS Report 1. MOSIS Report 2. MOSIS Report 3

EECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary

Philadelphia University Student Name: Student Number:

Exam for Physics 4051, October 31, 2008

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering

Fundamentals of Boolean Algebra

Digital Electronics Circuits 2017

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

COE 202: Digital Logic Design Sequential Circuits Part 4. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

Shift Register Counters

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Lecture 17: Designing Sequential Systems Using Flip Flops

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

Unit II Chapter 4:- Digital Logic Contents 4.1 Introduction... 4

Synchronous Sequential Logic Part I

Digital Logic Design - Chapter 5

Lecture 9: Digital Electronics

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. *MR for LS160A and LS161A *SR for LS162A and LS163A

Design at the Register Transfer Level

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs

Sequential Logic Worksheet


MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)

on candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.

Digital Electronics. Part A

Lecture 14: State Tables, Diagrams, Latches, and Flip Flop

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

Fundamentals of Digital Design

Different encodings generate different circuits

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

Lecture 7: Logic design. Combinational logic circuits

EECS150 - Digital Design Lecture 23 - FSMs & Counters

Stop Watch (System Controller Approach)

EECS150 - Digital Design Lecture 16 Counters. Announcements

DIGITAL LOGIC CIRCUITS

Topics for Lecture #9. Button input processor

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec 09 Counters Outline.

Schedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date.

EE 209 Spiral 1 Exam Solutions Name:

Digital Electronics II Mike Brookes Please pick up: Notes from the front desk

Transcription:

Digital Electronics Principles & Applications Sixth Edition Roger L. Tokheim Chapter 8 Counters 2003 Glencoe/McGraw-Hill

INTRODUCTION Overview of Counters Characteristics of Counters Ripple Up Counter Ripple Counter with Waveforms Ripple Down Counter Self-stopping Counter Frequency Division using Counters Using Counter ICs Magnitude Comparators Troubleshooting Hints

Overview of Counters Counter-by definition One input (clock) Outputs follow defined sequence Common tasks of counter Count up or down Increment or decrement count Sequence events Divide frequency Address memory As memory

QUIZ 1. A digital counter has a single clock input with many outputs and the counter follows defined sequence such as 000, 001, 010, 011, 100, 101, 110, 111, 000, etc. (True or False) 2. Several common tasks of a counter are to count up or down, divide frequency, or as memory. (True or False) True True

Characteristics of Counters Number of bits (4-bit, 8-bit, etc.) Maximum count 4 bit = 2 4 = 0000 to 1111 in binary 8 bit = 2 8 = 0000 0000 to 1111 1111 in binary Modulus of counter-number of states Decade counter 4-bit 8-bit Up or down counter Asynchronous or synchronous counter Presettable counter Self-stopping counter

QUIZ 1. A4 4-bit counter will count from binary 0000 to. 1111 2. The modulus of a counter is the number of state it will cycle through such as a decade counter has a modulus of. 3. Counters can be designed to count up or downward or devised to be self-stopping. (True or False) 10 True 4. A 4-bit counter would have modulus of 4 (mod-4 counter) because it is constructed using four flip-flops. (True or False) False

Ripple Counter Clock Input Binary Output 01 10 10 10 Pulse 12 34 56 78 This PS On and the 4-bit CLR next counter input clock has pulse All 16 J-K (8) states flip-flops all FFs and will will count toggle are from because binary each 0000 will through in the receive 1111 a H-to-L and INACTIVE then pulse- reset one back TOGGLE after to another. 0000. MODE Watch The the counter has ripple a modulus thru the of counter. 16.

Ripple Counter With Waveforms Clock Input Binary Output 0 0 1 1 0 0 1 Pulse 12 34 5 Clock input FFs triggered on 1s output H-to-L pulse. CLK toggles 1s FF. 1s FF toggles 2s FF. 2s output 2s FF toggles 4s FF. 4s output

QUIZ Q#1- Q#2-1 the of the Q#3-2 the of the Q#4- After will will be pulse 8 the output of the mod-16 be 15. the output of the mod-16 will be. counter will be binary.. 1 01 10 1 01 0 0 0 01 Input Pulse Pulses 15 12 8

Decade Counter Clock Input Binary Output 0111 1000 1001 0000 0001 0010 0011 0100 0101 0 0 Pulse 12 34 56 78 Short negative pulse To clear input of each FF All J & K inputs = 1 All PR inputs = 1 To change mod-16 counter to decade counter: Count is at 1001. Reset count to 0000 after 1001 (9) count. Next clock pulse will increment counter for a When count hits 1010 reset to 0000. short time to 1010 which will activate the NAND gate See added 2-input NAND gate that clears all and reset the counter to 0000. JK FFs to 0 when count hits 1010.

QUIZ Q#1- Q#2- Q#3- This This The is circuit a gate can (mod-10, generates be described mod-16) a very as up short a counter. LOW (decade, pulse 4-bit) Q#4- After 0110, the counting sequence would be 0111, when 1000, the up count counter. 1001, reaches 1010, 1011, 10101100, and 1101, resets 1110, to counter 1111, 0000, to 0000. etc. (T or F) ANS: mod-10 decade ANS: ANS: NAND False 0110 1 0 Input pulses To clear input of each FF

Down Counter 1 0 0 1 10 Pulse 12 34 5 Changes from Ripple Up Counter are wiring from Q outputs (instead of Q outputs) to the CLK input of the next FF.

QUIZ Q#1- This i can be described as a 3-bit ripple (down-counter, Q#2- Q#3- This The circuit counting up-counter). is a sequence self-stopping of this 3-bit circuit ripple is 111, down 110, counter. 101, (T 100, or 011, F) 010, 001, 000, 111, 110, 101, 100, etc. (T or F) ANS: down-counter ANS: False ANS: True 111 1 1 Input pulses

Self-Stopping Down Counter 1 0 1 0 10 The count remained at binary 000. Pulse 12 34 56 78 This is a 3-bit down counter. The 1s FF is in TOGGLE mode when counting (J & K = 1). The 1s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate when the count decrements to 000. The count stops at 000.

QUIZ Q#1- This circuit could be described as a 3-bit (decade, Q#2- Q#3-With The self-stopping) 3-input the count OR gate 111, ripple generates the OR gate counter. a outputs (HIGH, a LOW) HIGH when which the places count the decreases left FF in to the 000 toggle which mode. stops the (T or count F) at 000. ANS: self-stopping ANS: LOW ANS: True 1 1 1 Input tpulses

Counter Used for Frequency Division 8 200 Hz 4 100 Hz 400 Hz 50 Hz 2 16 Clock Input 800 Hz

QUIZ Q#1- Q#2- is the Q#3- is is the the from from the 1s J-K with an from Q#4- Q#5- the the What The 2s J-K 8s 4s J-K is output the output from with with frequency the an 4-bit an from the 8s J-K of flip-flop 3200 Hz? p with an input counter frequency is referred of of of 3200 3200 3200 to as Hz? Hz? Hz? the ANS: 1600 ANS: 800 (divide-by-4, divide-by-16) output. 400 ANS: divide-by-16 200 Clock Input Frequency? 3200 Hz

Using the 7493 Counter IC Counters are available in IC form. Either ripple (7493 IC) or synchronous (74192 IC) counters are available. 100? Hz Hz 400? Hz Hz 800? Hz Hz 1600 Hz 7493 Counter IC wired as a 4-bit binary counter

Magnitude Comparator A magnitude comparator is a combinational logic device that compares the value of two binary numbers and responds with one of three outputs (A=B or A>B or A<B). A(0) Input binary 0111 1111 0001 Input binary 0110 0111 1100 A(1) A(2) A(3) B(0) B(1) B(2) 74HC85 Magnitude Comparator A > B A = B A < B HIGH HIGH HIGH B(3)

QUIZ Q#1- The 74HC85 Comparator IC compares two 4-bit (binary, Q#2- Q#3- decimal) numbers of the (A and B) and IC generates will be one Q#4- Which output of of the the comparator IC IC will will be be activated of three outputs with with including two two 4-bit 4-bit (1) A = B, (2) A > B, or as as with these two 4-bit binary numbers as (3) inputs? A < B. 0101 1101 A(0) A(1) A(2) A(3) B(0) B(1) 1010 B(2) B(3) 0101 1011 74HC85 Magnitude Comparator A>B A = B A < B??? ANS: binary = < ANS: A > B

Simple Troubleshooting Hints Feel topofictodetermineifitishot of if it is Look for broken connections, signs of excessive heat Smell for overheating Check power source Trace path of logic through circuit Know the normal operation of the circuit

QUIZ 1. The first three steps in troubleshooting are the use of your senses to (1) feel the top of the ICs for overheating, (2) to for broken connections, and (3) to smell for signs of overheating. 2. The forth step in troubleshooting is to use a simple handheld instrument called a to check the power sources at each IC. 3. Your knowledge of the normal operation of the circuit and equipment is very important in troubleshooting. (True or False) look logic probe True

REVIEW Overview of Counters Characteristics of Counters Ripple Up Counter Ripple Counter with Waveforms Ripple Down Counter Self-stopping Counter Frequency Division using Counters Using Counter ICs Magnitude Comparators Troubleshooting Hints