Hardware Design I Chap. 4 Representative combinational logic

Hardware Design I Chap. 4 Representative combinational logic E-mail: shimada@is.naist.jp Already optimized circuits There are many optimized circuits which are well used You can reduce your design workload You can use faster one than your design :-P Some of them has different optimization level Optimized for logic gates reduction Optimized for operating speed Hardware Design I (Chap. 4) 2

Outline Data path controlling circuits Multiplexer/demultiplexer Buffer/Three state buffer/bi-directional buffer Encoder/decoder Arithmetic circuits Adder Comparator/Majority vote Shifter Multiplier Divider Hardware Design I (Chap. 4) 3 Multiplexer (/2) A circuit which outputs one of the inputs Also called Selector e.g. 2- MUX (2-input -output multiplexer) Output the value of in0 if the input of sel =0 Output the value of in if the input of sel = x y x y in0 in sel out x 0 in0 in sel out y Relationship between inputs and output sel out 0 in0 in Hardware Design I (Chap. 4) 4 2

Multiplexer (2/2) Logical expression of 2- MUX: out = (sel)'(in0) + (sel)(in) Assume that sel signal controls open/close of AND gate You can easily to extend logical expression to much more inputs with above design sel in0 in out Truth table of 2- MUX sel in0 in out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Hardware Design I (Chap. 4) 5 4- MUX (/2) The input of sel becomes 2-bit width I denote each bit of them as sel and sel 0 The truth table becomes 6-value x y in0 in in2 in3 sel out x z w 00 x y in0 in in2 in3 sel out w z w sel sel 0 out 0 0 i0 0 i 0 i2 i3 Hardware Design I (Chap. 4) 6 3

4- MUX (2/2) Assume that sel signal controls open/close of AND gate sel = (0,0) opens in0 gate sel = (0,) opens in gate sel = (,0) opens in2 gate sel = (,) opens in3 gate sel 0 sel in0 in in2 in3 Hardware Design I (Chap. 4) 7 Multiplexer with transmission gate (/2) Transmission gate The circuit which can control conductivity Input and output is conducted if sel = Warning: There s no current drive ability High impedance status (noted as Z) The node is not connected either Vdd or Gnd sel sel 0 0 No conduct Conduct in out in out 0 Operation sel out 0 Z in Truth table sel in out 0 0 Z 0 Z 0 0 Hardware Design I (Chap. 4) 8 4

Multiplexer with transmission gate (2/2) Much simpler than MUX with logic gates Warning: There s no current drive ability (= output drive ability) Current drive ability is depends on the logic gate before transmission gate You have to increase drive ability of prior gate depending on outputs of transmission gate in0 sel in sel out 0 in0 in out Hardware Design I (Chap. 4) 9 Three state buffer (tri-state buffer) in A buffer which can output disconnected status Buffer: a circuit which amplifies signal strength Assuming two not gates which drives output current before transmission gate Strictly speaking, the buffer and transmission gate is unified Also called tri-state buffer Circuit symbol sel out Truth table sel in out 0 0 Z 0 Z 0 0 Amplifies signal (source of current) Hardware Design I (Chap. 4) 0 5

Buffer A circuit which amplifies signal strength The current of amplified signal is comes from internal of the buffer Usually, we utilize larger (wide gate width) FET to drive much current Usage Emphasize signal to drive much gates in output side Emphasize signal to drive long signal line Variations Implement NOT gates separately Utilize negated output Larger Larger Current Hardware Design I (Chap. 4) Bi-directional buffer A buffer which can control signal flow The signal flows port 2 to port if sel=0 The signal flows port to port 2 if sel= Note that the port and port 2 is separated in electrical viewpoint Compare to transmission gate sel port sel port 2 Compare! port port 2 sel Hardware Design I (Chap. 4) 2 6

Demultiplexer The opposite operation to multiplexer The output which has not elected becomes high impedance status Constructed with transmission gate x in sel out out2 0 sel out out2 0 in Z Z in in sel out out2 x Z Hardware Design I (Chap. 4) 3 Decoder The circuit which output signal to corresponding output from input value Assume that a multiplexer with logic gate which has no input The output is also called - hot code in 0 in out0 out out2 out3 Hardware Design I (Chap. 4) 4 7

Encoder A circuit which outputs the number with binary notation which is corresponding to inputs Opposite function to decoder The output value under multiple input is undefined in0 in in2 in3 out out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Hardware Design I (Chap. 4) 5 Priority encoder The encoder which gives priority to specified order It can tolerate multiple inputs e.g. The priority encoder which has priority to smaller inputs Priority encoder which has priority to smaller inputs in0 in in2 in3 out out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Hardware Design I (Chap. 4) 6 8

Reading table with decoder and multiplexer (/2) We can read data in table organization by utilizing decoder and multiplexer As shown in Chap. 5, we can minimize storage by utilizing table organization Reading data in 6th (00) entry 00 Decoder 3 2 0 7 6 5 4 0 9 8 5 4 3 2 4- MUX Hardware Design I (Chap. 4) 7 Reading table with decoder and multiplexer (2/2) Operation Select row by inputting higher side bits into decoder Select column by inputting lower side bits into 4- MUX Widely used in RAM, flash memory, and so on Reading data in 6th (00) entry 00 Decoder 3 2 0 7 6 5 4 0 9 8 5 4 3 2 4- MUX Hardware Design I (Chap. 4) 8 9

Outline Data path controlling circuits Multiplexer/demultiplexer Buffer/Three state buffer/bi-directional buffer Encoder/decoder Arithmetic circuits Adder Comparator/Majority vote Shifter Multiplier Divider Hardware Design I (Chap. 4) 9 How to design arithmetic circuits? From -bit arithmetic to multi bit arithmetic Design and optimize -bit module Under considering expansion to multi bit Create multi bit circuit by utilizing -bit module Similar to create program with function call Special technique for optimizing arithmetic circuits Utilize characteristic of binary integer Optimize under usual algebra Hardware Design I (Chap. 4) 20 0

The notation of integer in binary We can represent 0 to 2 n - integer with n-bit binary notation (if we consider positive value) 2 n- 2 n-2 2 3 2 2 2 2 0 Add weight to each 0 0 0 0 digit 4... We use twos complement to represent signed integer (detail: subtraction circuit) We can represent it -2 n- to +2 n- - e.g. 8-bit signed integer with twos complement can represent from -28 to +27 Hardware Design I (Chap. 4) 2 Addition of binary integer Addition of -bit 0+0 = 0, 0+ =, +0 =, + = 0 Carry By considering carry, an addition of one digit becomes addition of three -bit Addition of augend (a), addend (b), and carry (c) Carry +) 0 0 0 000 c_in c_out a sum b 0 c_in c_out a sum b 0 st bit 0 0th bit 0 Hardware Design I (Chap. 4) 22

Addition of binary integer Generalized notation of n-bit binary integer The result becomes (n+)-bit binary integer c 0 = 0 c n = s n +) c n c n- c n-2... c c 0 a n- a n-2... a a 0 b n- b n-2... b b 0 s n s n- s n-2... s s 0 Hardware Design I (Chap. 4) 23 -bit full adder Definition of the circuit Inputs: two -bit binary and -bit carry input from lower digit Operation: sum all of inputs Outputs: sum and carry output Half adder An adder which has no carry input a b c_in c_out sum 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a b c_out c_in sum Hardware Design I (Chap. 4) 24 2

Implementation of half adder Usually implemented with XOR gate Much smaller gate number than AND- OR organization a b c s 0 0 0 0 0 0 0 0 0 a s a s b c b c Hardware Design I (Chap. 4) 25 Implementation of full adder We can create full adder with half adder Usually, the path of carry generation becomes critical path Critical path: the path has longest route half adder a a c b b s c_in half adder a c b s c_out Path of carry generation sum Hardware Design I (Chap. 4) 26 3

n-bit ripple carry adder An adder which layouts n of -bit full adder Called ripple carry adder (RCA) The calculation time is in proportion to n a a 2 b 2 a b a 0 b 0 n- b 0 n- a b c_out c_in sum c n... c 3 a b c_out c_in sum c 2 a b c_out c_in sum c a b c_out c_in sum c 0 s n- s 2 s (a n- a n-2... a 0 ) + (b n- b n-2... b 0 ) s 0 Hardware Design I (Chap. 4) 27 The RCA is slow Why RCA is slow? c 5 will be defined after c 4 has defined c 4 will be defined after c 3 has defined... ->c 5 is defined under sequential definition n-bit addition requires O(n) time Definition of O(n): 0 0 +) 0 000 Assuming function f(n) and G(n) f(n) = O[g(n)] if constant c and n0 which satisfy f(n) c g(n), n n0 Note that f(n) > 0, g(n) > 0 Hardware Design I (Chap. 4) 28 4

Carry look-ahead adder The critical point is carry Are there any way to speeding up carry generation? Idea: separate carry to two category Generation of carry: g i = a i b i The carry must occur in this digit Propagation of carry: p i = a i + b i The carry will occur if carry from (i-) has arrived Note that the generation of g i and p i are easy Assuming (a n- a n-2... a 0 ) + (b n- b n-2... b 0 ) Hardware Design I (Chap. 4) 29 Extracting carry with g i, p i, and c 0 Cn becomes n+ sum of term of n+ literal c = g 0 +p 0 c 0 c 2 = g +p c -> c 2 = g +p g 0 +p p 0 c 0 Calculated without c c 3 = g 2 +p 2 c 2 -> c 3 = g 2 +p 2 g +p 2 p g 0 +p 2 p p 0 c 0... -> c 4 = g 3 +p 3 g 2 +p 3 p 2 g +p 3 p 2 p g 0 +p 3 p 2 p p 0 c 0 c n = g n- +p n- c n- -> c n = g n- +p n- g n-2 +p n- p n-2 g n-3 + +p n- p k g k- + + p n- p 0 c 0 Hardware Design I (Chap. 4) 30 5

The condition which C n becomes Sum of later itemize g n- = g n-2 was propagated after n- digit (=p n- ) g n-3 was propagated after n-2 digit (=p n- p n-2 ) g k- was propagated after k digit. c 0 was propagated through all digits c n = g n- +p n- g n-2 +p n- p n-2 g n-3 + +p n- p k g k- + + p n- p 0 c 0 Hardware Design I (Chap. 4) 3 4-bit CLA p 3 g 3 g 2 g p 2 p p 0 g 0 c 0 c 4 c 3 c c 2 Hardware Design I (Chap. 4) 32 6

The characteristic of CLA It can calculate c i in parallel Much complicated than RCA Calculation time becomes O(log n) c n becomes sum of n+ term Each term is consist of n+ literals -> If we implement it with balance tree, the height becomes log n Hardware Design I (Chap. 4) 33 Quiz How long does CLA requires to calculate 64-bit value with NAND2 gate delay?. Around 8 NAND2 gate delay 2. Around 2 NAND2 gate delay 3. Around 6 NAND2 gate delay 4. Around 20 NAND2 gate delay 64-bit RCA requires around 29 NAND2 gate delay Hardware Design I (Chap. 4) 34 7

Answer 2. Around 2 NAND2 gate delay NAND2 delay for prepare pi and gi About 8 NAND2 delay for prepare ci from pi and gi 3 NAND2 delay for calculate si Result of practical implementation Alpha 2264 processor utilizes 2 FO4 delay for each pipeline stage pipeline stage ->Chap. It execute 64-bit arithmetic in pipeline stage Hardware Design I (Chap. 4) 35 Explore of faster adder Adder is one of the important circuit so that there s many implementations Examples Carry select adder Conditional sum adder Carry skip adder Carry bypass adder Carry complete adder Domino logic adder for Pentium 4 Hardware Design I (Chap. 4) 36 8

Outline of domino logic Operate with precharge and evaluation (=discharge) If input satisfies condition, output is discharged e.g. Domino logic XOR gate (a,b) = (,0) (a,b) = (0,) Otherwise, the output is Precharge not discharged 0 0-> ->0 ->0 a b a b a 0 b a b a b a 0 b 0 0 Discharge Discharge Hardware Design I (Chap. 4) 37 Twos complement (/2) A method which gives negative weight for most significant bit -2 n- 2 n-2... 0 0 0 0 e.g. Twos complement with 8-bit width -2 7 2 6 2 5 2 4 2 3 2 2 2 2 0 0 0 0 0 0 0 0 = -2 7 = -28 2 3 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = -2 7 + 2 0 = -27 = 2 6 + 2 0 =65 = 2 6 + 2 5 +...+ 2 0 = 27 Hardware Design I (Chap. 4) 38 9

Twos complement (2/2) We can represent -2 n- to +2 n- - Example of 8-bit width e.g. Twos complement with 8-bit 0 +27 width Why we do not use independent 0000000 + 00000000 0 sign bit? - It creates positive 0 and negative 0 0000000-28 -> redundant!!! Independent sign bit 0 000000000000000 positive 0............ 000000000000000 negative 0 Hardware Design I (Chap. 4) 39 How to create twos complement? You can gain inverse sign of twos complement by negating all bits and add to it 0 = 27 Add 00 Negation Add Negation 0000000 000000 = -27 Why it becomes twos complement? A negation of m becomes -2 n- + (2 n- -) - m By adding to above one, we can gain -m Note that -m = -2 n- +(2 n- -m) = -2 n- +{(2 n- -)-m+} Hardware Design I (Chap. 4) 40 20

Subtraction with twos complement Create twos complement of subtrahend and add it with adder Organization of the circuit Negate all bits before adder + is done by adding carry to c 0 a a 2 b 2 a b a 0 b 0 n- b n- a b c_out c_in sum c n... c 3 a b c_out c_in sum c 2 a b c_out c_in sum c a b c_out c_in sum c 0 s n- s 2 s (a n- a n-2... a 0 ) - (b n- b n-2... b 0 ) s 0 Hardware Design I (Chap. 4) 4 The sign bit after adding positive and negative values Assume signed 8-bit world If carry in and carry out of the sign bit are same, you only have to add them 0 Equal - Equal 0 +) 000000 +3 +) 000000 0000000 +2 0 00000 0 Equal - Equal 0 00000 000000-25 -26 +) 0 +) 0 00 000000 000000-65 +3-62 +63 +3 +66 Hardware Design I (Chap. 4) 42 2

The sign bit after adding positive and negative values Sign bit: equals to most left bit (MSB: most significant bit) If carry in and carry out of the sign bit are different, you have to treat it overflow The result exceeds range which can be represented with signed 8-bit From -28 to +27 Different Wrong result Different 0 Wrong result 0 +27 0-65 +) 000000 +3 +) 00000-25 0 000000-26 000000 +66 0 True result is +30 True result is -90 Hardware Design I (Chap. 4) 43 Short exercise Show arithmetic result under signed 8-bit world Show both binary and decimal notation Notate overflow if it occurs +) 0 0 0 0 0 0 0-67 +35 +) 0 0 0 +63 +27 Hardware Design I (Chap. 4) 44 22

Answer 0 0-67 +) 0 0 0 0 0 +35 +) 0 0 0 0 0 0-32 0 0 0 0 0 0 Overflow! True result is +90 +63 +27-66 Hardware Design I (Chap. 4) 45 Unify adder and subtracter We can unify adder and subtracter Control signal provide carry for least bit which is required to create twos complement Notation method of n-bit width signal a n b n Control signal 0: adding Negation of each bit n : subtracting MUX n Adder Carry for least bit n Hardware Design I (Chap. 4) 46 23

ALU (Arithmetic Logic Unit) Usually, we implement multiple arithmetic function to one circuit We can share logic gates between arithmetics e.g. AND/XOR operation of a and b are partial result of half adder We can save number of logic gates a b 8 8 ALU... Control (add, sub, compare, and, or, xor,...) 8 Hardware Design I (Chap. 4) 47 -bit right shift Movie digit to right Least significant bit (LSB) is banished MSB differs between shift method Logical shift: insert 0 Arithmetic shift: insert prior MSB The result becomes divided by 2 000 e.g. 00000(+7) -> 000000(+3) e.g. 00(-6) -> 0(-3) 0 Achieved with only wire connection Insert Copy Logical shift: 0 000 Arithmetic shift: 000 Hardware Design I (Chap. 4) 48 24

-bit left shift Movie digit to right 000 MSB is banished 0 is inserted into LSB 0 The result becomes multiplied by 2 e.g. 00000(+7) -> 00000(+4) Insert e.g. 00(-6) -> 000(-2) 0000 Also achieved with only wire connection You have to consider overflow if you execute arithmetic shift e.g. 0000000(-28) -> 00000000(0) Overflow! Hardware Design I (Chap. 4) 49 -bit rotate left (or right) -bit rotate left Move digit to left MSB is moved to LSB -bit rotate right Move digit to right LSB is moved to MSB Rotate left 000 000 Rotate right 000 000 Hardware Design I (Chap. 4) 50 25

Barrel shifter A circuit which can achieve arbitrary shift Usually, it permits several shift related operations n-bit shift gives result of multiplied by 2 n or divided by 2 n Shift amount c 2 c c 0 i 7 i 6 i 5 i 4 i 3 i 2 i i 0 Barrel shifter right/left arithmetic/logical o 7 o 6 o 5 o 4 o 3 o 2 o o 0 Hardware Design I (Chap. 4) 5 One implementation of barrel shifter Creating logical expression of each outputs and construct two level logic e.g. o 3 = r_l (i 0 c c 0 +i c +i 2 c 0 ) + c 2 c c 0 + r_l (i 4 c 0 +i 5 c +i 6 c c 0 +i 7 c 2 ) Assuming r_l = under right shift Shift amount c 2 c c 0 i 7 i 6 i 5 i 4 i 3 i 2 i i 0 Barrel shifter right/left (r_l) o 7 o 6 o 5 o 4 o 3 o 2 o o 0 Hardware Design I (Chap. 4) 52 26

The other implementation of barrel shifter Cascaded MUX which selects 2 n bits right shift, 2 n bits left shift, or no shift The length of critical path becomes long 0 i 7 i 6 i 5 i 4 i 3 i 2 i i 0 0 c 0 right/left MUX c right/left c 2 right/left MUX MUX o 7 o 6 o 5 o 4 o 3 o 2 o o 0 Hardware Design I (Chap. 4) 53 Example of operation 3-bit right shift 0 i 7 i 6 i 5 i 4 i 3 i 2 i i 0 0 c 0 right/left c right/left c 2 0 right/left MUX MUX MUX o 7 o 6 o 5 o 4 o 3 o 2 o o 0 Hardware Design I (Chap. 4) 54 27

Equivalent comparator -bit equivalent comparator becomes XNOR n-bit equivalent comparator AND of all digits Equivalent if all digits are equivalent Place AND gate with balanced tree a b out 0 0 0 0 0 0 a n-... a 2 a a 0 b n- b2 b b0... Hardware Design I (Chap. 4) 55 Comparator for grater than, less than, grater equal, and less equal (/2) -bit comparison a>b (GT: grater than) -> f = a b a>=b (GE: grater equal) -> f = a+b Abbreviation of compare or comparator: cmp Similarly, less than and less equal function will be implemented Also, we can exchange inputs and evaluate with GT and GE Prepare MUX at input side of comparator a b GT GE 0 0 0 0 0 0 0 0 a MUX cmp b MUX grater /less Hardware Design I (Chap. 4) 56 28

Comparator for grater than, less than, grater equal, and less equal (2/2) In multi-bit implementation, the result of higher digit is selected Prepare a logic which conduct Propagate lower result if a i =b i Propagate 0 if inputs a i <b i Propagate if inputs a i >b i a b 000 0 0000 0 0 a b 0 0 00 0 000 0 0 0 a b R out 0 0 R in 0 0 0 R in R out a n- b n- -bit cmp R in R out a i b i a 0 b 0 -bit cmp R in R -bit cmp 0 out Hardware Design I (Chap. 4) 57 Comparison with subtraction circuit If the result of a-b is positive, a>b is approved Check MSB under twos complement arithmetic If the n-bit value is unsigned value, you have to check with (n+)bit value arithmetic If the result of a-b is zero, a=b is approved If you implement cmp into ALU, you can use this method Dedicated cmp is used in dedicate purpose hardware Hardware Design I (Chap. 4) 58 29

Multiply -bit multiply is the same to AND 0 x 0 = 0, 0 x = 0, x 0 = 0, x = n-bit multiply becomes n of n-bit addition Iteration of -bit shift and addition The output becomes (2xn)-bit binary ) +) 0 00 0 0000 0 0000 00 ) A = a n- a n-2... a a 0 B = b n- b n-2... b b 0 A x b 0 A x b x 2 A x b 2 x 4 -bit left shift 2-bit left shift Hardware Design I (Chap. 4) 59 Example of 4-bit multiply (a 3 a 2 a a 0 ) x (b 3 b 2 b b 0 ) x) The result of -bit multiply (AND) a 3 a 2 a a 0 b 3 b 2 b b 0 a 3 b 0 a 2 b 0 a b 0 a 0 b 0 a 3 b a 2 b a b a 0 b +) a 3 b 2 a 2 b 2 a b 2 a 0 b 2 a 3 b 3 a 2 b 3 a b 3 a 0 b 3 z 7 z 6 z 5 z 4 z 3 z 2 z z 0 Hardware Design I (Chap. 4) 60 30

Array multiplier Align adder to array The operation time becomes O(n) a 3 a 2 a a 0 x) Note that represents adder (3-input 2-output) +) b 3 b 2 b b 0 a 3 b 0 a 2 b 0 a b 0 a 0 b 0 a 3 b a 2 b a b a 0 b a 3 b 2 a 2 b 2 a b 2 a 0 b 2 a 3 b 3 a 2 b 3 a b 3 a 0 b 3 Carry z 7 z 6 z 5 z 4 z 3 z 2 z z 0 Hardware Design I (Chap. 4) 6 Outline of Wallace tree multiplier One digit of n-bit multiply becomes summation of n binaries If we utilize carry save adder, we can construct 3-2 arithmetic tree. Group 3 binaries from summation of n and apply carry save addition 2. The result becomes summation of (2/3 x n) 3. Back to. until the summation becomes summation of 2 (usual addition) It can operate multiply with O(log n) Hardware Design I (Chap. 4) 62 3

Carry save adder (CSA) +) An array of n full adders Output sum of 3 binary inputs (2 binary outputs) There s no carry propagation Operation time is constant (independent to number of inputs) It can quickly translate sum of 3 binaries to sum of 2 binaries No relationships a a n- a n-2... a a n- b n- c n- a b c a 0 b 0 0 b n- b n-2... b b 0 c n- c n-2... c c 0 d n d n- d n-2... d d 0 e n e n- e n-2... e e 0 e n a b c_out c_in sum d n- e n- e 2... a b c_out c_in sum d e a b c_out c_in sum Hardware Design I (Chap. 4) 63 d 0 c 0 3-2 Wallace tree multiplier CSA CSA2 CLA a 3 a 2 a a 0 ) b 3 b 2 b b 0 a 3 b 0 a 2 b 0 a b 0 a 0 b 0 CSA a 3 b a 2 b a b a 0 b CSA2 +) a 3 b 2 a 2 b 2 a b 2 a 0 b 2 a 3 b 3 a 2 b 3 a b 3 a 0 b 3 CLA z 7 z 6 z 5 z 4 z 3 z 2 z z 0 Hardware Design I (Chap. 4) 64 32

Example of 8-bit multiply Number of summation becomes 2/3 under one CSA After O(log n) of CSAs, it becomes sum of 2 binaries x ) A = a 7 a 6... a a 0 B = b 7 b 6... b b 0 Apply CLA at final A x b 0 A x b x 2 A x b 2 x 4 A x b 3 x 8 A x b 4 x 6 A x b 5 x 32 A x b 6 x 64 A x b 7 x 28 CSA CSA CSA CSA CSA CSA Hardware Design I (Chap. 4) 65 Division Implement computation on paper frankly e.g. 07 divided by 3 Cannot subtract 0000000 0 Cannot subtract 00 000000 000 000000 000 -) 0000000000000 -) 0000000000000 000 000 -) 000000000000 6-bit left shift 000000 x 2 7 000 -) 00000000000 (7-bit left shift) 5-bit left shift 0000000000 Can subtract 00000 Hardware Design I (Chap. 4) 66 33

How to represent it to circuit? Implement computation on paper frankly Usually, it becomes sequential circuit (Chap. 6) If we achieve it with combinational logic, it requires much adders How to implement subtractable or not Firstly subtract and evaluate whether the result is negative value or not Constructed with subtracter and checking MSB If the value underruns 0, how do we treat it? Restoring method: add divisor to dividend Non-restoring method: detail is shown in later slide Hardware Design I (Chap. 4) 67 Restoring method If MSB of dividend after subtraction is, it adds divisor to restore In worst case, it requires twice adder per each digit Operation time becomes O(2n) e.g. 07 divided by 3 3 is denoted as 0...00 and -3 is denoted as...0 00 000000 000 +) 00000000 Add to 000 +) restore 00000000000000 00000000000 +) 0000000 000 Add to +) 00000000000000 restore 00000000000 +) 000000 0000000000000 Hardware Design I (Chap. 4) 68 34

Non-restoring method If temporal dividend becomes negative, this method adds following shifted dividend If temporal dividend is positive Subtract shifted dividend Quotient becomes if result is positive, otherwise 0 If temporal dividend is negative Add shifted dividend Quotient becomes if result is positive, otherwise 0 In some case, we have to compensate reminder Operation time becomes O(n) Hardware Design I (Chap. 4) 69 Example of non-restoring method Let s assume 37 divided by 6 Quotients 0 6 (00) 6 is denoted as 00 and -6 is denoted as 00 0 0 0 0 0 37 0-6x2 3 0 0 0 0 0 0 0 +6x2 2 0 0 0 0 0 0 0 0 0 0 0-6x2 0 0 0 0 0 0 0 0 0 0-6x2 0 0 0 0-48 - +24 3-2 -6 If reminder becomes negative, correct remainder by adding +6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Remainder (=) Hardware Design I (Chap. 4) 70 35

Utilizing higher radix under division We can speedup division by utilizing higher radix Prior division is radix-2 division Only prepare n left shifted divisor e.g. radix-4 division Prepare following divisor. n left shifted 2. n+ left shifted 3. (n left shifted) + (n+ left shifted) Subtract above three from dividend Get 2-digit of quotient simultaneously Quotient becomes 00 if all of them are not subtractable Quotient becomes 0 if only. is subtractable Quotient becomes 0 if. and 2. are subtractable Quotient becomes if all of them are subtractable Hardware Design I (Chap. 4) 7 Hardware Design I (Chap. 4) 72 36

Quiz What is the correct organization of 8- MUX? Hardware Design I (Chap. 4) 73 Answer Both and 4 are correct answer is based on AND-OR logic gate based organization 4 is based on transmission gate based organization Hardware Design I (Chap. 4) 74 37

Hardware Design I (Chap. 4) 75 Hardware Design I (Chap. 4) 76 38