rithmetic uilding locks Datapath elements dder design Static adder Dynamic adder Multiplier design rray multipliers Shifters, Parity circuits ECE 261 Krish Chakrabarty 1 Generic Digital Processor Input-Output MEMORY DTPTH CONTROL ECE 261 Krish Chakrabarty 2
uilding locks for Digital rchitectures rithmetic unit - it-sliced datapath(adder, multiplier, shifter, comparator, etc.) Memory - RM, ROM, uffers, Shift registers Control - Finite state machine (PL, random logic.) - Counters Interconnect - Switches -rbiters - us ECE 261 Krish Chakrabarty 3 Signals it-sliced Design Metal 2 (control) Data Control Control Metal 1 (data) it 3 Data-in Register dder Shifter Multiplier it 2 it 1 it 0 Data-out Tile identical processing elements ECE 261 Krish Chakrabarty 4
Full-dder Cin Full adder Sum Cout ECE 261 Krish Chakrabarty 5 The inary dder Cin Full adder Sum Cout Sum = C = + + + C o = + + ECE 261 Krish Chakrabarty 6
Sum and Carry as a functions of P, G Define 3 new variable which ONLY depend on, Generate (G) = Propagate (P) = + Delete = ECE 261 Krish Chakrabarty 7 The Ripple-Carry dder 0 0 1 1 2 2 3 3 C o,0 C o,1 C o,2 F F F F (=,1 ) S 0 S 1 S 2 S 3 Worst case delay linear with the number of bits t d =O(N) t d = (N-1)t carry + t sum Goal: Make the fastest possible carry path circuit ECE 261 Krish Chakrabarty 8
Complimentary Static CMOS Full dder X S Note: 1) S = + C o ( + + ) 2) Placement of 3) Two inverter stages for each C o C o O(N) delay 28 Transistors ECE 261 Krish Chakrabarty 9 Inversion Property Inverting all inputs results in inverted outputs F C o F C o S S ECE 261 Krish Chakrabarty 10
Minimize Critical Path by Reducing Inverting Stages Even Cell Odd Cell 0 1 1 0 2 3 3 2 C o,0 C o,1 C o,2 F F F F S 0 S 1 S 2 S 3 Exploit Inversion Property Need two different types of cells, F : no inverter in carry path ECE 261 Krish Chakrabarty 11 better structure: the Mirror dder -Propagate Kill C o S -Propagate Generate 24 transistors ECE 261 Krish Chakrabarty 12
The Mirror dder Symmetrical NMOS and PMOS chains identical rising and falling transitions if the NMOS and PMOS devices are properly sized. Maximum of two series transistors in the carry-generation circuitry. Critical issue: minimization of the capacitance at C o. Reduction of the diffusion capacitances important. The capacitance at C o composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. Transistors connected to placed closest to output. Only the transistors in carry stage have to be optimized for speed. ll transistors in the sum stage can be minimal size. ECE 261 Krish Chakrabarty 13 NP-CMOS dder S 1 1 17 transistors, ignoring extra inverters for inputs and outputs 1 1 1 1 0 2 1 1 Ci1 1 1 1 0 0 0 0 0 0 0 0 0 S 0 0 Carry Path ECE 261 Krish Chakrabarty 14
Manchester Carry Chain P 0 P 1 P 2 P 3 P 4 C o,4 G 0 G 1 G 2 G 3 G 4 Only nmos transmission gates used. Why? Delay of long series of pass gates: add buffers ECE 261 Krish Chakrabarty 15 Carry-ypass dder P 0 G 1 P 0 G 1 P 2 G 2 P 3 G 3 C o,0 C o,1 C o,2 F F F F P 0 G 1 P 0 G 1 P 2 G 2 P 3 G 3 C o,0 C o,1 C o,2 F F F F P=P o P 1 P 2 P 3 Idea: If (P0 and P1 and P2 and P3 = 1) then C o3 =C 0, else kill or generate. ECE 261 Krish Chakrabarty 16
Manchester-Carry Implementation P 0 P 1 G 0 G 1 P 2 G 2 P 3 G 3 P P ECE 261 Krish Chakrabarty 17 Carry-ypass dder (cont.) it 0-3 it 4-7 it 8-11 it 12-15 Carry Carry Carry Carry Propagation Propagation Propagation Propagation Sum Sum Sum Sum Design N-bit adder using N/M equal length stages e.g. N = 16, M = 4 What is the critical path? t p = t setup + Mt carry + (N/M-1)t bypass + M tcarry + t sum, i.e. O(N) ECE 261 Krish Chakrabarty 18
Carry Ripple versus Carry ypass t p ripple adder bypass adder 4..8 N ECE 261 Krish Chakrabarty 19 Carry-Select dder Generate carry out for both 0 and 1 incoming carries P,G Carry Propagation 4-bit block for bits k, k+1, k+2, k+3 Carry Propagation C o,k-1 Co,k+3 Carry Vector SumGeneration ECE 261 Krish Chakrabarty 20
Carry Select dder: Critical Path it 0-3 it 4-7 it 8-11 it 12-15 Carry Carry Carry Carry Carry Carry Carry Carry C o,7 C o,11 C o,15 S 0-3 S 4-7 S 8-11 S 12-15 ECE 261 Krish Chakrabarty 21 Carry-Select dder: Linear Configuration it 0-3 it 4-7 it 8-11 it 12-15 Carry (1) Carry (1) (5) (5) (6) Carry Carry (5) Carry Carry (5) (7) (8) Carry Carry (5) C o,7 C o,11 C o,15 S 0-3 S 4-7 S 8-11 S 12-15 re equal-sized blocks best? ECE 261 Krish Chakrabarty 22
Linear Carry Select it 0-3 it 4-7 it 8-11 it 12-15 Carry Carry Carry Carry Carry Carry Carry Carry C o,7 C o,11 C o,15 S 0-3 S 4-7 S 8-11 S 12-15 ECE 261 Krish Chakrabarty 23 Square Root Carry Select it 0-1 it 2-4 it 5-8 it 9-13 (1) Carry (1) Carry (3) (3) (4) Carry Carry (4) Carry Carry (5) (5) (6) Carry Carry (6) C o,7 C o,11 C o,15 i.e., O( N) ECE 261 Krish Chakrabarty 24
dder Delays - Comparison 50.0 40.0 ripple adder 30.0 tp 20.0 linear select 10.0 square root select 0.0 0.0 20.0 40.0 60.0 N ECE 261 Krish Chakrabarty 25 Carry Look-head - asic Idea 0, 0 1, 1 N-1, N-1... P0,1 P 1,N-1 P N-1... S 0 S 1 S N-1 Delay independent of the number of bits ECE 261 Krish Chakrabarty 26
Carry-Lookahead dders High fanin for large N Implement as CL slices, or use 2nd level lookahead generator 4 4 4 4 4 4 4 4 16-bit CL based on 4-bit slices and ripple carry 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Faster implementation CL generator ECE 261 Krish Chakrabarty 27 Look-head: Topology G 3 G 2 G 1 G 0 P 0 P 1 P 2 P 3 Gnd ECE 261 Krish Chakrabarty 28