Timed Automata VINO 2011

Size: px
Start display at page:

Download "Timed Automata VINO 2011"

Transcription

1 Timed Automata VINO 2011 VeriDis Group - LORIA July 18, 2011

2 Content 1 Introduction 2 Timed Automata 3 Networks of timed automata

3 Motivation Formalism for modeling and verification of real-time systems. Introduced by Alur and Dill (1990,1994). Developed in parallel (and independently) of timed extension of process algebras. Nondeterministic finite automata + real-valued clocks.

4 Motivation Example Formalism for modeling and verification of real-time systems. Introduced by Alur and Dill (1990,1994). Developed in parallel (and independently) of timed extension of process algebras. Nondeterministic finite automata + real-valued clocks. x > 14, press Off Light Bright press, x := 0 x 14, press press

5 Clock constraints Let fix a finite set C = {x, y,... } whose elements represent the clock names. Definition (Clock constraints) The set B(C) of clock constraints over the set of clocks C is defined by the abstract syntax g, g 1, g 2 ::= x n g 1 g 2 where x C is a clock, n N and {, <, =, >, }.

6 Clock constraints Let fix a finite set C = {x, y,... } whose elements represent the clock names. Definition (Clock constraints) The set B(C) of clock constraints over the set of clocks C is defined by the abstract syntax g, g 1, g 2 ::= x n g 1 g 2 where x C is a clock, n N and {, <, =, >, }. Example x 5 0 x < 5 x > 3 y = 2

7 Clock operations Valuation v : C R 0 is a valuation function and v(x) stores the amount of time elapsed from the last time x was reset. Delay for each d R 0, the valuation v + d is called delay and defined by Reset (v + d)(x) = v(x) + d for each x C. for each r C, the valuation v[r] is called reset and defined by { 0 if x r, v[r](x) = v(x) otherwise.

8 Evaluation Definition Let g B(C) be a clock constraint for a given set of clocks C and let v : C R 0 be a clock valuation. The evaluation of clock constraints (v = g) is defined inductively on the structure of g by v = x n iff v(x) n, v = g 1 g 2 iff v = g 1 v = g 2, where x C is a clock, n N, g 1, g 2 B(C) and {, <, =, >, }.

9 Evaluation Definition Let g B(C) be a clock constraint for a given set of clocks C and let v : C R 0 be a clock valuation. The evaluation of clock constraints (v = g) is defined inductively on the structure of g by v = x n iff v(x) n, v = g 1 g 2 iff v = g 1 v = g 2, where x C is a clock, n N, g 1, g 2 B(C) and {, <, =, >, }. Example Let C = {x, y}, and v = [x = 1.2; y = 3.01] a valuation, then v = x > 1 x 2

10 Evaluation Definition Let g B(C) be a clock constraint for a given set of clocks C and let v : C R 0 be a clock valuation. The evaluation of clock constraints (v = g) is defined inductively on the structure of g by v = x n iff v(x) n, v = g 1 g 2 iff v = g 1 v = g 2, where x C is a clock, n N, g 1, g 2 B(C) and {, <, =, >, }. Example Let C = {x, y}, and v = [x = 1.2; y = 3.01] a valuation, then v = x > 0 y 3

11 Evaluation Definition Let g B(C) be a clock constraint for a given set of clocks C and let v : C R 0 be a clock valuation. The evaluation of clock constraints (v = g) is defined inductively on the structure of g by v = x n iff v(x) n, v = g 1 g 2 iff v = g 1 v = g 2, where x C is a clock, n N, g 1, g 2 B(C) and {, <, =, >, }. Example Let C = {x, y}, and v = [x = 1.2; y = 3.01] a valuation, then v = y 3 x 1

12 Clocks equivalence Definition (Clocks equivalence) Two clock constraints g 1 and g 2 are equivalent iff they are satisfied by the same valuations, that is, for each valuation v, v = g 1 v = g 2.

13 Clocks equivalence Definition (Clocks equivalence) Two clock constraints g 1 and g 2 are equivalent iff they are satisfied by the same valuations, that is, for each valuation v, v = g 1 v = g 2. Example The clock constraints x 5 x 5 and x = 5 are equivalent and the same for y 5 y 0 and y 5.

14 Interval closed constraints Definition (Interval closed constraints) A constraint g is called interval closed if, for each valuation v and non-negative real number d, it holds that v = g and v + d = g imply v + d = g for each 0 d d.

15 Interval closed constraints Definition (Interval closed constraints) A constraint g is called interval closed if, for each valuation v and non-negative real number d, it holds that v = g and v + d = g imply v + d = g for each 0 d d. Lemma Every constraint in B(C) is interval closed.

16 Content 1 Introduction 2 Timed Automata 3 Networks of timed automata

17 Timed Automata Definition (Timed Automata) A timed automaton over a finite set of clocks C and a finite set of actions Act is a quadruple where L is a finite set of locations, l 0 L is the initial location, (L, l 0, E, I), E L B(C) Act 2 C L is a finite set of edges, and I : L B(C) assigns invariants to locations.

18 Timed Automata Definition (Timed Automata) A timed automaton over a finite set of clocks C and a finite set of actions Act is a quadruple where L is a finite set of locations, l 0 L is the initial location, (L, l 0, E, I), E L B(C) Act 2 C L is a finite set of edges, and I : L B(C) assigns invariants to locations. The edge (l, g, a, r, l ) is usually written as l g,a,r l.

19 Notion of state Knowing the present location is not enough to determine which of the outgoing edges can be taken next. A pair (l, v) in a timed automaton is a valid state if v satisfies the invariant of l. Initially, the control location is l 0 and the value of each clock is 0. Transitions: We can follow an edge if it guard is satisfied by the current location, or We can delay in the current location (only if the invariant is satisfied by v + d, and as B(C) is interval closed, in all the intermediate valuations).

20 Semantics - TLTS Definition (TLTS) Let A = (L, l 0, E, I) be a timed automaton over a set of clocks C and a set of actions Act. We define the timed transition system T (A) generated by A as T (A) = (Proc, Lab, { α α Lab}), where: Proc = {(l, v) (l, v) L (C R 0 ) and v = I(l)};

21 Semantics - TLTS Definition (TLTS) Let A = (L, l 0, E, I) be a timed automaton over a set of clocks C and a set of actions Act. We define the timed transition system T (A) generated by A as T (A) = (Proc, Lab, { α α Lab}), where: Proc = {(l, v) (l, v) L (C R 0 ) and v = I(l)}; Lab = Act R 0 is the set of labels; and

22 Semantics - TLTS Definition (TLTS) Let A = (L, l 0, E, I) be a timed automaton over a set of clocks C and a set of actions Act. We define the timed transition system T (A) generated by A as T (A) = (Proc, Lab, { α α Lab}), where: Proc = {(l, v) (l, v) L (C R 0 ) and v = I(l)}; Lab = Act R 0 is the set of labels; and the transition relation is defined by a (l, v) (l, v ) if there is an edge l g,a,r l E such that v = g, v = v[r] and v = I(l ),

23 Semantics - TLTS Definition (TLTS) Let A = (L, l 0, E, I) be a timed automaton over a set of clocks C and a set of actions Act. We define the timed transition system T (A) generated by A as T (A) = (Proc, Lab, { α α Lab}), where: Proc = {(l, v) (l, v) L (C R 0 ) and v = I(l)}; Lab = Act R 0 is the set of labels; and the transition relation is defined by a (l, v) (l, v ) if there is an edge l g,a,r l E such that v = g, v = v[r] and v = I(l ), d (l, v) (l, v + d) forall d R 0 such that v = I(l) and v + d = I(l).

24 Semantics - TLTS - Example Example x 2 l 0 x 1, a, x := 0 a a 0 (l 0, [x = 0]) 0.6 (l 0, [x = 0.6]) 0.4 (l 0, [x = 1]) 0.3 (l 0, [x = 1.3]) 0.7 (l 0, [x = 2]) a Figure: A timed automaton and one timed transition system of it.

25 Constraints in guards vs. invariant Example l 0 x 1, a, x := 0 Value clock x Time elapsed

26 Constraints in guards vs. invariant Example x 1 l 0 a, x := 0 Value clock x Time elapsed

27 Timed automaton - Example Example x 5, start, {x, y} := 0 x 10 Rest x 60 y 4 Work y 1, hit, y := 0 x 40, done, x := 0

28 Timed automaton - Example Example x 5, start, {x, y} := 0 x 10 Rest x 60 y 4 Work y 1, hit, y := 0 x 40, done, x := 0 Working periods of at least 40 min and at most 60 min.

29 Timed automaton - Example Example x 5, start, {x, y} := 0 x 10 Rest x 60 y 4 Work y 1, hit, y := 0 x 40, done, x := 0 Working periods of at least 40 min and at most 60 min. Resting periods of at least 5 min and at most 10 min.

30 Timed automaton - Example Example x 5, start, {x, y} := 0 x 10 Rest x 60 y 4 Work y 1, hit, y := 0 x 40, done, x := 0 Working periods of at least 40 min and at most 60 min. Resting periods of at least 5 min and at most 10 min. During working, hit-actions are in a range of 1 to 4 min.

31 Content 1 Introduction 2 Timed Automata 3 Networks of timed automata

32 Motivation Independent components running in parallel and communication. Such systems depend also on timing features. Process algebras such as CCS and TCCS provides this. Communication with synchronization (instantaneous).

33 Motivation Example Independent components running in parallel and communication. Such systems depend also on timing features. Process algebras such as CCS and TCCS provides this. Communication with synchronization (instantaneous). x > 14, press? Off Light Bright press?, x := 0 x 14, press? press? y = 3, press!, y := 0 press!, y := 0 U U y 3

34 Formally... Let Chan be the set of channel names, N the set of ordinary action names and Act = {c! c Chan} {c? c Chan} N. Definition (Network of timed automata) Let n be a positive integer and, for each i {1,..., n}, let A i = (L i, l i 0, E i, I i ) be a timed automaton over a set of clocks C and the set of actions Act. We call the composition A = A 1 A 2 A n a network of timed automata with n parallel components.

35 Semantics - TLTS Definition (TLTS) Let A = A 1 A 2 A n, where A i = (L i, l i 0, E i, I i ) for each i {1,..., n}, be a network of timed automata over a set of clocks C and actions Act. We define the TLTS T (A) generated by the network A as T (A) = (Proc, Lab, { α α Lab}).

36 Semantics -TLTS (2) Here: Proc = {(l 1, l 2,..., l n, v) (l 1, l 2,..., l n, v) L 1 L 2 L n (C R 0 ) and v = i {1,...,n} I i(l i ), Lab = N {τ} R 0 is the set of labels, and the transition relation is defined as (l 1,..., l i,..., l n, v) a (l 1,..., l i,..., l n, v ) if a N and g,a,r there is an edge (l i l i ) E i in the ith component automaton such that v = g, v = v[r] and v = I i (l i ) k i I k (l k );

37 Semantics -TLTS (2) Here: Proc = {(l 1, l 2,..., l n, v) (l 1, l 2,..., l n, v) L 1 L 2 L n (C R 0 ) and v = i {1,...,n} I i(l i ), Lab = N {τ} R 0 is the set of labels, and the transition relation is defined as (l 1,..., l i,..., l j,..., l n, v) τ (l 1,..., l i,..., l j,..., l n, v ) if g i,α,r i i j and there are edges (l i l i ) E i and g j,β,r j (l j l j ) E j such that α and β are complementary, v = g i g j, v = v[r i r j ] and v = I i (l i) I j (l j) I k (l k ); k i,j

38 Semantics -TLTS (2) Here: Proc = {(l 1, l 2,..., l n, v) (l 1, l 2,..., l n, v) L 1 L 2 L n (C R 0 ) and v = i {1,...,n} I i(l i ), Lab = N {τ} R 0 is the set of labels, and the transition relation is defined as (l 1,..., l n, v) d (l 1,..., l n, v + d) for all d R 0 such that v + d = i {1,...,n} I i (l i ) for each real number d in the interval [0, d].

39 Semantics - TLTS - Example Example x > 14, press? Off Light Bright press?, x := 0 x 14, press? y = 3, press!, y := 0 press? press!, y := 0 U U y 3 τ (Off, U, [0; 0]) (Light, U 3, [0; 0]) (Light, U τ, [3; 3]) (Bright, U, [3; 0]) τ 3 (Off, U, [9; 3]) (Off, U, [6; 0]) (Bright, U, [6; 3]) 3 τ

40 Limitations and extensions Anomalies Time deadlock: not discrete transition is enabled and time cannot proceed. Infinitely many discrete transitions performed in a finite amount of time. Extensions Urgency: a discrete action is taken before some deadline. Invariants - may result in unnecessary deadlock. Additional predicates decorating translations. Reset to values 0, reset to the value of another clock - reachability still decidable. Allow clocks to grow at different rates - Undecidable. Weighted timed automata. 1-safe timed Petri nets.

Lecture 11: Timed Automata

Lecture 11: Timed Automata Real-Time Systems Lecture 11: Timed Automata 2014-07-01 11 2014-07-01 main Dr. Bernd Westphal Albert-Ludwigs-Universität Freiburg, Germany Contents & Goals Last Lecture: DC (un)decidability This Lecture:

More information

Models for Efficient Timed Verification

Models for Efficient Timed Verification Models for Efficient Timed Verification François Laroussinie LSV / ENS de Cachan CNRS UMR 8643 Monterey Workshop - Composition of embedded systems Model checking System Properties Formalizing step? ϕ Model

More information

Real-Time Systems. Lecture 10: Timed Automata Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany main

Real-Time Systems. Lecture 10: Timed Automata Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany main Real-Time Systems Lecture 10: Timed Automata 2013-06-04 10 2013-06-04 main Dr. Bernd Westphal Albert-Ludwigs-Universität Freiburg, Germany Contents & Goals Last Lecture: PLC, PLC automata This Lecture:

More information

Recent results on Timed Systems

Recent results on Timed Systems Recent results on Timed Systems Time Petri Nets and Timed Automata Béatrice Bérard LAMSADE Université Paris-Dauphine & CNRS berard@lamsade.dauphine.fr Based on joint work with F. Cassez, S. Haddad, D.

More information

Timed Automata. Semantics, Algorithms and Tools. Zhou Huaiyang

Timed Automata. Semantics, Algorithms and Tools. Zhou Huaiyang Timed Automata Semantics, Algorithms and Tools Zhou Huaiyang Agenda } Introduction } Timed Automata } Formal Syntax } Operational Semantics } Verification Problems } Symbolic Semantics & Verification }

More information

Modelling Real-Time Systems. Henrik Ejersbo Jensen Aalborg University

Modelling Real-Time Systems. Henrik Ejersbo Jensen Aalborg University Modelling Real-Time Systems Henrik Ejersbo Jensen Aalborg University Hybrid & Real Time Systems Control Theory Plant Continuous sensors actuators Task TaskTask Controller Program Discrete Computer Science

More information

The algorithmic analysis of hybrid system

The algorithmic analysis of hybrid system The algorithmic analysis of hybrid system Authors: R.Alur, C. Courcoubetis etc. Course teacher: Prof. Ugo Buy Xin Li, Huiyong Xiao Nov. 13, 2002 Summary What s a hybrid system? Definition of Hybrid Automaton

More information

Timed Automata. Chapter Clocks and clock constraints Clock variables and clock constraints

Timed Automata. Chapter Clocks and clock constraints Clock variables and clock constraints Chapter 10 Timed Automata In the previous chapter, we have discussed a temporal logic where time was a discrete entities. A time unit was one application of the transition relation of an LTS. We could

More information

An introduction to Uppaal and Timed Automata MVP5 1

An introduction to Uppaal and Timed Automata MVP5 1 An introduction to Uppaal and Timed Automata MVP5 1 What is Uppaal? (http://www.uppaal.com/) A simple graphical interface for drawing extended finite state machines (automatons + shared variables A graphical

More information

Verification of Polynomial Interrupt Timed Automata

Verification of Polynomial Interrupt Timed Automata Verification of Polynomial Interrupt Timed Automata Béatrice Bérard 1, Serge Haddad 2, Claudine Picaronny 2, Mohab Safey El Din 1, Mathieu Sassolas 3 1 Université P. & M. Curie, LIP6 2 ENS Cachan, LSV

More information

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Borzoo Bonakdarpour and Sandeep S. Kulkarni Software Engineering and Network Systems Laboratory, Department of Computer Science

More information

Lecture 6: Reachability Analysis of Timed and Hybrid Automata

Lecture 6: Reachability Analysis of Timed and Hybrid Automata University of Illinois at Urbana-Champaign Lecture 6: Reachability Analysis of Timed and Hybrid Automata Sayan Mitra Special Classes of Hybrid Automata Timed Automata ß Rectangular Initialized HA Rectangular

More information

Undecidability Results for Timed Automata with Silent Transitions

Undecidability Results for Timed Automata with Silent Transitions Fundamenta Informaticae XXI (2001) 1001 1025 1001 IOS Press Undecidability Results for Timed Automata with Silent Transitions Patricia Bouyer LSV, ENS Cachan, CNRS, France bouyer@lsv.ens-cachan.fr Serge

More information

An Introduction to Hybrid Systems Modeling

An Introduction to Hybrid Systems Modeling CS620, IIT BOMBAY An Introduction to Hybrid Systems Modeling Ashutosh Trivedi Department of Computer Science and Engineering, IIT Bombay CS620: New Trends in IT: Modeling and Verification of Cyber-Physical

More information

Timed Automata: Semantics, Algorithms and Tools

Timed Automata: Semantics, Algorithms and Tools Timed Automata: Semantics, Algorithms and Tools Johan Bengtsson and Wang Yi Uppsala University {johanb,yi}@it.uu.se Abstract. This chapter is to provide a tutorial and pointers to results and related work

More information

Time and Timed Petri Nets

Time and Timed Petri Nets Time and Timed Petri Nets Serge Haddad LSV ENS Cachan & CNRS & INRIA haddad@lsv.ens-cachan.fr DISC 11, June 9th 2011 1 Time and Petri Nets 2 Timed Models 3 Expressiveness 4 Analysis 1/36 Outline 1 Time

More information

Time(d) Petri Net. Serge Haddad. Petri Nets 2016, June 20th LSV ENS Cachan, Université Paris-Saclay & CNRS & INRIA

Time(d) Petri Net. Serge Haddad. Petri Nets 2016, June 20th LSV ENS Cachan, Université Paris-Saclay & CNRS & INRIA Time(d) Petri Net Serge Haddad LSV ENS Cachan, Université Paris-Saclay & CNRS & INRIA haddad@lsv.ens-cachan.fr Petri Nets 2016, June 20th 2016 1 Time and Petri Nets 2 Time Petri Net: Syntax and Semantic

More information

Real-Time Systems. Lecture 15: The Universality Problem for TBA Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany

Real-Time Systems. Lecture 15: The Universality Problem for TBA Dr. Bernd Westphal. Albert-Ludwigs-Universität Freiburg, Germany Real-Time Systems Lecture 15: The Universality Problem for TBA 2013-06-26 15 2013-06-26 main Dr. Bernd Westphal Albert-Ludwigs-Universität Freiburg, Germany Contents & Goals Last Lecture: Extended Timed

More information

Reachability Results for Timed Automata with Unbounded Data Structures

Reachability Results for Timed Automata with Unbounded Data Structures Acta Informatica manuscript No. (will be inserted by the editor) Reachability Results for Timed Automata with Unbounded Data Structures Ruggero Lanotte Andrea Maggiolo-Schettini Angelo Troina Received:

More information

Saarland University Faculty of Natural Sciences and Technology I Department of Computer Science. Bachelor Thesis. From Uppaal To Slab.

Saarland University Faculty of Natural Sciences and Technology I Department of Computer Science. Bachelor Thesis. From Uppaal To Slab. Saarland University Faculty of Natural Sciences and Technology I Department of Computer Science Bachelor Thesis From Uppaal To Slab submitted by Andreas Abel submitted August 26, 2009 Supervisor Prof.

More information

for System Modeling, Analysis, and Optimization

for System Modeling, Analysis, and Optimization Fundamental Algorithms for System Modeling, Analysis, and Optimization Stavros Tripakis UC Berkeley EECS 144/244 Fall 2013 Copyright 2013, E. A. Lee, J. Roydhowdhury, S. A. Seshia, S. Tripakis All rights

More information

Dense-Timed Pushdown Automata

Dense-Timed Pushdown Automata Dense-Timed Pushdown Automata Parosh Aziz Abdulla Uppsala University Sweden Mohamed Faouzi Atig Uppsala University Sweden Jari Stenman Uppsala University Sweden Abstract We propose a model that captures

More information

An Introduction to Hybrid Systems Modeling

An Introduction to Hybrid Systems Modeling CS620, IIT BOMBAY An Introduction to Hybrid Systems Modeling Ashutosh Trivedi Department of Computer Science and Engineering, IIT Bombay CS620: New Trends in IT: Modeling and Verification of Cyber-Physical

More information

Task Automata: Schedulability, Decidability and Undecidability

Task Automata: Schedulability, Decidability and Undecidability Task Automata: Schedulability, Decidability and Undecidability Elena Fersman 1, Pavel Krcal, Paul Pettersson 2 and Wang Yi 3 Email: fpavelk,paupet,yig@it.uu.se Department of Information Technology Uppsala

More information

models, languages, dynamics Eugene Asarin PIMS/EQINOCS Workshop on Automata Theory and Symbolic Dynamics LIAFA - University Paris Diderot and CNRS

models, languages, dynamics Eugene Asarin PIMS/EQINOCS Workshop on Automata Theory and Symbolic Dynamics LIAFA - University Paris Diderot and CNRS models, s, LIAFA - University Paris Diderot and CNRS PIMS/EQINOCS Workshop on Automata Theory and Symbolic Dynamics Context A model for verification of real-time systems Invented by Alur and Dill in early

More information

Formally Correct Monitors for Hybrid Automata. Verimag Research Report n o TR

Formally Correct Monitors for Hybrid Automata. Verimag Research Report n o TR Formally Correct Monitors for Hybrid Automata Goran Frehse, Nikolaos Kekatos, Dejan Nickovic Verimag Research Report n o TR-2017-5 September 20, 2017 Verimag, University of Grenoble Alpes, Grenoble, France.

More information

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1

Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Complexity Issues in Automated Addition of Time-Bounded Liveness Properties 1 Borzoo Bonakdarpour and Sandeep S. Kulkarni Software Engineering and Network Systems Laboratory, Department of Computer Science

More information

Partial Order Reductions for Timed Systems

Partial Order Reductions for Timed Systems Partial Order Reductions for Timed Systems Johan Bengtsson 1 Bengt Jonsson 1 Johan Lilius 2 Wang Yi 1 1 Department of Computer Systems, Uppsala University, Sweden. Email: {bengt,johanb,yi}@docs.uu.se 2

More information

MODEL CHECKING TIMED SAFETY INSTRUMENTED SYSTEMS

MODEL CHECKING TIMED SAFETY INSTRUMENTED SYSTEMS TKK Reports in Information and Computer Science Espoo 2008 TKK-ICS-R3 MODEL CHECKING TIMED SAFETY INSTRUMENTED SYSTEMS Jussi Lahtinen ABTEKNILLINEN KORKEAKOULU TEKNISKA HÖGSKOLAN HELSINKI UNIVERSITY OF

More information

The Minimal Cost Reachability Problem in Priced Timed Pushdown Systems

The Minimal Cost Reachability Problem in Priced Timed Pushdown Systems The Minimal Cost Reachability Problem in Priced Timed Pushdown Systems Parosh Aziz Abdulla, Mohamed Faouzi Atig, and Jari Stenman Uppsala University, Sweden Abstract. This paper introduces the model of

More information

TIMED automata, introduced by Alur and Dill in [3], have

TIMED automata, introduced by Alur and Dill in [3], have 1 Language Inclusion Checking of Timed Automata with Non-Zenoness Xinyu Wang, Jun Sun, Ting Wang, and Shengchao Qin Abstract Given a timed automaton P modeling an implementation and a timed automaton S

More information

540 IEEE TRANSACTIONS ON AUTOMATIC CONTROL, VOL. 43, NO. 4, APRIL Algorithmic Analysis of Nonlinear Hybrid Systems

540 IEEE TRANSACTIONS ON AUTOMATIC CONTROL, VOL. 43, NO. 4, APRIL Algorithmic Analysis of Nonlinear Hybrid Systems 540 IEEE TRANSACTIONS ON AUTOMATIC CONTROL, VOL. 43, NO. 4, APRIL 1998 Algorithmic Analysis of Nonlinear Hybrid Systems Thomas A. Henzinger, Pei-Hsin Ho, Howard Wong-Toi Abstract Hybrid systems are digital

More information

When are Timed Automata Determinizable?

When are Timed Automata Determinizable? When are Timed Automata Determinizable? Christel Baier 1, Nathalie Bertrand 2, Patricia Bouyer 3, and Thomas Brihaye 4 1 Technische Universität Dresden, Germany 2 INRIA Rennes Bretagne Atlantique, France

More information

Model Checking Real-Time Systems

Model Checking Real-Time Systems Model Checking Real-Time Systems Patricia Bouyer, Uli Fahrenberg, Kim G. Larsen, Nicolas Markey, Joël Ouaknine, and James Worrell Abstract This chapter surveys timed automata as a formalism for model checking

More information

Classes and conversions

Classes and conversions Classes and conversions Regular expressions Syntax: r = ε a r r r + r r Semantics: The language L r of a regular expression r is inductively defined as follows: L =, L ε = {ε}, L a = a L r r = L r L r

More information

The efficiency of identifying timed automata and the power of clocks

The efficiency of identifying timed automata and the power of clocks The efficiency of identifying timed automata and the power of clocks Sicco Verwer a,b,1,, Mathijs de Weerdt b, Cees Witteveen b a Eindhoven University of Technology, Department of Mathematics and Computer

More information

Real-Time Reactive System - CCS with Time Delays

Real-Time Reactive System - CCS with Time Delays Real-Time Reactive System - CCS with Time Delays Wai Leung Sze (Stephen) Swansea University VINO 18th July 2011 Overview Introduction of real-time reactive system Describing the real-time reactive system

More information

From games to executables!

From games to executables! From games to executables! Implementations of strategies generated from UPPAAL TIGA by Kenneth Blanner Holleufer and Jesper Brix Rosenkilde THESIS for the degree of MASTER OF SCIENCE (Master of computer

More information

Laboratoire Spécification & Vérification. Language Preservation Problems in Parametric Timed Automata. Étienne André and Nicolas Markey

Laboratoire Spécification & Vérification. Language Preservation Problems in Parametric Timed Automata. Étienne André and Nicolas Markey Language Preservation Problems in Parametric Timed Automata Étienne André and Nicolas Markey June 2015 Research report LSV-15-05 (Version 1) Laboratoire Spécification & Vérification École Normale Supérieure

More information

Synchronized Recursive Timed Automata

Synchronized Recursive Timed Automata Synchronized Recursive Timed Automata Yuya Uezato 1 and Yasuhiko Minamide 2 1 University of Tsukuba uezato@score.cs.tsukuba.ac.jp 2 Tokyo Institute of Technology minamide@is.titech.ac.jp Abstract. We present

More information

Decision Problems for Parametric Timed Automata

Decision Problems for Parametric Timed Automata Decision Problems for Parametric Timed Automata Étienne André 1,2, Didier Lime 1, and Olivier H. Roux 1 1 École Centrale de Nantes, IRCCyN, CNRS, UMR 6597, France 2 Université Paris 13, Sorbonne Paris

More information

A Modal Specification Theory for Timing Variability

A Modal Specification Theory for Timing Variability University of Pennsylvania ScholarlyCommons Technical Reports (CIS) Department of Computer & Information Science 11-13-2013 A Modal Specification Theory for Timing Variability Andrew King University of

More information

Semantics and Verification

Semantics and Verification Semantics and Verification Lecture 2 informal introduction to CCS syntax of CCS semantics of CCS 1 / 12 Sequential Fragment Parallelism and Renaming CCS Basics (Sequential Fragment) Nil (or 0) process

More information

Robustness and Implementability of Timed Automata

Robustness and Implementability of Timed Automata Robustness and Implementability of Timed Automata Martin De Wulf, Laurent Doyen, Nicolas Markey, and Jean-François Raskin Computer Science Departement, Université Libre de Bruxelles, Belgium Abstract.

More information

Undecidability of Coverability and Boundedness for Timed-Arc Petri Nets with Invariants

Undecidability of Coverability and Boundedness for Timed-Arc Petri Nets with Invariants Undecidability of Coverability and Boundedness for Timed-Arc Petri Nets with Invariants Lasse Jacobsen, Morten Jacobsen and Mikael H. Møller Department of Computer Science, Aalborg University, Selma Lagerlöfs

More information

Timed Automata with Observers under Energy Constraints

Timed Automata with Observers under Energy Constraints Timed Automata with Observers under Energy Constraints Patricia Bouyer-Decitre Uli Fahrenberg Kim G. Larsen Nicolas Markey LSV, CNRS & ENS Cachan, France Aalborg Universitet, Danmark /9 Introduction The

More information

An Efficient Translation of Timed-Arc Petri Nets to Networks of Timed Automata

An Efficient Translation of Timed-Arc Petri Nets to Networks of Timed Automata An Efficient Translation of TimedArc Petri Nets to Networks of Timed Automata Joakim Byg, Kenneth Yrke Jørgensen, and Jiří Srba Department of Computer Science Aalborg University Selma Lagerlöfs Vej 300

More information

Lower-Bound Constrained Runs in Weighted Timed Automata

Lower-Bound Constrained Runs in Weighted Timed Automata Lower-Bound Constrained Runs in Weighted Timed Automata Patricia Bouyer LSV ENS Cachan & CNRS Email: bouyer@lsv.ens-cachan.fr Kim G. Larsen Dept. Computer Science Aalborg. Email:kgl@cs.aau.dk Nicolas Markey

More information

Hourglass Automata. Yuki Osada, Tim French, Mark Reynolds, and Harry Smallbone

Hourglass Automata. Yuki Osada, Tim French, Mark Reynolds, and Harry Smallbone Hourglass Automata Yuki Osada, Tim French, Mark Reynolds, and Harry Smallbone The University of Western Australia. yuki.osada@research.uwa.edu.au, {tim.french,mark.reynolds}@uwa.edu.au, 21306592@student.uwa.edu.au

More information

Safety-Critical Medical Device Development Using the UPP2SF Model

Safety-Critical Medical Device Development Using the UPP2SF Model University of Pennsylvania ScholarlyCommons Departmental Papers (CIS) Department of Computer & Information Science 2014 Safety-Critical Medical Device Development Using the UPP2SF Model Miroslav Pajic

More information

Theoretical Foundations of the UML

Theoretical Foundations of the UML Theoretical Foundations of the UML Lecture 17+18: A Logic for MSCs Joost-Pieter Katoen Lehrstuhl für Informatik 2 Software Modeling and Verification Group moves.rwth-aachen.de/teaching/ws-1718/fuml/ 5.

More information

Decidability Results for Probabilistic Hybrid Automata

Decidability Results for Probabilistic Hybrid Automata Decidability Results for Probabilistic Hybrid Automata Prof. Dr. Erika Ábrahám Informatik 2 - Theory of Hybrid Systems RWTH Aachen SS09 - Probabilistic hybrid automata 1 / 17 Literatur Jeremy Sproston:

More information

Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI

Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI Stavros Tripakis Aalto University and University of California, Berkeley Abstract FMI (Functional Mockup Interface) is a standard

More information

Weak Time Petri Nets strike back!

Weak Time Petri Nets strike back! Weak Time Petri Nets strike back! Pierre-Alain Reynier 1, and Arnaud Sangnier 2, 1 LIF, Université Aix-Marseille & CNRS, France pierre-alain.reynier@lif.univ-mrs.fr 2 Dipartimento di Informatica, Università

More information

Model Checking Linear Duration Invariants of Networks of Automata

Model Checking Linear Duration Invariants of Networks of Automata Model Checking Linear Duration Invariants of Networks of Automata Miaomiao Zhang 1, Zhiming Liu 2, and Naijun Zhan 3 1 School of Software Engineering, Tongji University, Shanghai, China miaomiao@tongji.edu.cn

More information

DISTINGUING NON-DETERMINISTIC TIMED FINITE STATE MACHINES

DISTINGUING NON-DETERMINISTIC TIMED FINITE STATE MACHINES DISTINGUING NON-DETERMINISTIC TIMED FINITE STATE MACHINES Maxim Gromov 1, Khaled El-Fakih 2, Natalia Shabaldina 1, Nina Yevtushenko 1 1 Tomsk State University, 36 Lenin Str.. Tomsk, 634050, Russia gromov@sibmail.com,

More information

DES. 4. Petri Nets. Introduction. Different Classes of Petri Net. Petri net properties. Analysis of Petri net models

DES. 4. Petri Nets. Introduction. Different Classes of Petri Net. Petri net properties. Analysis of Petri net models 4. Petri Nets Introduction Different Classes of Petri Net Petri net properties Analysis of Petri net models 1 Petri Nets C.A Petri, TU Darmstadt, 1962 A mathematical and graphical modeling method. Describe

More information

A Proof System for Timed Automata

A Proof System for Timed Automata A Proof System for Timed Automata Huimin Lin 1 and Wang Yi 2 1 Laboratory for Computer Science Institute of Software, Chinese Academy of Sciences lhm@ox.ios.ac.cn 2 Department of Computer Systems Uppsala

More information

An Algebraic Approach to Energy Problems II The Algebra of Energy Functions

An Algebraic Approach to Energy Problems II The Algebra of Energy Functions Acta Cybernetica 23 (2017) 229 268. An Algebraic Approach to Energy Problems II The Algebra of Energy Functions Zoltán Ésika, Uli Fahrenberg b, Axel Legay c, and Karin Quaas d Abstract Energy and resource

More information

Abstracting real-valued parameters in parameterised boolean equation systems

Abstracting real-valued parameters in parameterised boolean equation systems Department of Mathematics and Computer Science Formal System Analysis Research Group Abstracting real-valued parameters in parameterised boolean equation systems Master Thesis M. Laveaux Supervisor: dr.

More information

Timo Latvala. March 7, 2004

Timo Latvala. March 7, 2004 Reactive Systems: Safety, Liveness, and Fairness Timo Latvala March 7, 2004 Reactive Systems: Safety, Liveness, and Fairness 14-1 Safety Safety properties are a very useful subclass of specifications.

More information

A Unifying Approach to Decide Relations for Timed Automata and their Game Characterization

A Unifying Approach to Decide Relations for Timed Automata and their Game Characterization A Unifying Approach to Decide Relations for Timed Automata and their Game Characterization Shibashis Guha Indian Institute of Technology Delhi Chinmay Narayan Indian Institute of Technology Delhi Shanara

More information

Decidability of Single Rate Hybrid Petri Nets

Decidability of Single Rate Hybrid Petri Nets Decidability of Single Rate Hybrid Petri Nets Carla Seatzu, Angela Di Febbraro, Fabio Balduzzi, Alessandro Giua Dip. di Ing. Elettrica ed Elettronica, Università di Cagliari, Italy email: {giua,seatzu}@diee.unica.it.

More information

A Decidable Class of Planar Linear Hybrid Systems

A Decidable Class of Planar Linear Hybrid Systems A Decidable Class of Planar Linear Hybrid Systems Pavithra Prabhakar, Vladimeros Vladimerou, Mahesh Viswanathan, and Geir E. Dullerud University of Illinois at Urbana-Champaign. Abstract. The paper shows

More information

Automated Verification of a Parametric Real-Time Program: The ABR Conformance Protocol

Automated Verification of a Parametric Real-Time Program: The ABR Conformance Protocol Automated Verification of a Parametric Real-Time Program: The ABR Conformance Protocol Béatrice Bérard and Laurent Fribourg LSV Ecole Normale Supérieure de Cachan & CNRS 61 av. Pdt. Wilson - 94235 Cachan

More information

Monitoring and Fault-Diagnosis with Digital Clocks

Monitoring and Fault-Diagnosis with Digital Clocks Author manuscript, published in "6th Int. Conf. on Application of Concurrency to System Design (ACSD'06) (2006)" Monitoring and Fault-Diagnosis with Digital Clocks Karine Altisen Verimag Laboratory Karine.Altisen@imag.fr

More information

Zone-based Synthesis of Timed Models with Strict Phased Fault Recovery

Zone-based Synthesis of Timed Models with Strict Phased Fault Recovery Zone-based Synthesis of Timed Models with Strict Phased Fault Recovery Fathiyeh Faghih and Borzoo Bonakdarpour School of Computer Science, University of Waterloo, Canada TECHNICAL REPORT CS-2013-05 Abstract.

More information

Zone-Based Reachability Analysis of Dense-Timed Pushdown Automata

Zone-Based Reachability Analysis of Dense-Timed Pushdown Automata IT 12 034 Examensarbete 15 hp Juli 2012 Zone-Based Reachability Analysis of Dense-Timed Pushdown Automata Kristiina Ausmees Institutionen för informationsteknologi Department of Information Technology

More information

Clock Matrix Diagrams

Clock Matrix Diagrams Clock Matrix Diagrams U N I V E R S I T A S S A R A V I E N I S S Bachelor s Thesis Daniel Fass daniel@react.cs.uni-sb.de Reactive Systems Group Department of Computer Science Universität des Saarlandes

More information

Weak Time Petri Nets strike back!

Weak Time Petri Nets strike back! Weak Time Petri Nets strike back! Pierre-Alain Reynier 1, and Arnaud Sangnier 2, 1 LIF, Université Aix-Marseille & CNRS, France pierre-alain.reynier@lif.univ-mrs.fr 2 Dipartimento di Informatica, Università

More information

Timed Petri Nets and Timed Automata: On the Discriminating Power of Zeno Sequences

Timed Petri Nets and Timed Automata: On the Discriminating Power of Zeno Sequences Timed Petri Nets and Timed Automata: On the Discriminating Power of Zeno Sequences Patricia Bouyer 1, Serge Haddad 2, Pierre-Alain Reynier 1 1 LSV, CNRS & ENS Cachan, France 2 LAMSADE, CNRS & Université

More information

arxiv:cs/ v2 [cs.lo] 24 Aug 2006

arxiv:cs/ v2 [cs.lo] 24 Aug 2006 Alternating Timed Automata S lawomir Lasota 1 and Igor Walukiewicz 2 arxiv:cs/0512031v2 [cs.lo] 24 Aug 2006 1 Institute of Informatics, Warsaw University Banacha 2, 02-097 Warszawa 2 LaBRI, Université

More information

Design and Verification of Long Running Transactions in a Timed Framework

Design and Verification of Long Running Transactions in a Timed Framework Design and Verification of Long Running Transactions in a Timed Framework Ruggero Lanotte a, Andrea Maggiolo Schettini b, Paolo Milazzo b, Angelo Troina c, a Dipartimento di Scienze della Cultura, Politiche

More information

Introduction to Temporal Logic. The purpose of temporal logics is to specify properties of dynamic systems. These can be either

Introduction to Temporal Logic. The purpose of temporal logics is to specify properties of dynamic systems. These can be either Introduction to Temporal Logic The purpose of temporal logics is to specify properties of dynamic systems. These can be either Desired properites. Often liveness properties like In every infinite run action

More information

Modeling and Analysis of Hybrid Systems

Modeling and Analysis of Hybrid Systems Modeling and Analysis of Hybrid Systems Algorithmic analysis for linear hybrid systems Prof. Dr. Erika Ábrahám Informatik 2 - Theory of Hybrid Systems RWTH Aachen University SS 2015 Ábrahám - Hybrid Systems

More information

New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations

New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations New Complexity Results for Some Linear Counting Problems Using Minimal Solutions to Linear Diophantine Equations (Extended Abstract) Gaoyan Xie, Cheng Li and Zhe Dang School of Electrical Engineering and

More information

Spiking Neural Networks as Timed Automata

Spiking Neural Networks as Timed Automata Spiking Neural Networks as Timed Automata Giovanni Ciatto 1,2, Elisabetta De Maria 2, and Cinzia Di Giusto 2 1 Università di Bologna, Italy 2 Université Côté d Azur, CNRS, I3S, France Abstract In this

More information

CEGAR:Counterexample-Guided Abstraction Refinement

CEGAR:Counterexample-Guided Abstraction Refinement CEGAR: Counterexample-guided Abstraction Refinement Sayan Mitra ECE/CS 584: Embedded System Verification November 13, 2012 Outline Finite State Systems: Abstraction Refinement CEGAR Validation Refinment

More information

Weak Time Petri Nets strike back!

Weak Time Petri Nets strike back! Weak Time Petri Nets strike back! Pierre-Alain Reynier 1 and Arnaud Sangnier 2, 1 LIF, Université Aix-Marseille & CNRS, France pierre-alain.reynier@lif.univ-mrs.fr 2 Dipartimento di Informatica, Università

More information

Timed Automata: Semantics, Algorithms and Tools

Timed Automata: Semantics, Algorithms and Tools Timed Automata: Semantics, Algorithms and Tools Johan Bengtsson and Wang Yi Uppsala University Email: {johanb,yi}@it.uu.se Abstract. This chapter is to provide a tutorial and pointers to results and related

More information

The State Explosion Problem

The State Explosion Problem The State Explosion Problem Martin Kot August 16, 2003 1 Introduction One from main approaches to checking correctness of a concurrent system are state space methods. They are suitable for automatic analysis

More information

Model Checking Stochastic Automata

Model Checking Stochastic Automata Model Checking Stochastic Automata JEREMY BRYANS University of Stirling and HOWARD BOWMAN and JOHN DERRICK University of Kent at Canterbury Modern distributed systems include a class of applications in

More information

TCTL model-checking of Time Petri Nets

TCTL model-checking of Time Petri Nets 1 TCTL model-checking of Time Petri Nets Hanifa Boucheneb 1, Guillaume Gardey 2,3 and Olivier H. Roux 2 Affiliations : 1 : École polytechnique de Montréal, C.P. 6079, succ. Centre-ville Montréal H3C3A7

More information

Foundations of Informatics: a Bridging Course

Foundations of Informatics: a Bridging Course Foundations of Informatics: a Bridging Course Week 3: Formal Languages and Semantics Thomas Noll Lehrstuhl für Informatik 2 RWTH Aachen University noll@cs.rwth-aachen.de http://www.b-it-center.de/wob/en/view/class211_id948.html

More information

Simulation of Spiking Neural P Systems using Pnet Lab

Simulation of Spiking Neural P Systems using Pnet Lab Simulation of Spiking Neural P Systems using Pnet Lab Venkata Padmavati Metta Bhilai Institute of Technology, Durg vmetta@gmail.com Kamala Krithivasan Indian Institute of Technology, Madras kamala@iitm.ac.in

More information

Automata-theoretic analysis of hybrid systems

Automata-theoretic analysis of hybrid systems Automata-theoretic analysis of hybrid systems Madhavan Mukund SPIC Mathematical Institute 92, G N Chetty Road Chennai 600 017, India Email: madhavan@smi.ernet.in URL: http://www.smi.ernet.in/~madhavan

More information

A Determinizable Class of Timed Automata

A Determinizable Class of Timed Automata A Determinizable Class of Timed Automata Rajeev Alur 1 Limor Fix 2. Thomas A. Henzinger 2.* 1 AT&T Bell Laboratories, Murray Hill, NJ 2 Department of Computer Science, CorneU University, Ithaca, NY Abstract.

More information

Automatic Verification of Real-time Systems with Discrete Probability Distributions

Automatic Verification of Real-time Systems with Discrete Probability Distributions Automatic Verification of Real-time Systems with Discrete Probability Distributions Marta Kwiatkowska a, Gethin Norman a, Roberto Segala b and Jeremy Sproston a a University of Birmingham, Birmingham B15

More information

On decision problems for timed automata

On decision problems for timed automata On decision problems for timed automata Olivier Finkel Equipe de Logique Mathématique, U.F.R. de Mathématiques, Université Paris 7 2 Place Jussieu 75251 Paris cedex 05, France. finkel@logique.jussieu.fr

More information

Probabilistic Model Checking of Deadline Properties in the IEEE 1394 FireWire Root Contention Protocol 1

Probabilistic Model Checking of Deadline Properties in the IEEE 1394 FireWire Root Contention Protocol 1 Under consideration for publication in Formal Aspects of Computing Probabilistic Model Checking of Deadline Properties in the IEEE 1394 FireWire Root Contention Protocol 1 Marta Kwiatkowska a, Gethin Norman

More information

Hybrid Automata. Lecturer: Tiziano Villa 1. Università di Verona

Hybrid Automata. Lecturer: Tiziano Villa 1. Università di Verona Hybrid Automata Lecturer: Tiziano Villa 1 1 Dipartimento d Informatica Università di Verona tiziano.villa@univr.it Thanks to Carla Piazza, Dipartimento di Matematica ed Informatica, Università di Udine

More information

arxiv:cs/ v1 [cs.lo] 8 Dec 2005

arxiv:cs/ v1 [cs.lo] 8 Dec 2005 Alternating Timed Automata S lawomir Lasota 1 and Igor Walukiewicz 2 1 Institute of Informatics, Warsaw University Banacha 2, 02-097 Warszawa arxiv:cs/0512031v1 [cs.lo] 8 Dec 2005 2 LaBRI, Université Bordeaux-1

More information

Specifying Urgency in Timed I/O Automata

Specifying Urgency in Timed I/O Automata Specifying Urgency in Timed I/O Automata Biniam Gebremichael Frits Vaandrager Institute for Computing and Information Sciences Radboud University Nijmegen, The Netherlands {B.Gebremichael,F.Vaandrager}@cs.ru.nl

More information

models based on maximality semantics present concurrent actions differently from choice [11], because of non atomicity of actions. These models advoca

models based on maximality semantics present concurrent actions differently from choice [11], because of non atomicity of actions. These models advoca Maximality-based Region Graph: a Novel Alternative Riadh MATMAT Ilham KITOUNI Souad GUELLATI D-Eddine SAIDOUNI, MISC Laboratory, Constantine 2 University, 25000, Algeria {matmat; kitouni; guellati; saidouni}@misc-umc.org

More information

Analysis of a Boost Converter Circuit Using Linear Hybrid Automata

Analysis of a Boost Converter Circuit Using Linear Hybrid Automata Analysis of a Boost Converter Circuit Using Linear Hybrid Automata Ulrich Kühne LSV ENS de Cachan, 94235 Cachan Cedex, France, kuehne@lsv.ens-cachan.fr 1 Introduction Boost converter circuits are an important

More information

Learning Goals of CS245 Logic and Computation

Learning Goals of CS245 Logic and Computation Learning Goals of CS245 Logic and Computation Alice Gao April 27, 2018 Contents 1 Propositional Logic 2 2 Predicate Logic 4 3 Program Verification 6 4 Undecidability 7 1 1 Propositional Logic Introduction

More information

Serge Haddad Mathieu Sassolas. Verification on Interrupt Timed Automata. Research Report LSV-09-16

Serge Haddad Mathieu Sassolas. Verification on Interrupt Timed Automata. Research Report LSV-09-16 Béatrice Bérard Serge Haddad Mathieu Sassolas Verification on Interrupt Timed Automata Research Report LSV-09-16 July 2009 Verification on Interrupt Timed Automata Béatrice Bérard 1, Serge Haddad 2, Mathieu

More information

Petri Nets (for Planners)

Petri Nets (for Planners) Petri (for Planners) B. Bonet, P. Haslum... from various places... ICAPS 2011 & Motivation Petri (PNs) is formalism for modelling discrete event systems Developed by (and named after) C.A. Petri in 1960s

More information

Comparison of Different Semantics for Time Petri Nets

Comparison of Different Semantics for Time Petri Nets Comparison of Different Semantics for Time Petri Nets B. Bérard 1, F. Cassez 2, S. Haddad 1, Didier Lime 3, O.H. Roux 2 1 LAMSADE, Paris, France E-mail: {beatrice.berard serge.haddad}@lamsade.dauphine.fr

More information

Topics in Timed Automata

Topics in Timed Automata 1/32 Topics in Timed Automata B. Srivathsan RWTH-Aachen Software modeling and Verification group 2/32 Timed Automata A theory of timed automata R. Alur and D. Dill, TCS 94 2/32 Timed Automata Language

More information