Fall ACS Meeting November 4-6, 1997

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1 Optiml Configution of Combined GPP/DSP/FPGA Systems fo Miniml SWAP by John K. Antonio Deptment of Compute Science College of Engineeing Texs Tech Univesity Fll ACS Meeting Novembe

2 Outline Pogm Objectives nd Schedule of Milestones Repesenttive Exmples of Cuent Wo Competing STAP Weight Solves Powe Pediction Model fo FPGAs Optiml Configution fo SAR Pocessing Questions/Answes 2

3 Pogm Objectives Demonstte dvntges of combined use of GPP DSP nd FPGA technologies fo SAR nd STAP pplictions Demonstte dvntges/disdvntges of diffeent FPGA designs nd implementtions in tems of powe consumption nd el-estte equiements Develop nd evlute powe pediction models fo GPP/DSP/FPGA pototype system Development of foml optimiztions fo configuing GPP/DSP/FPGA systems 3

4 Pogm Objectives Incopotion of dt chcteistics nd equiements in optimizing system configution dynmic nge numeicl ccucy Incopotion of multiple GPP/DSP lgoithms FPGA designs nd implementtions nd dt epesenttions in optimizing system configution Time-domin vs. fequency-domin convolutions QR vs. conjugte gdient STAP weight solve Fixed-point vs. bloc floting point vs. floting point 4

5 Schedule of Milestones June 1997 Dec June 1998 Dec June 1999 Dec Optiml GPP/DSP Config. fo SAR Implement SAR on GPP/DSP Optiml GPP/DSP/FPGA Config. fo SAR Optiml GPP/DSP/FPGA Config. fo SAR/STAP Inte-GPP/DSP Comm. Simulto fo STAP Implement STAP on GPP/DSP Design SAR Line Filteing fo FPGA Design STAP Itetive Weight Solve fo FPGA Develop FPGA Powe Consumption Simulto Optiml GPP/DSP Config. fo STAP Implement SAR Line Filteing on FPGA Implement STAP Itetive Weight Solve on FPGA Optiml GPP/DSP/FPGA Config. fo STAP Implement SAR on GPP/DSP/FPGA Pltfom Implement STAP on GPP/DSP/FPGA Pltfom GPP/DSP/FPGA Pltfom Constuction nd Independent Testing of GPP/DSP nd FPGA Subsystems GPP/DSP nd FPGA Subsystem Integtion nd Testing Demonstte Combined SAR/STAP on GPP/DSP/FPGA Pltfom Key GPP/DSP Sub-System Resech/Design Implement/Test FPGA Sub-System Resech/Design Implement/Test GPP/DSP/FPGA System Resech/Design 5 Implement/Test

6 Outline Pogm Objectives nd Schedule of Milestones Repesenttive Exmples of Cuent Wo Competing STAP Weight Solves Powe Pediction Model fo FPGAs Optiml Configution fo SAR Pocessing Questions/Answes 6

7 Refeences fo STAP J. Wd Spce-Time Adptive Pocessing fo Aibone Rd Technicl Repot 1015 MIT Lincoln Lbotoy Lexington MA K. C. Cin J. A. Toes nd R. T. Willims R. A. Gmes Poject Lede RT_STAP: Rel-Time Spce-Time Adptive Pocessing Benchm MITRE Technicl Repot MTR 96B Feb MCARM Dt Files Rome Lbotoy D. G. Luenbege Line nd Nonline Pogmming Addison- Wesley Reding MA

8 Fomultion of STAP Weight Eqution Dt Mtix Needed fo Clculting Weights fo th Dopple Bin nd m th Rnge Segment Using 3 d x : Ode ^ Dopple-Fctoed STAP L 1 3L L Chnnels Dopple m th Rnge Segment with N R cells ψ m 1 N R H x x N R 1 8

9 9 R N R L N L m 3 : ^ STAP Weight Clcultion Using QR Decomposition m m N x x m H R H R N N R ψ s m w m γ ψ The Weight Eqution: s N m w R R s m w R R N w Q R Q R N R T T R T T R γ γ 1 1 * 1 1 * * * QR m T QR-Decomposition :

10 10 Using Conjugte Gdient Appoch to Solve the Weight Eqution CG fo Solving : ψw s Initiliztion T T T T d d d d g g d s w g d d d d g w w Ψ Ψ + Ψ Ψ set Choose d g w s d w Ψ Itetion

11 Peliminy Numeicl Studies Reltive Eo nd FLOP count Vs. Tolence fo N 125 Dt File: e pulses 28 Weight Vectos Computed QR CG Reltive Eo FLOP Count Tolence Tolence 11

12 Peliminy Numeicl Studies Reltive Eo nd FLOP count Vs. Tolence fo N 250 Dt File: e pulses 28 Weight Vectos Computed QR CG Reltive Eo FLOP Count Tolence Tolence 12

13 Implementtion of Conjugte Gdient on FPGAs Esie nd Moe Efficient to Implement on FPGA Hdwe thn QR Decomposition Appoch: Stte Mchine Design ψ Numeicl Opetions Floting point Bloc floting point Fixed point w j w j + 1 No. of vibles No. of bits/vible Dynmic Rnge Accucy Registes 13

14 QR Decomposition: QR Decomposition vesus Conjugte Gdient Suitble fo GPP/DSP implementtion Good pefomnce fo smll vlues of N R Conjugte Gdient: Suitble fo eithe GPP/DSP o FPGA implementtions Good pefomnce fo lge vlues of N R Povides wy to blnce desied pecision nd computtionl effot FPGA implementtions offe mny design pmetes e.g. dt epesenttion no. bits vible etc. 14

15 Conceptul Illusttion of Tde-Offs gphs shown e hypotheticl CG on GPP/DSP QR on GPP/DSP CG on FPGA - Floting Point CG on FPGA - Bloc Floting Point CG on FPGA - Fixed Point Computtionl Complexity Powe Requiements {Pecision Accucy Dyn. Rnge L N } Multidimensionl Pmete Spce {Pecision Accucy Dyn. Rnge L N } Multidimensionl Pmete Spce 15

16 Outline Pogm Objectives nd Schedule of Milestones Repesenttive Exmples of Cuent Wo Competing STAP Weight Solves Powe Pediction Model fo FPGAs Optiml Configution fo SAR Pocessing Questions/Answes 16

17 Refeences fo FPGA Powe Pediction K. P. Pe nd E. J. McClusey Pobbilistic Tetment of Genel Combintoil Netwos IEEE Tns. Computes Vol. C-24 June 1975 pp Kushi Roy nd Sht Psd Cicuit Activity Bsed Logic Synthesis fo Low Powe Relible Opetions IEEE Tns. VLSI Systems Vol. 1 No. 4 Dec.1993 pp. Kushi Roy Powe Dissiption Diven FPGA Plce nd Route unde Timing Constints School of Electicl nd Compute Engineeing Pudue Univesity. C4000 Seies Field Pogmmble Gte Ays ilinx Inc. Septembe

18 FPGA Powe Consumption Inteconnection fbic Logic bloc Most of the logic/e in the FPGA is used to oute signls. As signls tvese this netwo of tnsistos thee cn be significnt powe consumption. 18

19 Powe Dissiption in CMOS Lege Cuent Dynmic Cpcitnce Chging Cuent Most impotnt fo CMOS Dependnt on cloc fequency Dependnt on signl ctivity Tnsient Cuent 19

20 Time-Domin Modeling Vey pecise esults Computtionlly expensive x 1 x 2 x 3 y x 1 t: x 2 t: x 3 t : xx : 1 2 t xx 1 2x3 t: x 1 x 2 y Clcultion of instntneous powe: pt x 3 20

21 Pobbilistic Modeling ps: the pobbility tht signl s ttins logicl vlue of tue t ny given cloc cycle. As: the pobbility tht signl s tnsitions t ny given cloc cycle. p cloc p x p x A cloc 1. 0 A x A x p x A x

22 Pobbilistic Modeling x 1 x 2 x 3 Acceptble esults Computtionlly inexpensive y x 1 t: x 2 t: x 3 t : xx : 1 2 t xx 1 2x3 t: p0.88 A0.10 p0.29 A0.17 p0.69 A0.27 p0.83 A0.17 p0.10 A0.13 x 1 x 2 x 3 y P Clcultion of vege powe: 1 CV vg 2 2 A g g ll gtes 22

23 Pobbilistic Model Implementtion ps 1 As 1 ps 2 As 2 Step 1: Pobbilistic infomtion is distilled fom the input dt nd pesented to the model. Step 2: Pobbilistic dt popgtes thoughout the model depositing ctivity infomtion s it does so. Step 3: Powe is estimted using ctivity mesues nd nown CMOS gte cpcitnces. ps 3 As 3 23

24 Outline Pogm Objectives nd Schedule of Milestones Repesenttive Exmples of Cuent Wo Competing STAP Weight Solves Powe Pediction Model fo FPGAs Optiml Configution fo SAR Pocessing Questions/Answes 24

25 Refeences fo Optiml Configution fo SAR Pocessing J. T. Muehing nd J. K. Antonio Optiml Configution of n Embedded Pllel System fo Synthetic Apetue Rd Pocessing Poc. Int l Conf. on Signl Pocessing Applictions & Technology Boston MA Oct pp T. Einstein Reltime Synthetic Apetue Rd Pocessing on the RACE Multicompute Appliction Note Mecuy Computing Systems Inc. Chelmsfod MA J. C. Culnde nd R. N. McDonough Synthetic Apetue Rd: Systems nd Signl Pocessing John Wiley & Sons New Yo NY SHARC DSP Compute Nodes 3.3-Volt Mecuy Computing Systems Inc. Chelmsfod MA

26 GPP/DSP Appoch fo SAR Pocessing Rnge Pocessing shown coss 3 nge pocessos Azimuth Pocessing shown coss 4 zimuth pocessos K S Pulse No. 1 Distibuted Cone-Tun Rnge Smples 1 K 1 Rnge Smples 1 S Pulse No. whee S is the zimuth section length nd K is the nge efeence enel size 26

27 The Sectioned Convolution fo the Azimuth Pocessing FFT size Kenel Ovelp Discd Section Lge Ovelp/Section tio Smll zimuth memoy lge numbe zimuth pocessos Smll Ovelp/Section tio Lge zimuth memoy smll numbe zimuth pocessos 27

28 Deivtions fo Memoy nd Pocessos fo GPP/DSP Systems P v 6δF + α γr + 10δF lg F s 2 γδ P vr s α + F 6+ 10lg F γs 2 δ M 16Rv 6δF + α γr + 10δF lg F s s 3 γδ M 2 R λr+ 2δ S s 3 δ whee P nd P e the numbe of equied pocessos nd M nd M e the memoy equiements in Mbytes fo nge nd zimuth pocessing espectively 28

29 Detemining Optiml Configutions fo GPP/DSP Systems Detemine configutions fo the CNs numbe of CNs of ech configution nd section size to stisfy pocesso nd memoy equiements nd minimize powe consumption Nottion nd Definitions: CN Configution: Specifies the dughtecd type nd numbe of nge nd zimuth pocessos pe configued CN Y: The two possible CN configutions T Y T : Dughtecd type fo ech CN configution 29

30 Detemining Optiml Configutions fo GPP/DSP Systems Nottion nd Definitions continued: Y : Numbe of nge pocessos pe CN fo ech configution Y : Numbe of zimuth pocessos pe CN fo ech configution N N Y : Numbe of CNs of configutions nd Y Π CN : Powe pe CN s function of dughtecd type M CN : Memoy pe CN s function of dughtecd type P CN : Pocessos pe CN s function of dughtecd type 30

31 Y T CN T CN T CN T CN Y Y T CN Y T CN S Y Y N N K S F Y P Y Y P S P S M Y P M Y Y M S P S M P M M Y N N S P Y N N P Y Π N Π N Z Minimize: Subject to: Optimiztion Fomultion fo GPP/DSP Systems

32 Powe Consumption in Optiml Configution 32

33 % Powe Incese of Nominl Ove Optiml Configution 33

34 Optiml CN Configutions 400 v T Y Y Y T δ 34

35 Detemining Optiml Configutions fo GPP/DSP/FPGA Systems Assume FPGAs e used fo nge pocessing Additionl Nottion nd Definitions: D : Dynmic nge equied fo nge pocessing A : Accucy equied fo nge pocessing I : Incoming dt te depends on δ v R R s T u : Dt type used floting bloc o fixed B u : Numbe of bits used fo dt epesenttion depends on D A T u Cl u : Cloc te used depends on I T u B u 35

36 Detemining Optiml Configutions fo GPP/DSP/FPGA Systems Additionl Nottion nd Definitions continued: G u : Numbe of FPGA chips used fo nge pocessing depends on I T u B u Π G : Powe consumption of FPGAs depends on Cl u T u B u G u Ongoing Wo Deiving pecise eltionships mong bove tems Extending cuent GPP/DSP optimiztion fomultion to include FPGA utiliztion 36

37 Outline Pogm Objectives nd Schedule of Milestones Repesenttive Exmples of Cuent Wo Competing STAP Weight Solves Powe Pediction Model fo FPGAs Optiml Configution fo SAR Pocessing Questions/Answes 37

Discrete Model Parametrization

Discrete Model Parametrization Poceedings of Intentionl cientific Confeence of FME ession 4: Automtion Contol nd Applied Infomtics Ppe 9 Discete Model Pmetition NOKIEVIČ, Pet Doc,Ing,Cc Deptment of Contol ystems nd Instumenttion, Fculty