Some Aspects of Hardware Implementation of LDPC Codes

Transcription

1 Some Aspects of Hardware Implementation of LDPC Codes Emmanuel Boutillon Fréderic Guilloud (PhD, ENST) Jean-Luc Danger (ENST) Laboratoire d électronique des systèmes temps réel Université de Bretagne Sud UPRES EA 3372 emmanuel.boutillon@univ-ubs.fr Outline Definition of LDPC Code Decoding of a Parity Check Construction of a LDPC code Performances Architecture of LDPC decoder Serial decoding of parity check Simulation results Conclusion 2/57 1

2 Parity check Parity check (3,2,1) : b 0 b 1 b 2 bits CP (b 0, b 1, b 2 ) codeword <=> Sum of 1 = 0 mod 2. CP(3,2,1) = {(0, 0, 0) ; (0, 1, 1) ; (1, 1, 0) ; (1, 0, 1)} Generalization: Parity Check (n, n-1, 1) 3/57 Decoding a PC w j N(0,σ) b j {0,1} Mod. x j x j {-A,+A} Démod. y j = x j +w j The observation y j gives the intrinsic information i j of bit b j : i j = (p(b j =0/y j ), p(b j =1/y j )) or in an more convenient representation (log likelihood ratio): i j = ln(p(b j =1/y j )/p(b j =0/y j )) = 2y j /σ 2 Note: sign(i j ) => hard decision, i j reliability of the decision 4/57 2

3 Decoding a parity check code What information i 1 and i 2 gives over the value of b 0? Using? b 1 b 2 bits e 0 i 1 i 2 CP p(b 0 =0/y 1,y 2 ) = p(b 1 =0/y 1 ). p(b 2 =0/y 2 ) + p(b 1 =1/y 1 ). p(b 2 =1/y 2 ) p(b 0 =1/y 1,y 2 ) = p(b 1 =0/y 1 ). p(b 2 =1/y 2 ) + p(b 1 =1/y 1 ). p(b 2 =0/y 2 ) we have and extra independent information e 0 over b 0 given by: i 1 1 i + e e 2 e0 = i1 i2 = ln( ) i1 i e + e 2 e 0 is named the extrinsic information. 5/57 Decoding a parity check code Then i 0 and e 0 are added to obtain the final decoding The process is symmetrical for all bits y 0 y 1 y 2 1,4 2,2 2,9 Codeword i j b 0 b 1 b 2 b 0 b 1 b 2 i j e j /57 3

4 Note: iteration If the process is re-iterate, there is auto-confirmation -0,3 1 1,9-0,3 1 1,9 T j -1,1 1,2 2 b 0 b 1 b 2 b 0 b 1 b 2 I j -0,3 1 1,9 E j -0,8 0,2 0,1 and the system diverge... 7/57 LDPC Code It can be defined by a bi-partite graph Bit b i Branches Parity checks (PC) (b 0, b 1,, b 6 ) is a codeword <=> all PC are respected. 8/57 4

5 Why LDPC? Algebraic representation: X = (x 0, x 1,, x 6 ) T is a codeword if H.X = 0 H = N=number of bits P=number of PC Check Matrix Number of 1 over a row = dc=number of bit associated to the PC Number of 1 over a line = dv=number of PC associated to the bit Less than 1% of the bits of H are equal to 1 9/57 How to construct a good LDPC Code Select first the size and the rate of the code Select an optimal spectrum repartition of the branch example: 90 % bits => dv =3 branches, 10 % bits dv=> 12 branches 70 % PC => dc = 6 branches, 30 % PC => dc = 8 branches than chose the code randomly just avoiding short cycle like: b i bj and you have a good code 10/57 5

6 BP (or sum-product) decoding algorithm Step1: compute the LLR of received bit Step2: Message passing from bit to check + check processing. Step3: Message passing from check to bit + bit processing. Step4: repeat 2 and 3 until decoding OK or "max iteration" obtained. 11/57 Processing in bit node y n y n Bit Node i n b n t Bit Node i n b n t e 0 e 1 e 2 e 3 a 0 = t-e 0 a1 a 2 a 3 t + = i n e m m ai = in + ei m, m i = t ai 12/57 6

7 Processing in check nodes : principles b 0 b 1 b 2 b 3 b 4 a 0 a 1 a 2 a 3 a 4 b 0 b 1 b 2 b 3 b 4 e 0 e 1 e 2 e 3 e 4 Check Node Check Node e a i = ai = a1 a2 ai ai+ j i 1 dc No simplifications... 13/57 Processing in check node: realization a 0 a 1 a 2 a 3 a 4 e 0 e 1 e 2 e 3 e 4 Generic slice G.D. Forney «on iterative decoding and the two-way algorithm» Symp. On Turbo- Codes, Brest 1997 Side slice Complexity: 3.(dc - 2) operator "XOR" a b c 14/57 7

8 let s 1+ e e c = a b = ln( a b e + e Realization of "XOR" = ˆ ˆ a sign( a), sb = sign( b), a = a, b = a b ) = s x With F( x) ln(1 e ) â bˆ a. s b = + 1/16 + _ aˆ + bˆ aˆ bˆ ( min( aˆ, bˆ) F( aˆ bˆ) + F( aˆ + bˆ) ). LUT LUT1 x LUT2 b log(1+e ) 5/16 x 4/16 3/16 2/16 1/2 1 3/2 2 5/2 x min( aˆ, bˆ) c = a b 15/57 Iterative decoding y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 10 y 11 y 12 y 13 y n decoding iterations 16/57 8

9 Iterative decoding y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 10 y 11 y 12 y 13 y n decoding iterations 17/57 Iterative decoding y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 10 y 11 y 12 y 13 y n decoding iterations 18/57 9

10 BER Performances (rate 1/2) n=10 3 n=10 6 n=10 3 n=10 5 n=10 4 n=10 4 n=10 5 n=10 6 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 SNR Best known code for n > /57 Outline Definition of LDPC Code Architecture of LDPC decoder Full parallel decoder Decoder first code design Serial decoding of parity check Simulation results Conclusion 20/57 10

11 (3)Architecture :introduction Full parallel architecture Example Blanksby, Howland, «A 690-mW 1-Gb/s 1024-b Rate-1/2 Low- Density Parity-Check Code Decoder» (IEEE Trans. on Solid-State Circuits, 2002.) Avantages performance: 1Gb/s 64 iterations Power dissipation : 690mW PER=2 2,5 db Drawback Complex routing =>add oc CAD tool Fixed code Size : 52.5mm 2, 0.16µ Techno Direct implementation 21/57 Serial-parallel architecture Main problem: access to the memory Example: if Fclock = Fbit, then, at each clock cycle the number A of read/write memory access is given by: Where A d (1 ) b dc is the average degree of PC r is the rate of the code nb iter is the number of iteration Example: dc=6, r=1/2 and nb iter = 50 give A = 150 Solutions: a) Duplicate the memory b) Split the memory in small blocks for parallel decoding 22/57 11

12 (3)Architecture :introduction Method «Decoder first code design» Method proposed in Boutillon et al. «Decoder-First Code Design», Int. Symp. on Turbo Codes, Brest, The architecture is first defined P Parity Check are done every cycle. N=P.dc K=0..M-1 Memory is divided in N=P*dc sub_memory of size L. L dc MEM 0 RAG0... MEM... i RAGi Shuffle Network MEM N-1 RAGn-1 RPG Code of size NL with MP parity check. Decoding iteration: M cycles. Retrieve bit from memory at the address given by the Random Address Generator (RAG). Shuffle the data(random Permutation Generator). Perform the PC process. Unshuffle the extrinsic information serial on fly process of bit nodes. PC 0 PC 1 PC P-1 No performance degradations... 23/57 Shuffle Network: from node to PC N=dc.P bit messages form the N memories i=1..m π0 or Id.. π1 or Id.. π2 or Id.. To P parallel Parity Check processors. S 0,k S 1,k S 2,k Random Permutation Generator 24/57 12

13 Shuffle Network: from PC to node Store the N=dc.P checks messages in the N memories i=1..m π0 or Id.. π1 or Id.. π2 or Id.. S 0,k S 1,k S 2,k Random Permutation Generator From P parallel Parity Check processors. 25/57 Example: k=1 L= N=P.dc=2.3= k=0 N.L=12 bits RPG k=0 PC 0 PC 1 26/57 13

14 Example: k=1 L= N=P.dc=2.3= k=1 N.L=12 bits RPG k=0 k=1 PC 0 PC 1 27/57 Example: k=2 L= N=P.dc=2.3= k=1 N.L=12 bits RPG k=0 k=1 k=2 PC 0 PC 1 One decoding iteration performed every M=3 cycles. 28/57 14

15 Memory: serial computation of bit node extrinsic Memory bank sum of extrinsic Intrinsic previous current L i d d d e0 + e1 + e2 e0 d +1 + e 1 d +1 d e 1 e1 d +1 M t - RAG k d d a 1 = t e 1 e1 d +1 Shuffle network 29/57 Reported work on LDPC design Parrallele architecture No constraint on the code (Blanksby, Howland) Constraint on the code (Sobelman) Parrallele-serial architecture No constraint on the code (Lee, Wu) Constraint on the code (Verdier, Tong Zhang, Parhi) "Joint code and decoder design for implementation-oriented (3, k)-regular LDPC codes", Tong Zhang; Parhi, K.K, Asilomar Industry Flavion technology Hugues Network System Proposition for DVB-S2. 30/57 15

16 Outline Definition of LDPC Code Architecture of LDPC decoder Serial decoding of parity check simplification of PC equations architecture of PC processor Reduction of extrinsic memory Simulation results Conclusion 31/57 Actual scheduling D ecoding ofa codew ord N bits nb iter Iterations SERIE P.M Parity C hecks PC ofdc bits P SERIE-// solution PARALLEL 32/57 16

17 Proposed new scheduling D ecoding ofa codew ord N bits nb iter Iterations SERIE P.M Parity C hecks PC ofdc bits single PC Check P.dc SERIAL-// solution SERIAL SERIAL (dc clock cycle) Objective: sub_optimal algorithm with reduced complexity 33/57 Serial architecture N=P.dc K=0..M-1 MEM MEM i MEM N-1 RAG0 RAGi RAGn-1 Shuffle Network RPG P' > P PC in parallel PC 0 PC j PC P' each perform in dc cycles 34/57 17

18 Serial Processing of check node dc cycles From memory to check Sequential Processing PCa. From memory dc' cycles From memory to check Sequential Processing PCb. From check to memory dc cycles To memory From check to... PC a PC a Irregular LDPC are well managed 35/57 Assuming ai = si. aˆ i e i = a = s S j i j, j i j, j i λ-min algorithm the expression of the e i can be expressed by: aˆ j Where S = Term dominated by the smallest values Idea: computed it only with the λ smallest values of => λ-min algorithm e i α aˆ I = { ind 0,..., ind λ 1 } j I, j i j aˆ ind0... aˆ i indλ 1 s i aˆ k â j k I 36/57 18

19 Example λ=2-min algorithm 0 1 a = e = e else e else e else 3 2 a j e i ind0 = 3 ind1 = 4 e3 = j e4 = j { 3,4} / { 3,4} / a j = a4 = 3 j 3 a j = a3 = 2 j 4 eelse = a j = a3 a4 j { 3,4} Note: Fossorier proposed independantly e j = min a j i / j i + correction factor 37/57 Example λ=3-min algorithm a = e = e else e 1 e else e 3 e λ= a j ind0 = 3 ind1 = 4 ind2 = 1 e i = a j j / j i e else = a3 a4 a1 e1 = a3 a4 e3 = a4 a1 38/57 19

20 Serial sorting : 1) synthesis (ind i-1,min i-1 ) (k, a k ) (k, a k, s k ) s k + R min i a k C 0 1 glue FIFO 2 dc s k k= 1.. dc (ind i, min i ) (min, ind) S After the serial arrival of the dc bit message the λ mins are known. 39/57 Serial sorting : Example for dc=5, λ=3 (k, a k ) (0, 25) (1, 31) (2, 27) (3, 45) (4, 11) (-, 255) (0, 25) (0, 25) (0, 25) (0, 25) (4, 11) (-, 255) (-, 255) (1, 31) (2, 27) (2, 27) (0, 25) (-, 255) (-, 255) (-, 255) (1, 31) (1, 31) (2, 27) k=0 k=1 k=2 k=3 k=4 result After the serial arrival of the dc bit message the λ min are known. 40/57 20

21 "On the fly" parity check scheme Case of λ = 3 k=1..dc ind 2 ind 1 compare ind 0 t 2 t 1 t 0 min 2 + min 1 + min 0 + t 2 t 1 t 0 FIFO s k k= 1.. dc S s k t i =1 if (k=ind i ), 0 otherwise e k 41/57 Note: XOR function is simplified min j + min i _ min j - min i min j + min i mult by 2 LUT1 LUT2 PC operator can be simplified using min j >min i 42/57 21

22 min 2 min 1 min 0 a b 0 1 Precomputed PC: Computing cycle 1 cycle 2 cycle 3 cycle 4 (a,b)=(0,0) (a,b)=(0,1) (a,b)=(1,1) (a,b)=(1,2) min1 min 2 min0 min 2 min0 min 1 min0 min1 min2 min1 min 2 min0 min 2 min0 min 1 min1 min 2 min0 min 2 min1 min 2 43/57 Precomputed PC scheme: extrinsic generation ind 2 k=1..dc t 2 min0 min1 min2 i i i i o t 2 t 1 FIFO s k k= 1.. dc ind 1 compare t 1 i i t 0 ind 0 t 0 o s k t i =1 if (k=ind i ), 0 otherwise e k o = 1 if t 1 =t 2 =t 3 =0 IDEA : Instead of storing extrinsic, store just the information needed to re-generate it 44/57 22

23 Storage of extrinsic information Classical method: each PC needs the storage of dc extrinsic values => dc.(1+n b ) bit of memory Proposed method: store the information needed to recompute extrinsic values instead of storing extrinsic values Information to be stored: λ+1 min values λ indice values dc signs Product of sign Number of bits (λ+1).n b λ log 2 (dc) dc bits 1 bits The compression ratio is: 1+ dc + λlog2( dc) + ( λ + 1) Nb dc.(1 + Nb) 45/57 reduction factor Result λ=2 λ=3 λ= dc Trade-off "memory save" <-> "Computation" 46/57 23

24 Outline Definition of LDPC Code Architecture of LDPC decoder Serial decoding of parity check Simulation results Rate 1/2 MDPC Conclusion 47/57 Some result 48/57 24

25 Offset β : extrinsic = max( 0, e - β) 49/57 50/57 25

26 Performances of high rate Turbo-Code 1 Bit Error Rate e-05 1e-06 1e-07 1e-08 1e-09 1e-10 BER TC FER TC 1000 errors in average Few errors /57 Eb/N0 Use an external code to suppress the flatening Bit Error Rate e-05 1e-06 1e-07 1e-08 1e-09 1e-10 BER TC FER TC Rate losses (10log(R)) /57 Effect of external code Eb/N0 26

27 Construction of MDPC External code : - LDPC with few hundred of bit per parity (=> Medium DPC) - very high coding rate (arround 0,98). At the output of the Turbo-Code, most of the bit can be assumed correctly decoded. => they can be supressed of the MDPC code After suppression of reliable bit of the MDPC code: => the code becomes LDPC => the coding rate is low The decoding starts to be efficient 53/57 Construction of the Parity Check Matrix N length of the code P number of parity check dc i is the degre of the parity check P P i dv i is the degre of the bit b i F(b i ) is the set of PC connected to b i G(P i ) is the set of bit connected to PC P i N Parity check matrix H dc 1 value on the row Constraint on the code to obtain a regular MDPC: dv i = constant for all i i j Card(G(P i) G(Pj)) Max with Max as minimum as possible 54/57 27

28 Results (regular MDPC) G Code MDPC P = 320, 350 et 400 dc = 300 λ=2 min algorithm 10 iterations T=1 T=2 T=2 Code RS GF(256) -2.5 T=3 T=3 T=7-3 T= Log10(R) 0 0, Compared to RS code, the proposed scheme is more efficient 55/57 Influence of parameter dc P = decoding iterations. Gain iterations dc There is an optimal value of dc 56/57 28

29 Conclusion With the choice of LDPC as a standard for DVB-S2, VLSI architecture for LDPC becomes a real challenge. Proposition of λ-min algorithm to reduce the complexity Very efficient method in case of high rate LDPC Use Fossorier's method to reduce the sub-optimality of the code (offset and/or constant factor on extrinsic values). Ondoing implementation of the λ-min algorithm on FPGA Nallatec system, virtex1000e, 50 MHz P=8 up to 16 parallelism degree code size up to 2K. 57/57 29