74HC4094-Q100; 74HCT4094-Q100

Size: px
Start display at page:

Download "74HC4094-Q100; 74HCT4094-Q100"

Transcription

1 74HC4094-Q100; 74HCT4094-Q100 Rev November 2018 Product data sheet 1. General description 2. Features and benefits 3. Applications The is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input () and two serial outputs (QS1 and QS2) to enable cascading. ata is shifted on the LOW-to-HIGH transitions of the CP input. ata is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. ata in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V CC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Complies with JEEC standard JES7A Input levels: For 74HC4094-Q100: CMOS level For 74HCT4094-Q100: TTL level Low-power dissipation ES protection: MIL-ST-883, method 3015 exceeds 2000 V HBM JES22-A114F exceeds 2000 V MM JES22-A115-A exceeds 200 V (C = 200 pf; R = 0 Ω) Serial-to-parallel data conversion Remote control holding register

2 4. Ordering information Table 1. Ordering information Type number Package 74HC4094-Q100 74HCT4094-Q100 74HC4094B-Q100 74HCT4094B-Q100 Temperature range Name escription Version -40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm -40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm 74HC4094PW-Q C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT109-1 SOT338-1 SOT Functional diagram 3 1 CP STR 1 15 C2 EN3 QS1 QS2 QP0 QP SRG8 3 2 C1/ QP2 QP3 QP4 QP5 QP OE QP aaf aaf112 Fig. 1. Logic symbol Fig. 2. IEC Logic symbol 2 3 CP 8-STAGE SHIFT REGISTER QS2 QS STR 8-BIT STORAGE REGISTER 15 OE 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP aaf119 Fig. 3. Functional diagram Product data sheet Rev November / 19

3 STAGE 0 STAGES 1 TO 6 STAGE 7 Q Q Q QS1 CP CP CP FF 0 CP FF 7 LE Q QS2 LATCH Q Q LE LE LATCH 0 LATCH 7 STR OE QP0 QP2 QP4 QP6 QP1 QP3 QP5 QP7 001aag799 Fig. 4. Logic diagram 6. Pinning information 6.1. Pinning 74HC HCT4094 STR 1 16 V CC 74HC HCT4094 CP OE QP4 STR V CC OE QP0 QP QP5 QP6 CP QP0 QP QP4 QP5 QP6 QP2 QP QP7 QS2 QP2 QP3 GN QP7 QS2 QS1 GN 8 9 QS1 001aan578 Fig aan577 Pin configuration SOT109-1 (SO16) Fig. 6. Pin configuration SOT338-1 (SSOP16) and SOT403-1 (TSSOP16) Product data sheet Rev November / 19

4 6.2. Pin description Table 2. Pin description Symbol Pin escription STR 1 strobe input 2 data input CP 3 clock input QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output GN 8 ground supply voltage QS1, QS2 9, 10 serial output OE 15 output enable input V CC 16 supply voltage 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don t care; Z = HIGH-impedance OFF-state; NC = no change; = positive-going transition; = negative-going transition; Q6S = the data in register stage 6 before the LOW to HIGH clock transition; Q7S = the data in register stage 7 before the HIGH to LOW clock transition. Inputs Parallel outputs Serial outputs CP OE STR QP0 QPn QS1 QS2 L X X Z Z Q6S NC L X X Z Z NC Q7S H L X NC NC Q6S NC H H L L QPn -1 Q6S NC H H H H QPn -1 Q6S NC H H H NC NC NC Q7S CLOCK INPUT ATA INPUT STROBE INPUT OUTPUT ENABLE INPUT INTERNAL Q0S (FF 0) OUTPUT QP0 INTERNAL Q6S (FF 6) OUTPUT QP6 Z-state Z-state SERIAL OUTPUT QS1 Fig. 7. SERIAL OUTPUT QS2 001aaf117 At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs. Timing diagram Product data sheet Rev November / 19

5 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < -0.5 V or V I > V CC V - ±20 ma I OK output clamping current V O < -0.5 V or V O > V CC V - ±20 ma I O output current V O = -0.5 V to (V CC V) - ±25 ma I CC supply current ma I GN ground current ma T stg storage temperature C P tot total power dissipation SO16, SSOP16 and TSSOP16 packages [1] mw [1] For SO16: P tot derates linearly with 8 mw/k above 70 C. For SSOP16 and TSSOP16 packages: P tot derates linearly with 5.5 mw/k above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GN (ground = 0 V) Symbol Parameter Conditions 74HC4094-Q100 74HCT4094-Q100 Min Typ Max Min Typ Max V CC supply voltage V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature C Δt/ΔV input transition rise and fall rate Unit V CC = 2.0 V ns/v V CC = 4.5 V ns/v V CC = 6.0 V ns/v Product data sheet Rev November / 19

6 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter 74HC4094-Q100 V IH V IL V OH V OL I I I OZ HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current OFF-state output current Conditions 25 C -40 C to +85 C -40 C to +125 C Min Typ Max Min Max Min Max V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V I = V IH or V IL I O = -20 μa; V CC = 2.0 V V I O = -20 μa; V CC = 4.5 V V I O = -20 μa; V CC = 6.0 V V I O = -4.0 ma; V CC = 4.5 V V I O = -5.2 ma; V CC = 6.0 V V V I = V IH or V IL I O = 20 μa; V CC = 2.0 V V I O = 20 μa; V CC = 4.5 V V I O = 20 μa; V CC = 6.0 V V I O = 4.0 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V V I = V CC or GN; V CC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 μa V I = V IH or V IL ; V O = V CC or GN; V CC = 6.0 V I CC supply current V I = V CC or GN; I O = 0 A; V CC = 6.0 V C I input capacitance - - ±0.5 - ±5.0 - ±10.0 μa μa pf Unit Product data sheet Rev November / 19

7 Symbol Parameter 74HCT4094-Q100 V IH V IL V OH V OL I I I OZ HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current OFF-state output current Conditions 25 C -40 C to +85 C -40 C to +125 C Min Typ Max Min Max Min Max V CC = 4.5 V to 5.5 V V V CC = 4.5 V to 5.5 V V V I = V IH or V IL ; V CC = 4.5 V I O = -20 μa V I O = -4.0 ma V V I = V IH or V IL ; V CC = 4.5 V I O = 20 μa V I O = 4.0 ma V V I = V CC or GN; V CC = 5.5 V - - ±0.1 - ±1.0 - ±1.0 μa V I = V IH or V IL ; V O = V CC or GN; V CC = 5.5 V I CC supply current V I = V CC or GN; I O = 0 A; V CC = 5.5 V ΔI CC C I additional supply current input capacitance V I = V CC V; other inputs at V CC or GN; V CC = 4.5 V to 5.5 V; I O = 0 A - - ±0.5 - ±5.0 - ±10 μa μa per input pin; STR input μa per input pin; OE input μa per input pin; CP input μa per input pin; input μa pf Unit Product data sheet Rev November / 19

8 11. ynamic characteristics Table 7. ynamic characteristics Voltages are referenced to GN (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Fig. 12. Symbol Parameter 74HC4094-Q100 t pd t en t dis t t propagation delay enable time disable time transition time Conditions CP to QS1; see Fig. 8 [1] 25 C -40 C to +85 C -40 C to +125 C Min Typ Max Min Max Min Max V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns V CC = 6.0 V ns CP to QS2; see Fig. 8 [1] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns V CC = 6.0 V ns CP to QPn; see Fig. 8 [1] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns V CC = 6.0 V ns STR to QPn; see Fig. 9 [1] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns V CC = 6.0 V ns OE to QPn; see Fig. 10 [1] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns OE to QPn; see Fig. 10 [1] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns QPn and QSn; see Fig. 8 [1] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Unit Product data sheet Rev November / 19

9 Symbol Parameter t W t su t h f max C P pulse width set-up time hold time maximum frequency power dissipation capacitance Conditions CP HIGH or LOW; see Fig C -40 C to +85 C -40 C to +125 C Min Typ Max Min Max Min Max V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns STR HIGH; see Fig. 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns to CP; see Fig. 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns CP to STR; see Fig. 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns to CP; see Fig. 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns CP to STR; see Fig. 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns CP; see Fig. 8 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 5 V; C L = 15 pf MHz V CC = 6.0 V MHz C L = 50 pf; f = 1 MHz; [2] pf V I = GN to V CC Unit Product data sheet Rev November / 19

10 Symbol Parameter 74HCT4094-Q100 t pd t en t dis t t t W t su t h f max C P propagation delay enable time disable time transition time pulse width set-up time hold time maximum frequency power dissipation capacitance Conditions CP to QS1; see Fig. 8 [1] 25 C -40 C to +85 C -40 C to +125 C Min Typ Max Min Max Min Max V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns CP to QS2; see Fig. 8 [1] V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns CP to QPn; see Fig. 8 [1] V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns STR to QPn; see Fig. 9 [1] V CC = 4.5 V ns V CC = 5 V; C L = 15 pf ns OE to QPn; see Fig. 10 [1] V CC = 4.5 V ns OE to QPn; see Fig. 10 [1] V CC = 4.5 V ns QPn and QSn; see Fig. 8 [1] V CC = 4.5 V ns CP HIGH or LOW; see Fig. 8 V CC = 4.5 V ns STR HIGH; see Fig. 9 V CC = 4.5 V ns n to CP; see Fig. 11 V CC = 4.5 V ns CP to STR; see Fig. 9 V CC = 4.5 V ns n to CP; see Fig. 11 V CC = 4.5 V ns CP to STR; see Fig. 9 V CC = 4.5 V ns CP; see Fig. 8 V CC = 4.5 V MHz V CC = 5 V; C L = 15 pf MHz C L = 50 pf; f = 1 MHz; V I = GN to V CC V [2] pf Unit [1] t pd is the same as t PLH and t PHL ; t en is the same as t PZH and t PZL ; t dis is the same as t PLZ and t PHZ ; t t is the same as t THL and t TLH. [2] C P is used to determine the dynamic power dissipation (P in μw). P = C P x V CC 2 x fi x N + (C L x V CC 2 x fo ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L x V CC 2 x fo ) = sum of outputs. Product data sheet Rev November / 19

11 11.1. Waveforms and test circuits V I 1/f max CP input GN t W t PLH t PHL QPn, QS1 output V OH V OL 90 % 10 % QS2 output V OH t TLH t PLH t THL t PHL Fig. 8. V OL Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. aaa Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse width and the maximum frequency (CP) V I CP input GN t su t h V I STR input GN t W t PLH t PHL V OH QPn output Fig. 9. V OL Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. 001aaf114 Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock set-up and hold times for strobe input Product data sheet Rev November / 19

12 V I OE input GN t PLZ t PZL V CC output LOW-to-OFF OFF-to-LOW V OL V X t PHZ t PZH V OH output HIGH-to-OFF OFF-to-HIGH GN outputs enabled V Y outputs disabled Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Fig. 10. Enable and disable times outputs enabled 001aaf116 V I CP input GN t su t su V I t h th input GN V OH QPn, QS1, QS2 output V OL Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. 001aaf115 Fig. 11. The data input () to clock input (CP) set-up times and clock input (CP) to data input () hold times Table 8. Measurement points Type Input Output V X V Y 74HC4094-Q V CC 0.5V CC 0.1V OH 0.9V OH 74HCT4094-Q V 1.3 V 0.1V OH 0.9V OH Product data sheet Rev November / 19

13 t W V I negative pulse 0 V 90 % 10 % t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC G VI UT VO RL S1 open RT CL 001aad983 Test data is given in Table 9. efinitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S1 = Test selection switch. Fig. 12. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC4094-Q100 V CC 6 ns 15 pf, 50 pf 1 kω open GN V CC 74HCT4094-Q100 3 V 6 ns 15 pf, 50 pf 1 kω open GN V CC Product data sheet Rev November / 19

14 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 E A X c y H E v M A Z 16 9 Q pin 1 index A 2 A 1 (A ) 3 θ A L p 1 8 L e b p w M detail X mm scale IMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note A max A 1 A 2 A 3 b p c (1) E (1) e H (1) E L L p Q v w y Z Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION SOT109-1 REFERENCES IEC JEEC JEITA 076E07 MS-012 EUROPEAN PROJECTION ISSUE ATE Fig. 13. Package outline SOT109-1 (SO16) Product data sheet Rev November / 19

15 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 E A X c y H E v M A Z 16 9 Q A 2 A 1 (A ) 3 A pin 1 index 1 8 L detail X L p θ e b p w M mm scale IMENSIONS (mm are the original dimensions) A UNIT A 1 A 2 A 3 b p c (1) E (1) e H E L L p Q v w y Z (1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEEC JEITA MO-150 EUROPEAN PROJECTION ISSUE ATE Fig. 14. Package outline SOT338-1 (SSOP16) Product data sheet Rev November / 19

16 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E A X c y H E v M A Z 16 9 pin 1 index A 2 A 1 Q (A ) 3 A θ 1 8 e b p w M L detail X L p mm scale IMENSIONS (mm are the original dimensions) A UNIT A 1 A 2 A 3 b p c (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEEC JEITA MO-153 EUROPEAN PROJECTION ISSUE ATE Fig. 15. Package outline SOT403-1 (TSSOP16) Product data sheet Rev November / 19

17 13. Abbreviations Table 10. Abbreviations Acronym escription CMOS UT ES HBM MM TTL Complementary Metal Oxide Semiconductor evice Under Test ElectroStatic ischarge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history ocument I Release date ata sheet status Change notice Supersedes 74HC_HCT4094_Q100 v Product data sheet - 74HC_HCT4094_Q100 v.1 Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Fig. 4 and Fig. 7 corrected. 74HC_HCT4094_Q100 v Product data sheet - - Product data sheet Rev November / 19

18 15. Legal information ata sheet status ocument status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet Product status [3] evelopment Qualification Production efinition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "efinitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at efinitions raft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. isclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations A non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Product data sheet Rev November / 19

19 Contents 1. General description Features and benefits Applications Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics ynamic characteristics Waveforms and test circuits Package outline Abbreviations Revision history Legal information...18 Nexperia B.V All rights reserved For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com ate of release: 14 November 2018 Product data sheet Rev November / 19

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

The 74LV08 provides a quad 2-input AND function.

The 74LV08 provides a quad 2-input AND function. Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.

More information

74HC153-Q100; 74HCT153-Q100

74HC153-Q100; 74HCT153-Q100 Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each

More information

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers. Rev. 1 2 November 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The provides two buffers. 2. Features and benefits 3. Ordering information Wide supply voltage

More information

74HC151-Q100; 74HCT151-Q100

74HC151-Q100; 74HCT151-Q100 Rev. 2 11 February 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0

More information

74AHC373; 74AHCT373. Octal D-type transparant latch; 3-state

74AHC373; 74AHCT373. Octal D-type transparant latch; 3-state Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance

More information

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting Rev. 5 2 February 2016 Product data sheet 1. General description The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs

More information

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop. Rev. 2 12 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH

More information

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting Rev. 3 9 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable

More information

74HC541; 74HCT541. Octal buffer/line driver; 3-state

74HC541; 74HCT541. Octal buffer/line driver; 3-state Rev. 4 3 March 2016 Product data sheet 1. General description 2. Features and benefits The is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables (OE1

More information

74LVC1G125-Q100. Bus buffer/line driver; 3-state

74LVC1G125-Q100. Bus buffer/line driver; 3-state Rev. 2 8 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

74HC107-Q100; 74HCT107-Q100

74HC107-Q100; 74HCT107-Q100 Rev. 2 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,

More information

74HC30-Q100; 74HCT30-Q100

74HC30-Q100; 74HCT30-Q100 Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

74HC365; 74HCT365. Hex buffer/line driver; 3-state

74HC365; 74HCT365. Hex buffer/line driver; 3-state Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits The is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn

More information

7-stage binary ripple counter

7-stage binary ripple counter Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).

More information

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state Rev. 6 1 February 2016 Product data sheet 1. General description The is a dual 4-bit multiplexer, each with four binary inputs (ni0 to ni3), an output enable input (noe) and shared select inputs (S0 and

More information

Octal buffer/line driver; 3-state

Octal buffer/line driver; 3-state Rev. 4 1 March 2016 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC244 and 74HCT244. The is an octal non-inverting buffer/line

More information

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate Rev. 3 5 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current

More information

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger Rev. 4 12 May 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and

More information

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW

More information

74HC597-Q100; 74HCT597-Q100

74HC597-Q100; 74HCT597-Q100 Rev. 1 26 May 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit

More information

74HC280; 74HCT bit odd/even parity generator/checker

74HC280; 74HCT bit odd/even parity generator/checker Rev. 3 15 September 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a 9-bit parity generator or checker. Both even and odd parity outputs are available.

More information

74HC126; 74HCT126. Quad buffer/line driver; 3-state

74HC126; 74HCT126. Quad buffer/line driver; 3-state Rev. 3 22 September 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad buffer/line driver with 3-state outputs controlled by the output enable

More information

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop. Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH

More information

Bus buffer/line driver; 3-state

Bus buffer/line driver; 3-state Rev. 12 2 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).

More information

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device. 74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function

More information

74HC132-Q100; 74HCT132-Q100

74HC132-Q100; 74HCT132-Q100 Rev. 3 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state Rev. 2 16 March 2015 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

More information

The 74AXP1G04 is a single inverting buffer.

The 74AXP1G04 is a single inverting buffer. Rev. 1 25 August 2014 Product data sheet 1. General description The is a single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This

More information

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. Rev. 3 16 August 2013 Product data sheet 1. General description The is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

More information

4-bit magnitude comparator

4-bit magnitude comparator Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than

More information

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

74ALVCH V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Rev. 5 9 July 2012 Product data sheet 1. General description The is 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.

More information

74HC109-Q100; 74HCT109-Q100

74HC109-Q100; 74HCT109-Q100 Rev. 1 28 September 2016 Product data sheet 1. General description The is a dual positive edge triggered JK flip-flop featuring individual nj and nk inputs. It has clock (ncp) inputs, set (nsd) and reset

More information

74HC373-Q100; 74HCT373-Q100

74HC373-Q100; 74HCT373-Q100 Rev. 1 10 August 2012 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard

More information

74AHC573; 74AHCT573. Octal D-type transparant latch; 3-state

74AHC573; 74AHCT573. Octal D-type transparant latch; 3-state Rev. 7 8 November 20 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEEC standard

More information

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state Rev. 6 10 July 2012 Product data sheet 1. General description The is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates

More information

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state. The 74HC574; 74HCT574 is functionally identical to:

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state. The 74HC574; 74HCT574 is functionally identical to: Rev. 5 25 pril 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL.

More information

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer Rev. 5 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each

More information

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description The is a 1-of-2 non-inverting demultiplexer with a 3-state output. The

More information

The 74AUP2G34 provides two low-power, low-voltage buffers.

The 74AUP2G34 provides two low-power, low-voltage buffers. Rev. 6 17 September 2015 Product data sheet 1. General description The provides two low-power, low-voltage buffers. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise

More information

74HC2G08-Q100; 74HCT2G08-Q100

74HC2G08-Q100; 74HCT2G08-Q100 Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in

More information

Single dual-supply translating 2-input OR with strobe

Single dual-supply translating 2-input OR with strobe Rev. 1 10 October 2018 Product data sheet 1. General description The is a single dual-supply translating 2-input OR with strobe inputs. It features two data input pins (A, B), two strobe input pins (STRA,

More information

74HC2G125; 74HCT2G125

74HC2G125; 74HCT2G125 Rev. 5 17 March 2014 Product data sheet 1. General description 2. Features and benefits The 74HC2G125; 74HC2G125 are dual buffer/line drivers with 3-state outputs controlled by the output enable inputs

More information

74LV03. 1 General description. 2 Features and benefits. 3 Ordering information. Quad 2-input NAND gate

74LV03. 1 General description. 2 Features and benefits. 3 Ordering information. Quad 2-input NAND gate Rev. 4 31 August 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number Package The is a low-voltage Si-gate CMOS device

More information

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer Rev. 1 23 April 2018 Product data sheet 1 General description 2 Features and benefits The is a suitable for use in clock distribution. It has a data input (A), four data outputs (Yn) and an output enable

More information

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops

More information

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance

More information

74HC03-Q100; 74HCT03-Q100

74HC03-Q100; 74HCT03-Q100 Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable

More information

8-stage shift-and-store register

8-stage shift-and-store register Rev. 13 14 November 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information ll types operate from -40 C to +125 C. Type number The

More information

Low-power configurable multiple function gate

Low-power configurable multiple function gate Rev. 2 16 September 2015 Product data sheet 1. General description The is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions

More information

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state

74ALVCH V/3.3 V 16-bit D-type transparent latch; 3-state Rev. 5 17 November 2011 Product data sheet 1. General description The is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications.

More information

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate Rev. 5 14 March 2018 Product data sheet 1 General description 2 Features 3 Ordering information Table 1. Ordering information Type number 74HC1G08GW 74HCT1G08GW 74HC1G08GV 74HCT1G08GV The is a single.

More information

74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger

74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output

More information

Low-power configurable multiple function gate

Low-power configurable multiple function gate Rev. 8 23 September 2015 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the

More information

8-bit parallel-in/serial-out shift register

8-bit parallel-in/serial-out shift register Rev. 7 9 March 2016 Product data sheet 1. General description The is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When

More information

2-input EXCLUSIVE-OR gate

2-input EXCLUSIVE-OR gate Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output

More information

Octal bus transceiver; 3-state

Octal bus transceiver; 3-state Rev. 2 3 November 2016 Product data sheet 1. General description The is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE) and send/receive (DIR) for direction control.

More information

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter. Rev. 1 22 August 2012 Product data sheet 1. General description The is a single buffer and single inverter. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

More information

74HC1G125; 74HCT1G125

74HC1G125; 74HCT1G125 Rev. 6 6 September 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number 74HC1G125GW 74HCT1G125GW 74HC1G125GV 74HCT1G125GV

More information

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use

More information

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86. Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.

More information

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02. Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC

More information

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1. Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance

More information

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger Rev. 4 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,

More information

74HC573-Q100; 74HCT573-Q100

74HC573-Q100; 74HCT573-Q100 Rev. 3 5 March 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEEC

More information

Low-power dual Schmitt trigger inverter

Low-power dual Schmitt trigger inverter Rev. 1 9 October 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. It transforms slowly changing input signals into sharply defined, jitter-free output

More information

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate 8-input NND gate Rev. 6 27 December 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-input NND gate. Inputs include clamp diodes. This enables

More information

74AVC4T774PW. 4-bit dual supply translating transceiver; 3-state

74AVC4T774PW. 4-bit dual supply translating transceiver; 3-state Rev. 1 25 September 2017 Product data sheet 1 General description 2 Features and benefits The is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output

More information

74HC General description. 2 Features and benefits. 3 Ordering information. 8-bit magnitude comparator

74HC General description. 2 Features and benefits. 3 Ordering information. 8-bit magnitude comparator Rev. 3 4 July 2018 Product data sheet 1 General description 2 Features and benefits The is an. It performs comparisons of two 8-bit binary or BCD words. Inputs include clamp diodes. This enables the use

More information

The 74LV08 provides a quad 2-input AND function.

The 74LV08 provides a quad 2-input AND function. Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0

More information

Single supply translating buffer/line driver; 3-state

Single supply translating buffer/line driver; 3-state Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating buffer/line driver with 3-state output. The low threshold inputs

More information

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder Rev. 06 25 November 2009 Product data sheet 1. General description 2. Features 3. Applications The is a 4-bit, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer.

More information

74HC164; 74HCT bit serial-in, parallel-out shift register

74HC164; 74HCT bit serial-in, parallel-out shift register Rev. 8 19 November 2015 Product data sheet 1. General description The is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs

More information

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter Rev. 5 26 November 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package 74HC3G04DP 74HCT3G04DP 74HC3G04DC 74HCT3G04DC

More information

Octal D-type transparent latch; 3-state

Octal D-type transparent latch; 3-state Rev. 02 18 October 2007 Product data sheet 1. General description 2. Features The is an octal -type transparent latch featuring separate -type inputs for each latch and 3-state true outputs for bus-oriented

More information

74HC1G32-Q100; 74HCT1G32-Q100

74HC1G32-Q100; 74HCT1G32-Q100 Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input

More information

74HC1G02-Q100; 74HCT1G02-Q100

74HC1G02-Q100; 74HCT1G02-Q100 Rev. 1 7 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G02-Q100 and 74HCT1G02-Q100 are high speed Si-gate CMOS devices. They provide a 2-input

More information

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 14 15 December 2016 Product data sheet 1. General description The is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE

More information

74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting

74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting Rev. 3 21 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit inverting buffer/line driver with 3-state outputs. The device features

More information

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer. Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

More information

Low-power triple buffer with open-drain output

Low-power triple buffer with open-drain output Rev. 2 5 October 2016 Product data sheet 1. General description The is a triple non-inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain

More information

Dual supply buffer/line driver; 3-state

Dual supply buffer/line driver; 3-state Rev. 1 21 December 2015 Product data sheet 1. General description The is a dual supply non-inverting buffer/line driver with 3-state output. It features one input (A), an output (Y), an output enable input

More information

74HC4514; 74HCT to-16 line decoder/demultiplexer with input latches

74HC4514; 74HCT to-16 line decoder/demultiplexer with input latches Rev. 3 0 February 0 Product data sheet General description Features and benefits 3 pplications The is a 4-to-6 line decoder/demultiplexer having four binary weighted address inputs (0 to 3), with latches,

More information

2-input single supply translating NAND gate

2-input single supply translating NAND gate Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating 2-input NND gate. The low threshold inputs support 1.8 V input

More information

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output

More information

4-bit dual-supply buffer/level translator; 3-state

4-bit dual-supply buffer/level translator; 3-state Rev. 1 18 December 017 Product data sheet 1 General description Features and benefits The is a -bit, dual-supply level translating buffer with -state outputs. It features four data inputs (An and B), four

More information

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function. Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They

More information

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function. Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin

More information

74AHC273-Q100; 74AHCT273-Q100

74AHC273-Q100; 74AHCT273-Q100 74HC273-100; 74HCT273-100 Rev. 1 27 March 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified

More information

Dual buffer/line driver; 3-state

Dual buffer/line driver; 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output

More information

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Dual 2-input NOR gate

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Dual 2-input NOR gate Rev. 6 26 July 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package 74HC2G02DP 74HCT2G02DP 74HC2G02DC 74HCT2G02DC

More information

74HC166-Q100; 74HCT166-Q100

74HC166-Q100; 74HCT166-Q100 Rev. 1 25 September 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit serial or parallel-in/serial-out shift register. The device features

More information

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current

More information

74AVC1T General description. 2 Features and benefits. 1-to-4 fan-out buffer

74AVC1T General description. 2 Features and benefits. 1-to-4 fan-out buffer Rev. 1 3 April 1 Product data sheet 1 General description Features and benefits The is a translating suitable for use in clock distribution. It has dual supplies (V CC(A) and V CC(B) ) for voltage translation.

More information

74HC32-Q100; 74HCT32-Q100

74HC32-Q100; 74HCT32-Q100 Rev. 1 1 ugust 2012 Product data sheet 1. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages

More information

HEF4024B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. 7-stage binary counter

HEF4024B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. 7-stage binary counter Rev. 7 18 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master

More information

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer

More information