12 - The Tie Set Method

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Bruno Doyle
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1 12 - The Tie Set Method Definitions: A tie set V is a set of components whose success results in system success, i.e. the presence of all components in any tie set connects the input to the output in the logic diagram. A minimal tie set T is a tie set where the set remaining after a removal of any of its elements is no longer a tie set. This means that all components of a minimal tie set must be succeed to cause system success. Example: Find the tie sets of Fig.8 below. Fig.8 Solution : The tie sets are : (B1,B4), (B2,B5), (B1, B3,B4), (B2,B3,B5) T1 T2 T3 T4 A visual description of defining the above minimum tie sets is shown in Fig.9. 1

2 Fig.9 2

3 We can develop a logical model for our system as: T1 I/P T2 O/P T3 T4 Equivalent Tie Set Logic Diagram Now all tie set blocks can be modelled logically as a series combination of their constituent components, so we can expand the logic diagram as: B1 B4 I/P B2 B5 O/P B1 B3 B5 B2 B3 B4 Final Equivalent Tie Set Logic Diagram 3

4 Numerical Example 2 : Consider the same 4-bus system shown in Fig.7 in the previous example1. Use the tie set method to determine the reliability, unreliability and the expected outage time in hours per year of the system. Assume that the reliability of the generator R G =0.92 and the reliability of each line R L1 =R L2 =R L3 R L4 =R L5 = Solution 4

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6 Fault Tree Analysis (FTA) Fault Tree Analysis uses tree structures to provide a systematic way to view logical sequences that can lead to failure of complex system. Boolean gates shown in the following table are used to model the failure interactions. Table -1 Fault tree gate and event symbols Intermediate event AND gate Basic event OR gate Undeveloped event Inhibit gate Transfer event Conditional event Exclusive OR gate Used with inhibit gate A Fault Tree Analysis identifies and ranks combinations of events represented on a Fault Tree that cause system failure, and provides estimates of the system's failure probability. The Qualitative analysis of the Fault Tree determines the: a) probability of system failure (top event) based on a single failure (basic event) cause or common cause potential using minimal cut sets, b) combination of 6

7 component failures (minimal cut sets), c) importance ranking of contributors to system failure. The primary event symbols are typically used as follows: Basic event - failure or error in a system component or element (example: switch stuck in open position) Intermediate event an event resulting from combination of two or more basic events Undeveloped event - an event about which insufficient information is available, or which is of no consequence Conditioning event - conditions that restrict or affect logic gates (example: mode of operation in effect) The gates work as follows: OR gate - the output occurs if any input occurs AND gate - the output occurs only if all inputs occur (inputs are independent) Exclusive OR gate - the output occurs if exactly one input occurs Priority AND gate - the output occurs if the inputs occur in a specific sequence specified by a conditioning event Inhibit gate - the output occurs if the input occurs under an enabling condition specified by a conditioning event Transfer symbols are used to connect the inputs and outputs of related fault trees, such as the fault tree of a subsystem to its system. Transfer in Transfer out Characteristics of fault tree: 1. It is a top-down analysis, where the top event is specified first. 2. Does not necessarily contain all possible failure mod of the components of the system.only those failure modes which contribute to the existence occurrence of the top event are modelled. 7

8 3. A fault tree is an expression for Boolean logic.i.e., all basic events are binary, that is, either true or false. Example1: Draw the fault tree analysis for the circuit shown below, in which the DC motor does not run when switch (S) is pressed. Fig1 Solution: The fault tree is shown in Fig.2 below Fig.2 8

9 Example 2 : Determine the probability event A in the fault tree of Fig.3 below if all the basic events are statically independent and mutually exclusive of one another. The probabilities of the basic event are estimated as follows: P(D)= 0.05 P(H) = 0.12 P(L) = 0.05 P(F) = 0.15 P(I) = 0.10 P(G) = 0.20 P(K) = 0.05 A B C D E J Fig.3 K 9

10 Solution P (J) = P (K) P (L) P (K). P (L) P (E) = P (I) P (J) = P (I) + P (J) = = P(B)= P(D) P(E) P(F) = P(D) + P(E)+ P(F)= = P(C) = P (G) P (H) = P(G). P (H) = (0.20) (0.12) = P(A)= P(B) P(C) = P(B). P(C) = (0.3025) (0.0240) Example 3: Consider the power system shown in Fig. 4. The generator at station A represents power inflow that can be considered as perfectly reliable for purpose of this example. Define system failure to be: Station B is isolated or Station C is isolator or The combined load of station B and C are carried by single circuit. Draw a fault tree for this system. Fig.4 10

11 Solution: The top event is System failure. Based on the given definition, we may immediately draw the first level of a tree as follows: First level Now one proceeds by analysing each of three ways that system fail: 1. For event E1 to occur it requires three events: a. loss of circuit 1 (basic event ) b. loss of circuit 2 (basic event ) c. loss of supply from station C ( intermediate event) Because of this failure mode requires all of these events to occur, we flow them through AND gate. 2. Occurance of event of the event E2 requires two events a. loss of circuit 3 (basic event ) b. loss of supply from substation B (intermediate event ) Because this failure mode requires both of these two events to occur, we flow them through an AND gate. 3. Occurrence of the event E3 in three different ways: a. supply from circuit 1 only ( intermediate event ) b. supply from circuit 2 only (intermediate event ) or 11

12 c. supply from circuit 3 only (intermediate) Because this failure mode occurs if any of these three events occur, we flow them through OR gate. In this way we can proceed to draw the second level, third level and finally the full tree will be as shown in fig.5. Fig.5 Fault tree for example 3. 12

Chapter 18 Section 8.5 Fault Trees Analysis (FTA) Don t get caught out on a limb of your fault tree.

Chapter 18 Section 8.5 Fault Trees Analysis (FTA) Don t get caught out on a limb of your fault tree. C. Ebeling, Intro to Reliability & Maintainability Engineering, 2 nd ed. Waveland Press, Inc. Copyright