DETERMINING AN APPROPRIATE NUMBER OF FOUPS IN SEMICONDUCTOR WAFER FABRICATION FACILITIES. Jens Zimmermann Scott J. Mason John W.

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1 Prceedings f the 2008 Winter Simulatin Cnference S. J. Masn, R. R. Hill, L. Mönch, O. Rse, T. Jeffersn, J. W. Fwler eds. DETERMINING AN APPROPRIATE NUMBER OF FOUPS IN SEMICONDUCTOR WAFER FABRICATION FACILITIES Jens Zimmermann Sctt J. Masn Jhn W. Fwler Lars Mönch Chair f Enterprise-wide Sftware Systems Department f Industrial Department f Industrial Dept. f Mathematics and Cmputer Science Engineering Engineering University f Hagen University f Arkansas Arizna State University Hagen, GERMANY Fayetteville, AR, 72701, USA Tempe, AZ, 85287, USA ABSTRACT In this paper, multiple rders per jb type frmatin and release strategies are described fr semicnductr wafer fabricatin facilities (wafer fabs). Different rders are gruped int ne jb because rders f an individual custmer very ften fill nly a prtin f a Frnt-Opening Unified Pd (FOUP). A FOUP is assigned t each jb and is used t mve the jb thrughut the wafer fab after the jb frmatin. We determine an apprpriate number f FOUPs fr a given rder release rate that will yield acceptable values fr n-time delivery perfrmance, cycle time, and thrughput via discrete event simulatin. 1 INTRODUCTION In semicnductr manufacturing, integrated circuits (IC) are prduced n silicn wafers. This type f manufacturing is very capital intensive. The prcess cnditins are very cmplex (cf. Gupta et al. 2006). We have t deal with parallel machines (als referred t as tls), different types f prcesses (batch prcesses and single wafer prcesses), sequence-dependent setup times, prescribed custmer due dates fr the jbs, and re-entrant prcess flws. It is cmmn fr a fab t prduce a large number f different prducts and the prduct mix may change ften. This is especially in wafer fabs that specialize in applicatin specific circuits (ASIC fundries). In mst semicnductr cmpanies wafers travel thrugh 300-mm wafer fabs in FOUPs cntaining a maximum f 25 wafers. Due t the increase in wafer size, a FOUP full f 300-mm wafers can weigh in excess f 40 punds. Therefre, full factry autmatin given by Autmated Material Handling Systems (AMHS) is required as peratrs will be unable t physically carry FOUPs safely. In additin t ecnmic cncerns, the ptential revenue t be earned frm the larger 300-mm wafers frces cmpanies t restrict manual transfer f prductin wafers, whether by hand r by cart. These technlgical challenges make the already challenging planning and scheduling prblems even mre cmplex. The cmbinatin f decreased line widths and mre area per wafer result in fewer wafers being needed t fill IC rders f sme custmers. Each wafer fab will have nly a limited number f FOUPs as they are expensive. A large number f FOUPs have the ptential t cause verlad in the AMHS. In additin, sme tls have the same prcessing times regardless f the number f wafers in the batch. Therefre, it is generally nt reasnable t assign an individual FOUP t each rder. Therefre, 300-mm manufacturers ften have the need and the incentive t grup rders frm different custmers int ne r mre FOUPS t frm prductin jbs. These jbs have t be scheduled n the varius types f tl grups in the wafer fab and prcessed tgether. This class f integrated jb frmatin and scheduling prblems are called multiple rders per jb scheduling prblems. T date, multiple rders per jb scheduling prblems have nly been cnsidered fr single, parallel, and flwshp machine envirnments in the literature (cf., fr example, Qu and Masn 2005). The interdependency between multiple rders per jb frmatin prblems and the number f FOUPs has apparently nt been cnsidered in the literature s far. In rder t investigate this dependency we use discrete event simulatin as an apprpriate technique t deal with the stchastic and dynamic nature f a full wafer fab prblem. The paper is rganized as fllws. In the next sectin, we describe the researched prblem in sme detail. Then we cntinue with a literature review in Sectin 3. We present the suggested slutin methdlgy in Sectin 4. The used framewrk fr FOUP simulatins is presented in Sec /08/$ IEEE 2164

2 Zimmermann, Mönch, Masn, and Fwler tin 5. The results f the perfrmed simulatin study are analyzed and discussed in Sectin 6. 2 PROBLEM DESCRIPTION We describe the prblem in Sectin 2.1. Then we discuss related literature. Finally, we analyze the prblem. 2.1 Prblem Statement Custmers f a semicnductr manufacturer place their rders fr specific prduct types at different pints in time by phne, fax, , r the Internet. We dente the set f all existing rders by O : = { 1,,n}. Each rder has the fllwing attributes assciated with it: s : the size f rder measured in number f wafers that are necessary t fulfill the required number f IC s accunting fr prductin yield, d : the due date f rder, r : the release time f rder, w : the weight f rder that is a measure fr the custmer imprtance. The capacity f a FOUP is dented by K and is measured in wafers. The attribute s can vary widely acrss different types f wafer fabs. In a high vlume, lw mix cmmdity type wafer fab, s will be usually greater than K. In high mix ASIC r fundry type wafer fabs, usually s < K hlds. Therefre, rders with the same z will be aggregated t better use the capacity f the FOUP. This leads t better FOUP utilizatin and reduces the number f FOUPs needed. Thrughut the rest f the paper, we dente the number f FOUPs by n f. The fllwing assumptins are made within this research. Only rders with the same prcess flw can be used t frm a jb. This means that we knw the rute f the FOUP after a jb is assigned t the FOUP. When a jb is frmed then this decisin cannt be changed, i.e., a split r merge f jbs is nt allwed. Different types f prcesses are used within the wafer fabs f interest. The prcessing times f mst nn-batching tls depend n the number f wafers within the jb. Batching tls are run in a FOUP based manner, i.e., the maximum batch size is measured in number f FOUPs. Only jbs with the same prcess flw can be batched tgether. FOUPs nly pick up rders that are waiting fr prcessing. Therefre, infrmatin n future rder arrivals will nt be taken int accunt. This has the cnsequence that in sme situatins the number f wafers that will be transferred via ne FOUP is small. A jb will be frmed nly in tw different situatins. The jb assciated with a FOUP is cmpleted and the FOUP is newly available. When rders are in the rder pl, then a new jb will be frmed. When the rder pl is empty and a FOUP is available, then jbs will be frmed whenever a new rder is released int the rder pl. Nte that the first situatin will be mre imprtant because usually the number f FOUPs is limited. The space fr the strage f FOUPs waiting in stckers and mini-stckers is large enugh. Therefre, blcking f the tls because f missing stcker space is nt pssible. A large number f FOUPs leads t cngestin f the AMHS. We simply intrduce additinal transprtatin time t mdel this cngestin instead f mdeling the AMHS in detail. The prblem studied in this paper is t determine an apprpriate number f FOUPs given a certain rder release rate such that we can maintain a certain thrughput (TP), have a small cycle time (CT), and a small ttal weighted tardiness (TWT). The measure TWT is given by the summatin f the tardiness f all cmpleted rders multiplied with their weight w. Besides determining the number f FOUPs we have t lk fr strategies t frm the jbs. We expect that jb frmatin will have an impact n CT and TWT, especially in situatins, when the number f FOUPs is small. 2.2 Prblem Analysis Fr a fixed number f FOUPs, the wafer fab can be cnsidered apprximately as a CONWIP system. Therefre, the prblem t find an apprpriate number f FOUPs is similar t determine an apprpriate wrk in prcess (WIP) level in a CONWIP system. Fr simple CONWIP manufacturing systems, CT and TP can be determined simultaneusly in a recursive manner by mean value analysis using Little s law (Hpp and Spearman 2000). The thrughput f the CONWIP system can be cnsidered apprximately as its release rate. Based n this release rate we are able t determine the waiting time f the rders in the rder pl by using queuing thery. When the rder release rate in the rder pl is larger than the release rate int the CONWIP system, then the number f rders in the rder pl will increase ver time. We expect that the cycle time f the rders in the rder pl will be large when the number f FOUPs is small. At the same time, we expect that the number f wafers within ne FOUP will increase when the number f FOUPs is small. The impact f jb frmatin rules will be imprtant in the case f a full rder pl. We expect that a large number f FOUPs leads t a smaller number f wafers within a FOUP. At the same time, the cycle time will increase with an increasing num- 2165

3 Zimmermann, Mönch, Masn, and Fwler ber f FOUPs because f CONWIP system prperties and because f AMHS cngestin. 2.3 Related Literature Because f ur findings frm the prblem analysis sectin, we have t discuss literature with respect t jb frmatin strategies in multiple rders per jb scheduling prblems. Multiple rders per jb scheduling prblems are cnsidered by Qu and Masn (2005), Laub et al. (2007), and Erramilli, and Masn (2006). Several decmpsitin appraches are suggested fr single, parallel, and flwshp machine envirnments that address the jb frmatin, jb assignment, and jb sequencing prblem independently. Hwever, jb frmatin and release strategies are nt cnsidered n the entire wafer fab level s far. A survey related t rder release strategies in semicnductr manufacturing is presented by Fwler et al. (2002). This survey cntains especially a discussin f CONWIP appraches in semicnductr manufacturing. Framinan et al. (1999) als discuss varius appraches t analyze CONWIP systems in different industries. It turns ut that very ften simulatin based appraches are apprpriate. This apprach is als used by Gillard (2002) fr analyzing the CONWIP strategy in ne f Intel s wafer fabs. Therefre, we will use discrete-event simulatin t determine an apprpriate number f FOUPs. is based n the AutSched AP custmizatin suggested by Mönch (2005). FOUPS will be represented by lts in AutSched AP. Each FOUP bject cntains pinters t its rder bjects. The verall prcedure can be described as fllws: 1. Generate rders within the blackbard. 2. Create FOUPS whenever rders are created and the maximum number f FOUPS is nt reached r when a FOUP gets available. Chse the cntent f a FOUP based n heuristics, set the pinters t the rder bjects. 3. Launch and prcess a lt in AutSched AP that represents the FOUP frm Step Destry FOUPS at the end f the simulatin and cllect FOUP and rder related statistics. The described framewrk is shwn in Figure 1. Order Generatr Blackbard Order Pl 3 SIMULATION BASED METHODOLOGY In this sectin, we present a simulatin framewrk that can be used t determine an apprpriate number f FOUPs and assess the perfrmance f different jb frmatin heuristics. Furthermre, we als present the used jb frmatin heuristics. 3.1 Simulatin Framewrk We use the simulatin engine AutSched AP because mst f prcess specifics f the semicnductr industry can be mdeled in an apprpriate way. Because there is n clear separatin made between rders and lts in AutSched AP, we extend the simulatin framewrk suggested by Mönch et al. (2003) t the case f rders and FOUPS. The main idea f the framewrk is a blackbard-type data mdel that is between the simulatin engine and prductin cntrl appraches. The blackbard acts as a mirrr f the business bjects fund in the simulatin mdel like machines, prducts, and lts (as mving entities). In rder t avid a time cnsuming custmizatin f AutSched AP, we intrduce rders nly within the blackbard. Because we have a fixed number f FOUPs, the treatment f FOUPs is similar t lt handling in CONWIP appraches fr wafer fabs. Therefre, ur implementatin AutSched AP AutSched AP Lts Figure 1: Simulatin Framewrk 3.2 Slutin Apprach Given a certain rder release rate λ we cnsider a wafer fab with a fixed number f FOUPs n f and a given heuristic h fr frming the jbs. We measure the values f the perfrmance measures thrughput (TP), cycle time (CT), and ttal weighted tardiness (TWT). A First in First Out (FIFO) type heuristic first srts the rders with respect t increasing ready times r f the rders. Then the maximum number f rders is taken frm the beginning f this list t frm jb J such that s K J is valid. We call this heuristic FIFO-H in the remainder f this paper. The next heuristic cnsiders simultaneusly the weight, the due date, and the release date f each rder. The pririty index f rder is given by: 2166

4 Zimmermann, Mönch, Masn, and Fwler w r IWDD, () t : = 2. (1) d t The rders are srted with respect t a decreasing index I WDD,. The mtivatin fr the secnd term in the prduct is as fllws. In case f rders that stay fr a lng time in the rder pl, r is small. Hence, the index I WDD, is large. A maximum number f rders are taken frm the beginning f this list t frm jb J such that s K is J valid. This heuristic is called the Weighted Due Date heuristic (WDD-H). The fllwing heuristic is similar t WDD-H. We use the fllwing index t assess rder : w r IWSS, () t : = 2. (2) s t Nte that we simply replace d frm expressin (1) by s in expressin (2). This heuristic is called the Weighted Shrtest Size heuristic and we use the abbreviatin WSS- H. 4 COMPUTATIONAL EXPERIMENTS In this sectin, we present the cmputatinal results f ur simulatin experiments. We describe ur design f experiments in Sectin 4.1. Then, the cmputatinal results are presented and discussed. 4.1 Design f Experiments We use a mdificatin f the MiniFab simulatin mdel develped by El Adl et al. (1996) with 24 tls rganized in nine tl grups fr the experiments. The mdel cntains three prducts. We simulate 15 mnths with the first three mnths used fr warm up. Expnentially distributed tl breakdwns are cnsidered. We take five independent replicatins fr each simulatin run t btain stchastically significant results. An rder is created n average every 38 minutes. The quantity s is distributed with 50 percent prbability accrding t U[2,8] and with 50 percent prbability accrding t U[3,11]. We use a fixed weight scheme fr the rders. The discrete distributin D 1 describes a situatin where many lts have small r medium weight. D 1 is given by the expressin wj = 1 D1 : = wj = 5 with wj = 10 p p p = 0.5, = 0.35, = The due dates f the rders are calculated using the flw factr cncept. The flw factr FF is defined as the rati f the cycle time and the raw prcess time. We calculate due dates f rder by the expressin: u : = k + k = 1 d RN FF p r, (4) where we dente the prcessing time f prcessing step k by p k. The quantity u dentes the number f prcessing steps f rder. RN is distributed accrding t U[0.5, 1.1]. We use a flw factr FF = The transprtatin time f the FOUPs is mdeled as a specific additinal lad and unlad time. This ffset depends n the number f FOUPs within the system and the riginal lad and unlad times. We carry ut simulatins with a fixed maximum number f FOUPs n f = 10,20,, 110 fr each jb frmatin rule. The tls within the wafer fab are cntrlled with the FIFO dispatching rule. 4.2 Cmputatinal Results In Figure 2, we present the results f ur experiments fr the average weighted tardiness (AWT). The AWT values are btained by simply dividing the crrespnding TWT value by the number f cmpleted rders. AWT in h 14, , , , , , , Average Weighted Tardiness (3) # FOUPs Figure 2: AWT Values FIFO-H WDD-H WSS-H We use the perfrmance measure AWT instead f TWT because AWT als takes the number f cmpleted rders int accunt. Therefre, AWT is a mre fair measure fr cmparisn in situatins where the thrughput is different fr the jb frmatin heuristics. 2167

5 Zimmermann, Mönch, Masn, and Fwler It turns ut that we btain the smallest values fr AWT in case f 50 and 60 FOUPs fr all jb frmatin rules. We bserve an increase in the AWT value when mre than 70 FOUPs are used because f the additinal transprtatin time. A large number f FOUPs leads t a cngested transprtatin system. The transprtatin times increase and the FOUPs wait a lng time fr transprtatin. This causes tls t nt be able t prcess wafers because n rders are available at the tls. This leads als t higher cycle times as shwn in Figure 3. CT in h 7, , , , , , , Cycle Time # FOUPs Figure 3: CT Values FIFO-H WDD-H WSS-H Figure 3 shws that the cycle time increases when mre than 70 FOUPs are used. A higher cycle time leads t a lwer thrughput. The results fr the thrughput are presented in Figure 4. TP in Wafers 14,000 12,000 10,000 8,000 6,000 4,000 2,000 0 Thrughput # FOUPs Figure 4: TP Values FIFO-H WDD-H WSS-H We see that the thrughput decreases when mre than 70 FOUPs are used. The thrughput increases up t apprximately 50 FOUPs. The number f FOUPs is large enugh t prduce all rders in an adequate time. The WSS-H rule leads t small AWT values in the cases f few and many FOUPs, a small cycle time and a high thrughput in cmparisn with the ther rules. In case f 40 and 50 FOUPs, the WSS-H rule leads t slightly wrse results fr AWT. FIFO-H and WDD-H prvide better results. The results f the WDD-H rule are better r equal t the FIFO-H rule. All tested rules prvide essentially the same results fr AWT, cycle time, and thrughput in the case f 60 FOUPs. In Table 1, we analyze the FOUP utilizatin measured in rders, the average waiting time f the rders in the rder pl, and the cycle time f the FOUPs. The cycle time f the FOUPs is similar fr all assessed rules. Table 1: FOUP Utilizatin, Waiting Time, and Cycle Time FOUP utilizatin in rders FOUPs FIFO WDD WSS FOUPs FIFO WDD WSS Average waiting time in rder pl in hur FOUPs FIFO WDD WSS FOUPs FIFO WDD WSS FOUP cycle time in hurs FOUPs FOUPs The utilizatin f the FOUPs decreases up t a number f 60 FOUPs. Then, the utilizatin increases. This is understandable because the cycle time increases and mre rders are in the manufacturing system. The average waiting time fllws the same trend. We see frm Table 1 that the FOUP cycle time increases almst linearly with the number f FOUPs. The utilizatin and the waiting time in the rder pl are nearly the same fr the FIFO-H and WDD-H rule. The utilizatin fr the WSS-H rule is higher and the waiting time is lwer in the cases f few and many FOUPs. This rule selects rders with a small number f wafers. Hence, mre rders are cmpleted. We identify an ptimal number f FOUPs fr the applied wafer fab mdel and a fixed rder release rate. This number is 60 FOUPs because we get a small average 2168

6 Zimmermann, Mönch, Masn, and Fwler weighted tardiness, a small cycle time, and a high thrughput. 5 CONCLUSIONS AND FUTURE RESEARCH In this paper, we described a simulatin study t find an apprpriate number f FOUPs in wafer fabs where multiple rders are used t frm a jb. We presented a simulatin envirnment that can be used t mdel the multiple rder per jb decisins. The simulatin study clearly shws that there is a apprpriate number f FOUPS given a certain rder release rate such that the values f perfrmance measures like TWT, CT, r thrughput are within a certain range. There are sme directins fr future research. It seems pssible t relax sme f the assumptins described in Sectin 2.1. Fr example, it seems a gd strategy t wait fr future rder arrivals t increase the number f wafers within a FOUP. Furthermre, simulatin studies with mre realistic simulatin mdels, especially with respect t number f tls and number f prducts, need t be perfrmed. It seems likely that including the AMHS in the simulatin study will be beneficial. ACKNOWLEDGEMENT The authrs gratefully acknwledge the simulatin effrts f Marc Rsari Scpelliti. REFERENCES Angrawal, G. K., and S. S. Heragu A Survey n autmated material handling systems in 300-mm semicnductr fabs. IEEE Transactins n Semicnductr Manufacturing, 19(1): El Adl, M.K., A. A. Rdriguez, and K. S. Tsakalis Hierarchical mdeling and cntrl f re-entrant semicnductr manufacturing facilities. In Prceedings f the 35th Cnference n Decisin and Cntrl, Kbe, Japan. Erramilli, V., and S. J. Masn Multiple rders per jb cmpatible batch scheduling. IEEE Transactins n Electrnics Packaging Manufacturing 29(4): Fwler, J.W., G. L. Hgg, and S. J. Masn Wrklad cntrl in the semicnductr industry. Prductin Planning & Cntrl 13(7): Framinan, J. M., P. L. Gnzalez, and R. Ruiz-Usan The CONWIP prductin cntrl system: review and research issues. Prductin Planning & Cntrl 14(3): Gillard, W. G A simulatin study cmparing perfrmance f CONWIP and bttleneck-based release rules. Prductin Planning & Cntrl, 13(2): Gupta, J.N.D., R. Ruiz, J. W. Fwler, and S. J. Masn Operatinal planning and cntrl f semicnductr wafer prductin. Prductin Planning & Cntrl, 17(7): Hpp, W. J., and M. L. Spearman Factry physics, 2 nd ed. Bstn: McGraw-Hill. Laub, J. D., J. W. Fwler, and A. B. Keha Minimizing makespan with multiple-rders-per-jb in a twmachine flwshp. Eurpean Jurnal f Operatinal Research 182(1): Mönch, L., O. Rse, and R. Sturm Simulatin framewrk fr perfrmance assessment f shp-flr cntrl systems. SIMULATION: Transactins f the Sciety f Mdeling and Cmputer Simulatin Internatinal 79(3): Mönch, L Simulatin-based assessment f rder release strategies fr a distributed shifting bttleneck heuristic. In Prceedings f the 2005 Winter Simulatin Cnference, , Orland, USA. Qu, P., and S. J. Masn Metaheuristic Scheduling f 300mm Jbs Cntaining Multiple Orders. IEEE Transactins n Semicnductr Manufacturing 18(4): AUTHOR BIOGRAPHIES JENS ZIMMERMANN is a Ph.D. student in the Department f Mathematics and Cmputer Science at the FernUniversität in Hagen, Germany. He received a master s degree in infrmatin systems frm the Technical University f Ilmenau. He is interested in semicnductr manufacturing, simulatin, multi-agent-systems, and machine learning. He is a member f GI (German Chapter f the ACM). His address is <Jens.Zimmermann@- fernuni-hagen.de>. LARS MÖNCH is a Prfessr in the Department f Mathematics and Cmputer Science at the University in Hagen, Germany and heads the chair f enterprise-wide sftware systems. He received a master s degree in applied mathematics and a Ph.D. in the same subject frm the University f Göttingen, Germany. His current research interests are in simulatin-based prductin cntrl f semicnductr wafer fabricatin facilities, applied ptimizatin and artificial intelligence applicatins in manufacturing and lgistics. He is a member f GI (German Chapter f the ACM), GOR (German Operatins Research Sciety), SCS, INFORMS, IIE, and serves as an Assciate Editr f IEEE Transactins n Autmatin Science and Engineering. His address is <Lars.Mench@fernunihagen.de>. SCOTT MASON is an Assciate Prfessr in the Department f Industrial Engineering < uark.edu/> at the University f Arkansas. He received his 2169

7 Ph. D. in Industrial Engineering frm Arizna State University after earning Bachelr's and Master's degrees frm The University f Texas at Austin. Dr. Masn's areas f fcus include scheduling and large-scale systems mdeling, ptimizatin, and algrithms, with dmain expertise in semicnductr manufacturing and transprtatin lgistics. He is an Assciate Editr fr IEEE Transactins n Electrnics Packaging Manufacturing < trans-/trans-epm.html> and currently serves as Assciate Department Head f Industrial Engineering and Chair f Graduate Studies at Arkansas. JOHN FOWLER is a Prfessr f Industrial Engineering at Arizna State University (ASU) and was the Center Directr fr the Factry Operatins Research Center that was jintly funded by Internatinal SEMATECH and the Semicnductr Research Crpratin. His research interests include mdeling, analysis, and cntrl f semicnductr manufacturing systems. Dr. Fwler is a member f IIE, INFORMS, and SCS. He is an Area Editr fr SIMULATION: Transactins f the Sciety fr Mdeling and Simulatin Internatinal and an Assciate Editr f IEEE Transactins n Semicnductr Manufacturing. He is an IIE Fellw, the Vice President f Chapters/Fra fr INFORMS, the Trasurer f Omega Rh, and is n the Winter Simulatin Cnference Bard f Directrs. Zimmermann, Mönch, Masn, and Fwler 2170