SASIMI: Sparsity-Aware Simulation of Interconnect-Dominated Circuits with Non-Linear Devices

Transcription

1 SASIMI: Sparsity-Aware Simuation of Interconnect-Dominated Circuits with Non-Linear Devices Jitesh Jain, Stephen Cauey, Cheng-Kok Koh, and Venkataramanan Baakrishnan Schoo of Eectrica and Computer Engineering Purdue University, West Lafayette, IN Abstract We present a technique for the fast and accurate simuation of argescae VLSI interconnects with noninear devices, caed SASIMI The numerica efficiency of this technique is reaized through inear-agebraic techniques that expoit the sparsity and structure of the matrices that are encountered in VLSI structures Numerica resuts show that SASIMI is up to 14 times as fast as commercia-grade SPICE, for moderatesize circuits, with itte sacrifice in simuation accuracy 1 Introduction With aggressive technoogy scaing, the accurate and efficient modeing and simuation of interconnect effects has become and continues to be) a probem of centra importance For accurate modeing of the distributive effects of interconnects, it is necessary to mode a ong wire using many segments of umped RLC eements Owing to the inductive and capacitive couping between these eements, direct simuation of the resuting modes comes at a very high and often unacceptabe) simuation cost It has been highighted in the past that SPICE [11] is not amenabe to the simuation of interconnectdominated structures, such as power/ground networks, cock networks, and busses There have been many studies to eiminate the botteneck due to SPICE in the past severa years A representative seection of these advances in the simuation of arge-scae interconnects, which expoit the ocaity of capacitive and inductive couping effects, can be cassified into techniques at the modeing and simuation eves as foows: Modeing eve techniques: In [5], the authors propose a new circuit eement K to capture the inductive couping using the inverse of the inductance matrix Window-based extraction of K eements are proposed in [], [15], and [16] In [8], the authors use controed votage and current sources to construct a SPICE-compatibe circuit mode for K eements A simiar concept, caed Vector Potentia Equivaent Circuit VPEC), is introduced in [1] to obtain a ocaized circuit mode for inductive interconnects These techniques invove the inversion of the inductance matrix To avoid matrix inversion, the authors of [16] propose a wire dupication-based interconnect mode, in which the authors construct a sparse equivaent circuit by windowing the inductance matrix However, it shoud be emphasized that a these techniques utimatey rey on SPICE and its variants) for the simuation of dynamic responses, and thus are constrained by the imitations of SPICE Simuation eve techniques: The underying sover in a simuation too essentiay addresses the probem of soving Ax = b fast In [14], the authors propose a hierarchica anaysis of power distribution networks In this work the authors partition the power grid and mode each partition as a macro-mode with a sparsified port admittance matrix In [3], INDUCTWISE, an efficient simuation too for circuits modeed using conductance G), capacitance C), and K eements, is proposed In [14], and [3], it is shown that the Choesky factorization of the A matrix, which is composed of G, C, and/or K, can be very efficient due to the inherent sparsity of A However, the inverse of A is dense, which in turn impies that each simuation step invoves dense matrix-vector mutipications In contrast, the authors of [7] perform inear circuit simuation using a new formuation, caed RLP, to mode circuits by resistance R), inductance L), and the inverse of capacitance P) Athough the resuting A matrix in the RLP formuation is dense, its inverse is sparse, which enabes fast sparse matrix inversion and sparse matrix-vector mutipication in each simuation step The above methods however, are unabe to hande non-inear devices This probem is addressed in [4], where the approach in [14] is extended to hande non-inear devices However, it aso inherits the imitation that the sparsity of matrix A is expoited ony for fast Choesky factorization, and not in each simuation step In this paper, we propose SASIMI which uses sparsity-aware simuation techniques for interconnect-dominated circuits with noninear devices Our contribution in this paper is two fod First, we extend the RLP formuation as described in [7] to incude non-inear devices, without sacrificing the computationa benefits achieved due to sparsity of the inear system It shoud be noted that the A matrix invoved in the soution of the inear system is constant throughout the simuation In contrast, the A matrix invoved in soving the non-inear system changes in each simuation step However, the A matrix is sparse Due to the sparse and time varying nature of the probem at hand Kryov subspace based iterative methods coud be used for efficient simuation Our second contribution is to introduce a nove preconditioner constructed based on the sparsity structure of the non-inear system The inverse of the preconditioner has a compact representation in the form of the Hadamard product [1], which faciitates not ony the fast computation of the inverse, but aso the fast dense matrix-vector product Experimenta resuts show that SASIMI is up to 14 times faster than commercia grade SPICE, even for moderate-size circuits Mathematica Preiminaries VLSI interconnect structures, with non inear devices can be anayzed using the Modified Noda Anaysis MNA) formuation which yieds equations of the foowing form where G = [ G A T A Gx + Cẋ = b, 1) ] [ C, C = L ] [ ] vn, x =, i

2 [ A T b = i I s + I n ], G = A T g R 1 A g, and C = A T c CA c R denotes the resistance matrix The matrices G, L and C are the conductance, inductance and capacitance matrices respectivey, with corresponding adjacency matrices A g, A and A c I s is the current source vector with adjacency matrix A i,andv n and i are the node votages and inductor currents respectivey Vector, I n captures the effect of non-inear oads and depends on the node votages as I n = f v n ) f is a function which varies depending on the oad characteristics and in genera can be a noninear function With N denoting the number of inductors, we note that L,C,R R N N, C,G R N N Differentia equations such as 1) can be numericay soved using standard agorithms ike the trapezoida method [1] Considering a uniform discretization of the time axis with resoution h, x k = xkh) Using the approximations d dt xt) x x k and x k x + x k t=kh h over the interva [kh,k + 1)h], the determination of x from x k requires the soution of a set of inear and noninear equations: G + C ) G x = h C ) x k + b + b k ) h and In = f v ) n 3) The noninearity in the above set of equations can be handed by the standard Newton-Raphson technique of inearizing 3) and iterating unti convergence: Equation ) is a inear equation of the form Lx)=, where we have omitted the iteration index k for simpicity Equation 3) is a noninear equation of the form gx) = Let gx) Gx) be a inear approximation of gx), inearized around some x = x Then, simutaneousy soving Lx)=andGx)= yieds numerica vaues for x and hence v n These vaues are then used to obtain a new inear approximation gx) G new x), andthe process is repeated unti convergence A good choice of the point x for the initia inearization at the kth time-step is given by the vaue of v n from the previous time-step A direct impementation of this agorithm requires Opqn 3 1 ) operations, where p is the number of time steps, q is the maximum number of Newton-Raphson iterations in each time step, and n 1 = 3N 3 The RLP formuation The mathematica framework that underies our approach is an aternative formuation of the MNA equations that uses the resistance, inductance and the inverse of the capacitance matrix This is the so-caed RLP formuation, first proposed in [7] We begin by decomposing C, A, anda i as: C = C cc C vc C cv C vv, A T = A T 1 A T AT i = A T i1 A T i I n = v n = v c Here C vv denotes the sub-matrix I v v v of the capacitance matrix that changes amid the simuation, whie a other sub-matrices remain constant The matrix C vv captures the drain, gate and buk capacitances of a devices, which are votagedependent, whie C cc,andc cv are the capacitance matrices that arise from interconnects and are hence constant For typica interconnect structures, the above decomposition aows us to manipuate the MNA equations ) and 3): ) L h + R + h 4 A 1P cc A T 1 X i L = h R h ) 4 A 1P cc A T 1 i k Y + A 1 v k c + h 4 A 1P cc A T i1 I A 1 P cc C cv v v v A v + v v + v k v), 4) vc = v k c h P cca T i + i h + P cca T i1 I P cc C cv v v v k v), 5) C vv v v = C vv v k v h AT i + i h + AT i I C vc v c v h c + I v + I v, 6) Iv = f vv ) 7) Here r denotes the size of interconnect structure connected directy to non inear circuit, and given = N r we note that C cc R, C vv R r r P cc = Ccc 1 is the inverse capacitance matrix, and A is the adjacency matrix of the circuit A is obtained by first adding A g and A and then removing zero coumns these correspond to intermediate nodes, representing the connection of a resistance to an inductance) The deveopment thus far is simiar to that in [7], with the major difference being the addition of 6) and 7), which account for the noninear eements The main contribution in [7] was the fast soution of 4) and 5), where a matrices are constant over the simuation period We wi show in 4 that the techniques in [7] can be extended to hande the case when noninear eements are present For future reference, we wi ca the technique of directy soving 4), 5), 6), and 7) as the Exact-RLP agorithm It can be shown that the computationa compexity of the Exact-RLP agorithm is O 3 + pq + r 3)) For arge VLSI interconnect structures we have >> r, reducing the compexity to O 3 + pq )) 4 Computationay efficient impementation We now turn to the fast soution of equations 4) through 7) Reca that the noninear equation 7) is handed via the Newton-Raphson technique This requires, at each time step, inearizing 7) and sub-

3 Figure 1: Sparsity structure of A The nonzero entries are shown darker Figure : Sparsity structure of A shown darker The non-zero entries are stituting it into 6) The resuting set of inear equations have very specific structure: Equations 4) and 5) are of the form Ax = b where A is fixed does not change with the time-step) Moreover, A 1 is typicay approximatey sparse For detais, see 4) is an upper Heisenberg matrix For these methods the choice of a preconditioner matrix M,which is an approximation of A, can greaty affect the convergence A good preconditioner shoud have the foowing two properties: M 1 A I Equation 6) after the substitution of the inearized 7)) is again of the form Ax = b, where the matrix A is obtained by adding C vv and the coefficient of the first-order terms in the inearized equation 7) Reca that the matrix C vv captures the drain, gate and buk capacitances of a devices It aso contains the interconnect couping capacitances between gates and drains of different non-inear devices in the circuit As each non-inear device is connected to ony a few nodes and the capacitive effects of interconnects are ocaized, the A matrix is observed to be sparse in practice For detais, see 41) Note that A changes with each Newton-Raphson iteration and with the time-step Thus the key computationa probem is the soution of a sparse timevarying set of inear equations, couped with a arge fixed system of inear equations Ax = b with A 1 being sparse 41 Soving sparse time-varying inear equations Kryov subspace methods have been shown to work extremey we for sparse time-varying inear equations [6] Specificay, the GM- RES Generaized Minimum Residua) method of Saad and Schutz [13] aows the efficient soution of a sparse, possiby non-symmetric, inear system to within a pre-specified toerance This method performs a directiona search aong the orthogona Arnodi vectors which span the Kryov subspace of A That is, given an initia guess x and corresponding residua r = b Ax, orthogona vectors {q 1,q,q m are generated with the property that they span S m, the soution search space at iteration m S m = x + span{r,ar,,a m r = x + κa,r,m) span{q 1,q,q m 8) These vectors are chosen according to the Arnodi iteration: AQ m = Q m+1 H m where Q m = {q 1,q,q m is orthogona and H m R m+1 m It must accommodate a fast soution to an equation of the form Mz = c for a genera c Figure 1 depicts the sparsity structure of the A matrix for a circuit exampe of parae wires driving a bank of inverters For such a sparsity structure, an appropriate choice of the preconditioner coud be of the form as shown in Figure 3 Athough we have chosen a circuit with ony inverters for simpicity, a more compicated circuit structure woud simpy distribute the entries around the diagona and off-diagona bands and ead to possiby more off diagona bands To see this, consider an extreme case where the circuit under consideration has ony non-inear devices and does not comprise of interconnects In this case the sparsity pattern of the A matrix is as shown in Figure Therefore, the chosen preconditioner woud encompass not ony the sparsity structure shown in Figure 1 but aso other sparsity patterns that might arise with the anaysis of more compicated noninear devices Correspondingy the structure of the preconditioner see Figure 3) woud have additiona bands Matrices of the form shown in Figure 3 have the foowing two properties which make them an idea choice for preconditioner The inverses of the preconditioner matrix can be computed efficienty in inear time, Or) r denotes the size of interconnect structure directy connected to non-inear devices), by expoiting the Hadamard product formuation as shown in [1] It can aso be shown that this formuation faciitates the fast matrix-vector products, again in inear time Or)), which arise whie soving inear systems of equations with the preconditioner matrix A simpe exampe which best iustrates these advantages is a

4 been shown with a sma exampe as beow a 1 b 1 a B = b b 1 a 3 1) b a 4 a 1 b 1 b = P 1 a a 3 b P, 13) b a 4 X where 1 1 P = 1 1 Figure 3: Preconditioner matrix symmetric tridiagona matrix a 1 b 1 b 1 a b B = b n a n 1 b n 1 b n 1 The inverse of B can be represented compacty as a Hadamard product of two matrices, which are defined as foows: u 1 u 1 u 1 v 1 v v n B 1 u 1 u u v v v n = 1) u 1 u u n v n v n v n U V There exists an expicit formua to compute the sequences {u,{v efficienty in On) operations which is detaied in [1] In this case, if we are interested in soving a inear system of equations By = c, we ony need to concern ourseves with the matrix-vector product B 1 c = y This computation can aso be performed efficienty in On) computations as outined beow: P ui = i j=1 u j c j, P vi = n j=i v j c j, a n i = 1,,n, 9) y 1 = u 1 P v1, y i = v i P ui 1 + u i P vi, i =,,n 11) The above formuation for a tridiagona matrix coud be easiy extended to hande the more genera case when the preconditioner matrix is a zero padded bock tridiagona matrix matrix with zero diagonas inserted between the main diagona and the non-zero superdiagona and sub-diagona of tridiagona matrix) as in Figure 3 Eementary row and coumn bock permutations coud be performed on such a matrix to reduce it into a bock tridiagona matrix This has Hence B 1 = PX 1 P T u 1 u 1 v 1 v 3 u = u v u 1 u 3 v 4 v 3 v 3 14) u u 4 v 4 v 4 U V We have not incuded bock matrices for simpicity of presentation, however the zero padded bock tridiagona case is a natura extension of the above exampe A the entries in U,V matrices have to be now repaced by bocks and accordingy the row and coumn permutations woud be repaced by their bock counterparts with an identity matrix of appropriate size repacing the ones in the P matrix Tabe 1 gives the comparison for Incompete-LU preconditioner and the zero-padded Z-Pad) preconditioner Simuations were done on circuits consisting of busses with parae conductors driving bank of inverters Size denotes the number of non-inear devices A the resuts are reported as a ratio of run-time and iteration-count number of iterations for the soution to converge to within a toerance of 1e-1) of Z-Pad to the Incompete-LU preconditioner As can be seen from Tabe 1, Z-Pad offers a substantia improvement in run time as compared to the Incompete-LU preconditioner Size Runtime Iterations 5/1 5/1 5/1 5/1 Tabe 1: Preconditioner comparison 4 Soving Ax= b with a constant, approximatey sparse A 1 We now turn to the soution of equations 4) and 5) As mentioned earier, these equations reduce to the form Ax = b with a constant, approximatey sparse A 1 A corresponding to X in 4)) is composed of L, R and P Each of these matrices has a sparse inverse for typica VLSI interconnects which then eads to a approximatey sparse A 1 Note that this argument is used for motivating the sparsity inherent in A 1 and cannot be used as a theoretica proof for the same) In addition this sparsity has a reguar pattern which can be expained on the basis of how inductance and capacitance matrices are extracted The distributed RLC effects of VLSI interconnects can be modeed by dividing conductors into sma subsets of segments,

5 Sparsity Index Size Figure 4: Average sparsity versus circuit size each of which are aigned [9, 3] Each of these subsets eads to a sparsity pattern corresponding to a band in A 1 ) A the effects when summed up ead to a A 1 matrix that has a reguar sparsity pattern Window seection agorithm as described in [16, 3] coud then be empoyed to find out the sparsity pattern in A 1 It has been recognized in earier work that this property sparsity) yieds enormous computationa savings; it has been shown in [7] that an approximate impementation of the Exact-RLP agorithm, referred to simpy as the RLP agorithm provides an order-of-magnitude in computationa savings with itte sacrifice in simuation accuracy To proceed, we rewrite 4) and 5) as i = X 1 Yi k + X 1 A 1 v k c + h 4 X 1 A 1 P cc A T i1 I X 1 A 1 P cc C cv v v v A v + v v + v k v), 15) X 1 A 1 v c + h X 1 A 1 P cc A T i1 = X 1 A 1 v k c X 1 h A 1 P cca T I k i + i ) X 1 A 1 P cc C cv v v v k v) 16) Athough X is a dense matrix, X 1 turns out to be an approximatey sparse matrix Moreover the matrices X 1 Y, X 1 A 1, X 1 A 1 P cc A T i1, X 1 A 1 P cc C cv are aso approximatey sparse [7] This information can be used to reduce the computation significanty by noting that each step of trapezoida integration now requires ony sparse vector mutipications Soving sparse 15) and 16) aong with 6) and 7) is termed as the RLP agorithm SASIMI) To anayze the computationa saving of the approximate agorithm over the Exact-RLP agorithm, we denote sparsity index of a matrix A as ratio of the number of entries of A with absoute vaue ess than ε to the tota number of entries The computation required for each iteration of 15) and 16) is then O 1 ν) ), where ν is the minimum of the sparsity indices the matrices X 1 Y, X 1 A 1, X 1 A 1 P cc A T i1, X 1 A 1 P cc C cv Figure 4 provides the average sparsity for the matrices for a system with parae conductors driving a bank of inverters The sizes in consideration are 1,, 5 and 1 On top of this the computation time of X 1 can be reduced to O) by using the windowing techniques detais in [16]) Hence the computationa compexity of RLP is O pq1 ν) ) as compared to O pqn1) 3 for the MNA approach σ ρ=5 ρ= ρ= Tabe : RMSE comparison 5 Numerica resuts and concusions We impemented the Exact-RLP and RLP SASIMI) agorithms in C++ A commerciay avaiabe version of SPICE with significant speed-up over the pubic-domain SPICE has been used for reporting a resuts with SPICE Simuations were done on circuits consisting of busses with parae conductors driving bank of inverters, with wires of ength 1mm, cross section 1µm 1µm, and with a wire separation of 1µm A periodic 1V square wave with rise and fa times of 6ps each was appied to the first signa with a time period of 4ps A the other ines were assumed to be quiet For each wire, the drive resistance was 1Ω A time step of 15ps was taken and the simuation was performed over 3 ps or time steps) For the inverters the W/L ratio of NMOS and PMOS were taken to be 4µm/5µm and 16µm/5µm respectivey In order to expore the effect of the number of non-inear eements reative to the tota, three cases were considered With ρ denoting the ratio of the number of inear eements to that of non-inear eements, the experiments were performed for ρ equaing 5, and 5 The number of inear eements in the foowing resuts is denoted by σ We first present resuts comparing the accuracy in simuating the votage waveforms at the far end of the first ine after the inverter oad) The metric for comparing the simuations is the reative mean square error RMSE) defined as i v i ṽ i ) i v i where v and ṽ denote the waveforms obtained from Exact-RLP and SASIMI respectivey Tabe presents a summary of the resuts from the study of simuation accuracy It can be seen that the simuation accuracy of the Exact-RLP agorithm is amost identica to that of SPICE, whie the SASIMI has a marginay inferior performance as measured by the RMSE The error vaues for SASIMI are compared simpy with the Exact-RLP as it had the same accuracy as SPICE resuts for a the experiments run A pot of the votage waveforms at the far end of the active ine, obtained from SPICE, Exact-RLP and SASIMI agorithms, is shown in Figure 5 The number of conductors in this simuation exampe is ) There is amost no detectabe simuation error between the SASIMI, Exact-RLP and SPICE waveforms over time steps To give a better picture, the accuracy resuts reported are for a arger simuation time of time steps We now turn to a comparison of the computationa requirements between Exact-RLP, SASIMI and SPICE Tabe 3 summarizes the findings For a fair comparison our tota simuation time is compared against the transient simuation time for SPICEie we have not incuded any of the error check or set up time for SPICE) As can be seen from the tabe, SASIMI outperforms the Exact-RLP agorithm and SPICE For the case of 5 conductors with ρ = 5, the Exact-RLP agorithm is 39 times as fast compared to SPICE SASIMI is about 14 times faster as compared to SPICE, and more than three times faster than Exact-RLP As can be seen, the computationa savings increase as the ratio of inear to non-inear eements is

6 σ ρ=5 ρ= ρ=5 SPICE Exact-RLP SASIMI SPICE Exact-RLP SASIMI SPICE Exact-RLP SASIMI >1hrs >1hrs >1hrs > 1day > 1day > 1day Tabe 3: Run time in seconds) comparisons Votage > SPICE Exact RLP SASIMI Time > x 1 1 Figure 5: The votage waveforms obtained through SPICE, Exact-RLP and SASIMI increased from 5 to 5 The savings aso increase with increase in the size of the probem considered The computationa efficiency of the SASIMI can be expained on the use of sparsity-aware agorithms for both the inear and non-inear parts of the probem 6 Acknowedgments This materia is based on work supported by the NASA, under Award NCC -1363, and by Nationa Science Foundation under Award CCR and CCR-336 References [1] U M Ascher and L R Petzod Computer Methods for Ordinary Differentia Equations and Differentia- Agebraic Equations SIAM, 1998 [] M Beattie and L Pieggi Modeing magnetic couping for on-chip interconnect In Proc Design Automation Conf, pages , 1 [3] T H Chen, C Luk, H Kim, and C C-P Chen IN- DUCTWISE: Inductance-wise interconnect simuator and extractor In Proc Int Conf on Computer Aided Design, pages 15, [4] T-H Chen, J-L Tsai, C C-P Chen, and T Karnik HISIM: Hierarchica interconnect-centric circuit simuator In Proc Int Conf on Computer Aided Design, pages , 4 [5] A Devgan, H Ji, and W Dai How to efficienty capture on-chip inductance effects: Introducing a new circuit eement K In Proc Int Conf on Computer Aided Design, pages , [6] G H Goub and C F Van Loan Matrix Computations John Hopkins University Press, 1996 [7] J Jain, C-K Koh, and V Baakrishnan Fast simuation of VLSI interconnects In Proc Int Conf on Computer Aided Design, pages 93 98, 4 [8] H Ji, Q Yu, and W Dai SPICE compatibe circuit modes for partia reuctance K In Proc Asia South Pacific Design Automation Conf, pages , 4 [9] T Lin, M W Beaftie, and L T Pieggi On the efficacy of simpified D on-chip inductance In Proc Design Automation Conf, pages , [1] R Nabben Decay rates of the inverses of nonsymmetric tridiagona and band matrices SIAM Journa on Matrix Anaasis and Appications, 3):8 837, May 1999 [11] L W Nage SPICE: A computer program to simuate semiconductor circuits Technica report, UC Berkeey, ERL Memo ERL-M5, 1975 [1] A Pacei A oca circuit topoogy for inductive parasitics InProc Int Conf on Computer Aided Design, pages 8 14, [13] Y Saad and M Schutz GMRES: A generaized minima residua agorithm for soving non-symmetric inear systems SIAM Journa on Scientific Computing, pages , 1986 [14] M Zhao, R V Panda, S S Sapatnekar, and D Baauw Hierarchica anaysis of power distribution networks IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, pages , February [15] H Zheng, B Krauter, M Beattie, and L Pieggi Windowbased susceptance modes for arge scae RLC circuit anayses In Proc Design Automation and Test in Europe Conf, pages , [16] G Zhong, C-K Koh, and K Roy On-chip interconnect modeing by wire dupication In Proc Int Conf on Computer Aided Design, pages ,