VLSI Implementation of High-Performance CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphic Systems

Transcription

1 Proceedgs of the 6th WSEAS Iteratoal Coferece o Istrumetato, Measuremet, Crcuts & Systems, Hagzhou, Cha, Aprl 5-7, 7 7 VLSI Implemetato of Hgh-Performace CORDIC-Based Vector Iterpolator Power-Aware 3-D Graphc Systems TZE-YUN SUNG Departmet of Mcroelectrocs Egeerg Chug Hua Uversty 77, Sec., Wufu Road Hschu, 3, TAIWAN Abstract: - Hgh performace archtectures for the data tesve ad latecy restraed applcatos ca be acheved by maxmzg both parallelsm ad ppelg. I ths paper, the CORDIC based hardware prmtves of 3-D rotato wth hgh throughput 3-D vector terpolato are preseted. The proposed archtecture for 3-D vector terpolator, whch s based o the redudat CORDIC arthmetc, has bee mplemeted by VLSI ad acheve up to eergy savg wthout mage qualty degradato. The graphc system s power-aware. Key-Words: - Redudat arthmetc, CORDIC, 3-D, vector terpolato, power-aware, hgh-throughput, parallelsm ad ppelg, VLSI. Itroducto Flexble hardware alog wth precso cotrol s very desrable for the power-aware 3-D graphcs rederg applcatos. I [], 3-D vector terpolato s requred. The 3-D vector terpolator of Euh et al. provdes multple precsos for the desg of power-aware systems []. The well kow CORDIC algorth whch has bee appled wth a great success to the hardware mplemetatos of may sgal processg tasks, e.g. se ad cose geerato, vector rotato, coordate trasformato, ad lear system solvg, s sutable for the mplemetato of 3-D vector terpolato [3]-[4]. I CORDIC, oly smple shfters ad adders are eeded, whch ca be realzed by the use of recofgurable hardware platforms, especally by FPGA [5]. Thus, the CORDIC-based 3-D vector terpolator s more flexble for the terpolato task. I ths paper, the archtecture of 3-D vector terpolator based o the CORDIC algorthm s proposed. It s sutable for VLSI mplemetato terms of the computatoal complexty. The remader of the paper s orgazed as follows. I secto, the covetoal CORDIC algorthm s revewed. I secto 3, the 3-D CORDIC algorthm s gve. The proposed VLSI archtecture of 3-D vector terpolator based o the CORDIC rotato algorthm s preseted secto 4. Its aalyss s gve secto 5, ad the cocluso ca be foud secto 6. The CORDIC Algorthm CORDIC (COordate Rotato DIgtal Computer s a algorthm performg a sequece of terato computatos by the use of coordate rotato [3] [4]. It ca be used to geerate mportat elemetary fuctos by usg oly smple adders ad shfters. The basc CORDIC terato equatos are gve by s( x x m + = σ y ( s( y y + = + σ x ( z + = z σ α (3 where m deotes the crcular (, lear (m= or hyperbolc (m=- coordate syste =,,,., -, s ( = /,,,3,4,5,..., m =,,3,4,5,6,..., m =, ad,,3,4,4,5,..., m = s( α = m ta [ m ] (4 The rotato σ = sg z for the rotato mode ( ( z ; σ = sg( x sg( y for the vectorg mode ( y. The scale factor s(, + k m = mσ the -th terato. After teratos, the product of all the scale factors s as follows. K m = k m =, = + mσ = + m (5 = s( = s( where the rotato drecto s defed by σ = {, + }.

2 Proceedgs of the 6th WSEAS Iteratoal Coferece o Istrumetato, Measuremet, Crcuts & Systems, Hagzhou, Cha, Aprl 5-7, D CORDIC Algorthm Fgure shows a vector R the 3-D space. Its respectve Cartesa ad sphercal coordates are (, Y, Z ad ( R, θ, φ. R ca be rotated ad the becomes a ew vector deoted by S wth Cartesa coordates ( +, Y+, Z + ad sphercal coordates ( R, θ + α, φ + β. The relatoshp betwee the Cartesa coordates ad sphercal coordates of R ad S are gve by = R cosθ sφ (6 Y = R sθ sφ (7 Z = R cosφ (8 + = R cos( θ + α s( φ + β (9 Y+ = R s( θ + α s( φ + β ( Z + = R cos( φ + β ( Equatos (9, ( ad ( ca be rewrtte by + = R (cosθ sθ sα (sφ cosβ + cosφ sβ = R cos θ sφ cosβ + R cosθ cosφ sβ R sθ sφ sα cosβ R sθ cosφ sα sβ = cosβ + U s β Y sα cosβ V sα s β ( Y + = Y cosβ + V sβ + sα cosβ + U sα sβ (3 Z + = Z cos β W s β (4 whereu, V ad W are defed as follows. U = R cosθ cosφ (5 V = R sθ cosφ (6 W = R sφ (7 It s oted thatu +, V + ad W + ca be wrtte by U+ = U cosβ sβ V sα cosβ + Y sα sβ (8 V + = V cosβ Y sβ + U sα cosβ sα sβ (9 W+ = W cos β + Z s β ( Based o equatos (6, (7 ad (8, equatos (, (3, (4, (8, (9 ad ( ca be computed by usg the followg set of CORDIC rotatos. U V + + ( + = V Y + U δ δ ρ k W = ( U ρ Vδ Yδ ρ ( k ρ ( = ( W Z ρ (3 k ( + = Y + V + δ + U δ ρ k Y = ( + U ρ Yδ Vδ ρ (4 k ρ (5 Z + = ( Z W ρ k (6 where = + (7 sα = δ + (8 cos β = + (9 s β = ρ + (3 k = + (3 I the -D CORDIC rotato, α = δ ta, β = ρ ta, ad δ ad ρ are {, }. Equatos ( ad ( ca be expressed the matrx for whch s gve by U + δ U = V+ k δ V δ ρ (3 k δ Y Smlarly, equatos (4 ad (5 ca be rewrtte by + δ = Y + k δ Y δ U + ρ (33 k δ V It s oted that there are four -D CORDIC rotatos volved the 3-D rotato of a vector. I addto, the scale factor of Z + ad W + s dfferet from that of U +, V +, + ady +. They ca be compesated va the pre-scale of puts or post-scale of outputs wth ther respectve costats K ad K, whch are gve by K (34 = k = = k = K (35

3 Proceedgs of the 6th WSEAS Iteratoal Coferece o Istrumetato, Measuremet, Crcuts & Systems, Hagzhou, Cha, Aprl 5-7, VLSI Archtecture for 3-D Vector Iterpolator Vector terpolato ca be obtaed by usg algorthms based o sphercal terpolato, lear terpolato or CORDIC terpolato. The sphercal terpolato volves complex computatos. The lear terpolato requres post ormalzato, whch s also complex. The proposed CORDIC-based 3-D terpolator, whch s performed o polar compoets, s effcet ad very flexble terms of the hardware mplemetatos. Fgure shows the archtecture of the proposed 3-D vector terpolator by usg the crcular CORDIC algorthm wth rotato mode. I whch, the geerators of ( U +, V+ ad ( +, Y+ cosst of two -D CORDIC processors, two hardwre shfters, ad two adders/sub-tractors. The geerators of W + ad Z + cosst of half -D CORDIC Processor. The tal coordates ( U, V, W are obtaed by usg the auxlary geerator ( U, V, W [6], whch s show Fgure 3. Thus, the proposed archtecture s composed of the auxlary geerator ( U, V, W, the redudat CORDIC arthmetc (for the computato of 3-D vector terpolato, ad dual-memory baks (for storg the coordates (, Y, Z ad ( U, V, W, respectvely. The hardware code of the proposed system s wrtte Verlog-hardware descrpto Laguage (HDL [7]. The system dagram s show Fgure 4. The cotrol ut s desged by the fte state mache (FSM, the state dagram of FSM s show Fgure 5, ad the hardware code of FSM s show Appedx. The chp s sytheszed by TSMC.8 µ m P6M CMOS cell lbrares [8]. The gate cout s reported by the Syopsys desg aalyzer [8]. The power cosumpto s reported by PrmPower [8]. The layout vew of the 3-bt 3-D vector terpolator s show Fgure 6. The core sze s53 µ m 53µ ad the power dsspato s 49.35mW wth the clock rate of MHz at.8v. The crtcal path s 4.7 s. All cotrol sgals are geerated terally o-chp. Ths chp offers a hgh throughput wth low gate couts by usg a parallel-ppeled archtecture. 5 Advatages of New Archtectures ad Algorthms The Euler agle method takes a sequece of three rotatos [], [9], each of whch rotates wth respect to oe of the three orthogoal axes. Ths method ca be represeted by the Euler agles correspodg to the sequece of rotatos wth respect to the coordate axes. I [], the 3-D rotato s mplemeted by cascadg two -D CORDIC processors. Lag ad Atelo developed a method to replace the two -D CORDIC processors by oe 3- D CORDIC processor [7]. The sequece of rotatos s composed of oe -D CORDIC rotato followed by oe 3-D CORDIC rotato. Both of the aforemetoed methods requre more tha two -D CORDIC computatos. I the proposed 3-D rotato algorth the archtecture based o the covetoal CORDIC processor requres oe -D CORDIC computato parallel wth fve CORDIC processors. The auxlary geerator of coordate ( U, V, W ad the redudat arthmetc CORDIC for 3-D rotato ca perform parallel. Four termedate vectors betwee Vad V are show Fgure 7. Vector terpolator mplemeted by CORDIC cossts of two steps. Frst step terpolates the polar compoets of the two gve vectors learly accordg to the posto of termedate vector. Istead of vector ormalzato, 3-D CORDIC vector rotato s performed to produce ormalzed vector the secod step. We make the fucto of 3-D geometry rotato ad graphc rederg by usg the proposed algorthm ad archtecture s show Fgure 8, Fgure 8(a shows the orgal mage, ad Fgure 8(b shows the rotated ad redered mage. 3-D vector terpolato could acheve more tha 7% eergy savg wthout mage qualty degradato. We have a power-aware graphc system. 6 Cocluso Hgh-throughput archtecture for the 3-D vector terpolato task based o the CORDIC algorthm s preseted. It takes oly oe covetoal CORDIC computato tme. The proposed archtecture by the use of CORDIC processor s smple, regular ad therefore sutable for VLSI mplemetato. I power-aware 3-D graphcs rederg, the performace of 3-D vector terpolato ca be mproved by usg the proposed algorthm ad archtecture. Table shows the comparso of ths work wth Eberly [], Lag ad Atelo [9] ad Euh [].

4 Proceedgs of the 6th WSEAS Iteratoal Coferece o Istrumetato, Measuremet, Crcuts & Systems, Hagzhou, Cha, Aprl 5-7, 7 Refereces: [] B. Phog, Illumato for Computer Geerated Pctures, Commucatos of the ACM, 975, pp [] J. Euh, J. Chttamuru, W. Burso, CORDIC Based Iterporator for 3-D Graphcs, IEEE Workshop o Sgal Processg Systems,, pp [3] J. E. Volder, The CORDIC Trgoometrc Computg Techque, IRE Trasactos o Electroc Computers, Vol. EC-8, 959, pp [4] J. S. Walther, A Ufed Algorthm for Elemetary Fuctos, Sprg Jot Computer Coferece Proceedgs, Vol.38, 97, pp [5] O. Mecer, L. Semera, M. Morf, J. Delosme, Applcato of Recofgurable CORDIC Archtecture, The Joural of VLSI Sgal Processg, Specal Issue o Recofgurable Computg,. [6] T.-Y. Sug, Y.-H Hu, H.-J. Yu, Doubly Ppeled CORDIC Array for Dgtal Sgal Processg, It l Cof. o Acoustc, Speech ad Sgal Processg, Tokyo, Japa, 986, pp [7] D. E. Thomas, P. H. Moorby, The Verlog Hardware Descrpto Laguage, Ffth Edto, Kluwer Academc Pub.,. [8] Syopsys, syopsys. com/products. [9] T. Lag, E. Atelo, Hgh-Throughput CORDIC- Based Geometry Operatos for 3D Computer Graphcs, IEEE Trasactos o Computers, Vol. 54. No. 3, 5, pp [] D. H. Eberly, 3-D Game Ege Desg-A Practcal Approach to Real-Tme Computer Graphcs, Morga Kaufma Pub.,. z R Fg.. Vector R the 3-D space φ y θ x ta β ρ U V δ Y α ADD/SUB -D CORDIC -D CORDIC ρ + β + Shfter Shfter δ + W Z ρ α + ρ ADD/SUB ADD/SUB Shfter ADD/SUB ρ Y δ U U V + + V α W + -D CORDIC -D CORDIC Z W Shfter Shfter δ + Shfter α + ρ ADD/SUB ADD/SUB ADD/SUB ρ Y + + Fg.. The archtecture of the 3-D vector terpolator wth the CORDIC algorthm Z +

5 Proceedgs of the 6th WSEAS Iteratoal Coferece o Istrumetato, Measuremet, Crcuts & Systems, Hagzhou, Cha, Aprl 5-7, 7 cosφ sφ sφ Rotato Mode sφ cosφ m= Vectorg Mode U = cotφ δ Y Y cosφ sφ sφ Rotato Mode Y sφ Y cosφ m= Vectorg Mode V = Y cotφ δ Z Z cosφ cosφ cosφ Rotato Mode Z sφ Z sφ m= Vectorg Mode W = Z taφ δ cosφ Rotato Mode sφ + Y Z δ Vectorg Mode + ta + Y Z Z + Y Y Vectorg Mode + ta Y Y Fg.3. The auxlary coordate ( U, V, W Auxlary Coordate Geerator ( U, V, W Auxlary Memory ( U, V, W Graphc Memory (, Y, Z 3-D Vector Iterpolator (, Y, Z ( U, V, W Cotrol Ut Fg.4. The system dagram of 3-D vector terpolator

6 Proceedgs of the 6th WSEAS Iteratoal Coferece o Istrumetato, Measuremet, Crcuts & Systems, Hagzhou, Cha, Aprl 5-7, 7 Reset UVW: ot ready Memory_UVW_Wrte: ot ready CORDIC_3D: ot ready A B C D UVW: ready Memory_UVW_Wrte: ready UVW : eable CORDIC_3D: dsable Memory_UVW: dsable Memory_YZ : eable(read UVW : eable CORDIC_3D: dsable Memory_UVW: eable(wrte Memory_YZ : dsable Address < Memory Sze UVW : dsable CORDIC_3D: eable Memory_UVW: eable(read Memory_YZ : eable(read CORDIC_3D: ready H Address = Memory Sze Memory_YZ_Wrte: ready G F E UVW : dsable CORDIC_3D: dsable Memory_UVW: dsable Memory_YZ : dsable Address = Address + Memory_YZ_Wrte: ot ready UVW : dsable CORDIC_3D: eable Memory_UVW: eable(wrte Memory_YZ : eable(wrte Fg.5. The state dagram of FSM of cotrol ut Fg.6. The layout vew of 3-bt 3-D vector terpolator Fg.7. Vector terpolato (a The orgal mage (b The rotated ad redered mage Fg.8. The mage rotato ad rederg 3-D space Table The Comparso of 3-D rotato wth Eberly, Lag & Atelo ad ths work 3-D Graphcs Rederg Eberly [] Lag & Atelo [9] Euh [] Ths work Coordate system Cartesa Cartesa Polar Polar No. of -D CORDIC 3 5 processor No. of memory bak CORDIC computato(s 3 Auxlary coordate No. No. No. Yes geerator Throughput Low Medum Medum Hgh