74LVX573 Low Voltage Octal Latch with TRI-STATE Outputs

Transcription

1 Low Voltage Octal Latch with TRI-STATE Outputs General Description The LVX573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs The LVX573 is functionally identical to the LVX373 but with inputs and outputs on opposite sides of the package The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems Logic Symbols TL F Features Y Y Y Y IEEE IEC October 1995 Input voltage tralation from 5V to 3V Ideal for low power low noise 3 3V applicatio Available in SOIC JEDEC SOIC EIAJ TSSOP and SSOP packages Guaranteed simultaneous switching noise level and dynamic threshold performance TL F Connection Diagram Pin Assignment for SOIC SSOP and TSSOP TL F Low Voltage Octal Latch with TRI-STATE Outputs Pin Names D 0 D 7 LE OE O 0 O 7 Description Data Inputs Latch Enable Input TRI-STATE Output Enable Input TRI-STATE Latch Outputs SOIC JEDEC SOIC EIAJ SSOP TYPE 1 TSSOP Order Number M SJ MTC MX SJX MSCX MTCX See NS Package Number M20B M20D MSC20 MTC20 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F RRD-B30M115 Printed in U S A

2 Functional Description The LVX573 contai eight D-type latches with TRI-STATE output buffers When the Latch Enable (LE) input is HIGH data on the D n inputs enters the latches In this condition the latches are traparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW traition of LE The TRI-STATE buffers are controlled by the Output Enable (OE) input When OE is LOW the buffers are enabled When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches Truth Table Inputs Outputs OE LE D O n L H H H L H L L L L X O 0 H X X Z H e HIGH Voltage L e LOW Voltage Z e High Impedance X e Immaterial O 0 e Previous O 0 before HIGH-to-LOW traition of Latch Enable Logic Diagram TL F Please note that this diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays 2

3 Absolute Maximum Rating (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specificatio Supply Voltage (V CC ) b0 5V to a7 0V DC Input Diode Current (I IK ) V I eb0 5V b20 ma DC Input Voltage (V I ) b0 5V to 7V DC Output Diode Current (I OK ) V O eb0 5V b20 ma V O e V CC a 0 5V a20 ma DC Output Voltage (V O ) b0 5V to V CC a 0 5V DC Output Source or Sink Current (I O ) g25 ma DC V CC or Ground Current (I CC or I GND ) g75 ma Storage Temperature (T STG ) b65 Ctoa150 C Power Dissipation 180 mw Note The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings The Recommended Operating Conditio table will define the conditio for actual device operation DC Electrical Characteristics Recommended Operating Conditio Supply Voltage (V CC ) Input Voltage (V I ) Output Voltage (V O ) Operating Temperature (T A ) Input Rise and Fall Time (Dt DV) Symbol Parameter V CC T A ea25 C T A e b40 Ctoa85 C Units Min Typ Max Min Max V IH High Level Input V Voltage V IL Low Level Input V Voltage V to 3 6V 0V to 5 5V 0VtoV CC b40 Ctoa85 C 0 V to 100 V Conditio V OH High Level V IN e V IH or V IL I OH eb50 ma Output V I OH eb50 ma Voltage I OH eb4ma V OL Low Level V IN e V IH or V IL I OL e 50 ma Output V I OL e 50 ma Voltage I OL e 4mA I OZ TRI-STATE 3 6 g0 25 g2 5 ma V IN e V IH or V IL Output V OUT e V CC or GND Off-State Current I IN Input 3 6 g0 1 g1 0 ma V IN e 5 5V or GND Leakage Current I CC Quiescent ma V IN e V CC or GND Supply Current 3

4 Noise Characteristics Symbol Parameter V CC (V) T A e 25 C Units C L (pf) Typ Limit V OLP Quiet Output Maximum Dynamic V OL V 50 V OLV Quiet Output Minimum Dynamic V OL 3 3 b0 5 b0 8 V 50 V IHD Minimum High Level Dynamic Input Voltage V 50 V ILD Maximum Low Level Dynamic Input Voltage V 50 Note (Input t r e t f e 3 ) AC Electrical Characteristics Symbol t PLH t PHL t PLH t PHL t PZL t PZH t PLZ t PHZ t W t S t H Parameter Propagation Delay Time D n to O n Propagation Delay Time LE to O n TRI-STATE Output Enable Time V CC (V) g g g0 3 T A ea25 C T A e b40 Ctoa85 C Units Conditio Min Typ Max Min Max C L e 15 pf C L e 50 pf C L e 15 pf C L e 50 pf C L e 15 pf C L e 50 pf C L e 15 pf C L e 50 pf C L e 15 pf R L e 1kX C L e 50 pf R L e 1kX C L e 15 pf R L e 1kX C L e 50 pf R L e 1kX TRI-STATE Output C L e 50 pf R L e 1kX Disable Time 3 3 g C L e 50 pf R L e 1kX LE Pulse Width 3 3 g Setup Time D n to LE 3 3 g Hold Time D n to LE 3 3 g t OSHL Output to Output t OSLH Skew (Note 1) C L e 50 pf Note 1 Parameter guaranteed by design t OSLH e lt PLHm b t PLHnl t OSHL e lt PHLm b t PHLnl 4

5 Capacitance Symbol Parameter T A ea25 C T A eb40 Ctoa85 C Units Min Typ Max Min Max C IN Input Capacitance pf C OUT Output Capacitance 6 pf C PD Power Dissipation Capacitance (Note 1) 27 pf Note 1 C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load Average operating current can be obtained by the equation I CC(opr ) e C PD c V CC c f IN a I CC 8 (per latch) 5

6 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows TL F Physical Dimeio inches (millimeters) 20-Lead Small Outline Integrated Circuit (M) Order Number M or MX NS Package Number M20B 6

7 Physical Dimeio inches (millimeters) (Continued) 20-Lead Small Outline Package EIAJ SOIC (SJ) Order Number SJ or SJX NS Package Number M20D All dimeio in millimeters 20-Lead Plastic EIAJ SSOP Type I (MSC) Order Number MSCX NS Package Number MSC20 7

8 Low Voltage Octal Latch with TRI-STATE Outputs Physical Dimeio inches (millimeters) (Continued) 20-Lead Thin Shrink Small Outline Package JEDEC Order Number MTC or MTCX NS Package Number MTC20 LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with itructio for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2 c com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Fran ais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any respoibility for use of any circuitry described no circuit patent licees are implied and National reserves the right at any time without notice to change said circuitry and specificatio