Quantifying the Sub-optimality of Non-preemptive Real-time Scheduling

Transcription

1 Quanfyng he ub-opmaly of Non-preempve Real-me chedulng Abhlash Thekklakal, Radu Dobrn and askumar Punnekka Mälardalen Real-Tme Research Cener, Mälardalen Unversy, weden {abhlash.hekklakal, radu.dobrn, Absrac A number of preempve real-me schedulng algorhms, such as Earles Deadlne Frs (EDF), are known o be opmal on un-processor sysems under specfed assumpons. However, no un-processor opmal algorhm exss under he non-preempve schedulng paradgm. Hence preempve schemes srcly domnae non-preempve schemes wh respec o un-processor feasbly. However, he goodness of non-preempve schemes, compared o un-processor opmal preempve schedulng schemes such as EDF, whch can also be referred o as s sub-opmaly, has no been fully nvesgaed ye. In hs paper, we apply resource augmenaon, specfcally processor speed-up, o quanfy he sub-opmaly of non-preempve schedulng wh respec o EDF, and apply he resuls o guaranee user specfed upper-bounds on he preempon relaed schedulng coss. In parcular, we derve an upper bound on he mnmum processor speed-up requred o guaranee he non-preempve feasbly of asks ha are deemed feasble under he preempve EDF, and we prove ha, n he cases where, for all asks n he ask se, he larges execuon requremen s no greaer han he shores deadlne, hs bound s equal o 4. We also show how he proposed approach enables a sysem desgner o choose an opmal processor, n order o, e.g., guaranee specfed upperbounds on he preempon relaed overheads. I. INTRODUCTION Over he pas decades, real-me schedulng heory has maured o a pon where a farly large se of fundamenal quesons regardng preempve un-processor schedulng have been addressed. A major par of he research n hs doman deals wh schedulably analyss [] [2] [3] and feasbly analyss [4] [5] [6] [7] of hard real-me perodc and sporadc asks under a preempve schedulng scheme. However, non-preempve schedulng [8] [9] has been less nvesgaed compared o preempve schedulng [0], and especally he feasbly of non-preempve schedulng has receved relavely less aenon snce he work by Jeffay e al. []. Whle here exss ulzaon based ess for schedulably and feasbly of preempve real-me asks under varous assumpons [], no such es exss for nonpreempve schedulng even under resrcve assumpons. Under un-processor schedulng, EDF s known o be opmal [4], whle Fxed Prory chedulng (FP) scheme s no opmal []. Consequenly, prevous works have manly focused on fndng he goodness or sub-opmaly of FP wh respec o an opmal schedulng scheme, (e.g., EDF), under preempve and non-preempve schedulng usng resource augmenaon [2] [3] [4]. However, o our knowledge, no smlar effors have been made owards quanfyng he sub-opmaly of non-preempve schedulng wh respec o preempve schedulng, n spe of he fac ha preempve real-me schedulng srcly domnaes nonpreempve schedulng wh respec o feasbly [7]. Invesgang he sub-opmaly of non-preempve schedulng wh respec o preempve schedulng may also provde sgnfcan nsghs no he developmen of a ulzaon based es for non-preempve schedulng. Noe ha, n he res of he paper, whenever we refer o EDF, we mean preempve EDF, and we consder non-preempve schedulng paradgms under a non-dlng scheme. An mporan facor ha nfluences he feasbly of a ask se n modern real-me sysems, where hardware feaures such as caches, nfluence he ask execuons, s he number of preempons, as well as he pons a whch hese preempons occur [5]. Consequenly, varous mehods were proposed o conrol he preempve behavor of real-me sysems, a dealed survey of whch can be found n [6]. The feasbly analyss of real-me asks [6] [5] assumes neglgble preempon relaed overheads. On he oher hand, whenever hese preempon relaed overheads are no assumed o be neglgble, hey are eher ypcally accouned for n he wors case execuon mes (WCET) of he asks or n he schedulably analyss (e.g., [7] [8] [9] [20] [2] [22] [23]). Burns [24] nroduced he noon of cooperave schedulng, where preempons occur a predefned pons n he code, and proposed a schedulably analyss for. Baruah and Berogna nroduced he lmed preempon echnque called he floang non-preempve regon schedulng (f-npr) [7] [25], whch dsables preempons for a bounded perod of me whou compromsng he feasbly of he ask se. A majory of he modern processors suppor Dynamc Volage and Frequency calng (DVF) usng whch he asks WCET can be manpulaed by changng he CPU frequency. Consequenly, here exss a possbly o speedup he processor o conrol he lenghs of he larges nonpreempve regons of he asks o ensure ha hey are large enough o guaranee a specfed preempon behavor n he schedule. Augmenng he scheduler wh a faser processor provdes us wh he possbly of guaraneeng he feasbly of a specfed non-preempon behavor ha mnmzes he preempon relaed overheads, and hence broaden he se of feasble ask ses. Resource augmena-

2 on was frs nroduced by Kalyanasundaram e al. [26], showng ha faser processors can acheve he same effec as clarvoyance. In an earler work [27], we bounded he cos of non-clarvoyance whle feasbly schedulng a se of real-me asks under an error burs of known upperbounded lengh. Davs e al. [2] [3] [4] derved he upper and lower bounds on he processor speed-up requred for a fxed prory scheduler o schedule all he ask ses scheduled by an opmal schedulng algorhm, leveragng on he opmaly of EDF. In her work, he goodness or sub-opmaly of FP wh respec o an opmal schedulng algorhm such as EDF, s quanfed by he processor speedup requred o guaranee he FP schedulably of he se of all feasble asks ha are schedulable by he opmal algorhm. In hs paper, we examne he consequences of ncreasng he amoun of resources, specfcally speedng up he processor, on he preempon behavor of any gven ask se. We derve he resource augmenaon bound, specfcally he upper-bound on he processor speed-up, ha guaranees he feasbly of a user specfed non-preempon behavor of real-me asks. Consequenly, we calculae he upper-bound on he processor speed-up ha guaranees he feasbly of a fully non-preempve schedule, hence quanfyng he subopmaly of non-preempve schedulng. Addonally, we use he derved resource augmenaon bound o acheve effcen preempon relaed cos conrol by guaraneeng a non-preempon behavor ha mnmzes he preempon overheads. The man conrbuons of he paper are wo fold: ) We show ha he upper-bound on he processor speedup ha guaranees a fully non-preempve schedule for a ask se s gven by 4Cmax, where C max s he larges execuon requremen n he ask se. Hence, f a feasble schedule exss for a ask se on a sngle processor, non-preempve EDF can schedule f gven a processor ha s 4Cmax mes faser. 2) We presen a sensvy analyss based mehod o mnmze he preempon relaed overheads. The res of he paper s organzed as follows: secon II deals he sysem model and he varous noaons used hroughou hs paper. We recall some key resuls abou feasbly of preempve and non-preempve real-me schedulng n secon III and revse hem by ncludng he processor speed. We presen our man conrbuon, he resource augmenaon bound for non-preempve real-me schedulng, n secon IV. We hen buld on he heory presened n secon IV o derve a mehodology for mnmzng he preempon overheads usng processor speed-up n secon V. The wo seps of he mehod are presened n secons V-A and V-B, followed by an example n secon V-C. We presen a dscusson n secon VI on why he requred opmal speedup does no need o be as hgh as ndcaed by he bounds, followed by conclusons n secon VII. II. YTEM MODEL In hs secon, we nroduce he noaons used n he res of he paper whls descrbng he ask model, schedulng model, and he execuon me model. A. Task model We consder a se of sporadc real-me asks Γ= {τ, τ 2,...τ n }, where each τ s characerzed by a mnmum ner-arrval me T, a wors case execuon me, C a processor speed, and a relave deadlne, D. We assume ha he asks are ordered accordng o he ncreasng order of her deadlnes, whch means ha = D. We assume ha every ask τ has m opmal preempon pons [28] whn s execuon, where he m h pon denoes he end of he ask execuon. Le q,j, j =...m denoe he lengh of he ask execuon of τ up o s j h opmal preempon pon on a processor a speed, from he sar of s execuon. In order o focus on he heorecal consequence of resource augmenaon on he preempon behavor of he ask se, and for he sake of clary of presenaon, we assume neglgble preempon relaed overheads a hese opmal preempon pons. However such an assumpon does no affec he generaly of our resuls because he preempon relaed overheads can be accouned durng he placemen of he preempon pons e.g., as done by [28]. Le β denoe he blockng olerance of τ, whch s he larges me for whch τ can be blocked whou causng any deadlne mss. Also, le B β denoe he larges me for whch τ s effecvely blocked a run-me. LCM denoes he Leas Common Mulple of he me perods of all he asks n he se. The ulzaon U of a ask τ execung on a processor a speed s defned as U = C T and he ulzaon of he enre ask se s gven by U = n = U. The demand bound funcon of a ask τ, on a processor of speed, durng a me nerval [0, ) s gven by [5], ( ) DBF D () = max 0, + C For example, DBF () denoes he cumulave processor me requesed by τ durng a me nerval [0, ) on a processor of speed =. B. chedulng Model In our schedulng model we assume ha, whenever a hgher prory ask s released durng he execuon of a lower prory ask τ, nsead of mmedaely preempng τ he scheduler blocks he hgher prory ask for Q me uns on a processor of speed. Here, Q s he lengh of he larges non-preempve regon of τ derved from he ask arbues [7] [25]. Ths ype of scheduler s referred o as an f-npr scheduler [29] (f-npr sands for Floang Non- Preempve Regons). Consequenly, he maxmum number T

3 of mes he ask τ can be preemped when a processor of C speed s used, s gven by. Q We assume a work conservng scheduler,.e., he scheduler does no dle he processor when here are acve asks awang he processor. I s known ha EDF s opmal under a work conservng unprocessor schedulng scheme under boh preempve and non-preempve paradgms [4] []. We leverage on he opmaly of EDF o sudy he processor speed-up requred o guaranee he feasbly of a requred non-preempve behavor for real-me asks. C. Execuon Tme Model In hs paper we are focusng manly on he heorecal consequences of resource augmenaon, specfcally processor speed-up, on he preempon behavor of real-me asks, and hence we assume a lnear relaonshp beween execuon me and processor speed e.g., as assumed by Kalyanasundaram e al. [26] and Davs e al. [2]. However, hs assumpon can be easly relaxed by, e.g., paronng he execuon requremen no processor speed dependen and processor speed ndependen pars [30], on whch we furher elaborae n a echncal repor [3]. To ease he readably, and whou loss of generaly, we assume ha he ask se s nally execung on a processor of speed =. We assume ha, f C s he execuon me a speed =, he ask execuon me of τ scales lnearly as follows: C = C Conversely, he speed requred o oban an execuon me of C s gven by: = C C Ths model also allows us o use processor speed-up facors and processor speeds nerchangeably. Changng he processor speed from = o = a, s equvalen o speedng up he processor by a facor of a. III. FEAIBILITY ANALYI OF REAL-TIME YTEM Lmed preempon models are bascally generalzaons of non-preempve and preempve schedulng models as hey can smulae a preempve behavor rangng from nonpreempve o a fully preempve schedule by seng he non-preempon parameers appropraely. The floang Non- Preempve model (f-npr model) [7] [25] can be seen as a general schedulng model,.e., f Q s se equal o 0 for all τ, he sysem smulaes a fully preempve model, whle f Q s se equal o C, he sysem smulaes a fully nonpreempve model [29]. In our approach we buld on he f- NPR schedulng paradgm o sudy he feasbly of preempve, non-preempve, and lmed preempve schedulng of real-me asks, by varyng he lengh of he non-preempve regons of asks by processor speed varaons. Le us now recall some prevously publshed heorecal resuls on he feasbly of real-me asks on a unprocessor, and revse hem by ncludng he processor speed. Due o he susanably of EDF schedulng algorhm [32], he followng heorems can be generalzed o a processor of speed ( ). A real-me ask se s feasble f he cumulave processor me requesed by he se of asks durng any me nerval does no exceed he sze of ha me nerval [5]. The followng heorem deermnes he feasbly of unprocessor schedulng based on he blockng olerance (β ) of he asks. Theorem III.. [7] [25] A ask se s feasble on a speed processor, f and only f, [, n], where, β s gven by β = mn D <D + β 0 n DBFj () = kt j + D j, k N, j [, n] In he above heorem, D n+ s se as Where, P = max D n+ = mn (LCM, P ) { n = D, D 2,..., D n, (T D )U U When he β = 0, [, n], he ask se s schedulable only under a fully preempve schedulng scheme. The above heorem can be used o deermne he feasbly of lmed preempon schedulng on a processor a speed and s saed by he followng heorem. Theorem III.2. [7] [25] [28] A ask se s feasble under lmed preempve schedulng on a speed processor f, [, n], B β where β s gven by β = mn D <D + ( ) n DBF () = = kt j + D j, k N, j [, n] and B s he larges blockng acually experenced by τ due o he lmed preempons on a processor of speed. The bound Q k on he lengh of he non-preempve regon of a ask τ k on a processor of speed s gven by he followng heorem. }

4 Theorem III.3. [28] A ask se s feasble under lmed preempve schedulng on a speed processor f, k [, n], Q k = mn <k β The ask can execue enrely non-preempvely f Q k s greaer han s execuon me Ck. We can use he above heorem o sae he non-preempve feasbly of he ask se,.e., wheher s possble o fnd a non-preempve schedule, as follows: Theorem III.4. [] [7] [28] A ask se s feasble under non-preempve schedulng on a speed processor f, k [, n], C k Q k IV. QUANTIFYING THE UB-OPTIMALITY OF NON-PREEMPTIVE CHEDULING In hs secon, we derve he resource augmenaon bound ha guaranees he feasbly of a specfed non-preempon behavor of a gven se of real-me asks by examnng he consequences of havng a faser processor on he preempve behavor of real-me ask ses. An llusraon of he man conrbuons of hs secon, ha shows he consequences of havng a faser processor on he preempon behavor of real-me ask ses, s presened n Fgure. We refer o he fgure as he feasbly bucke for real-me ask ses under processor speed varaons. The mouh of he bucke, where he radus of he cross-secon s he larges, denoes he se of all ask ses feasble on a processor of speed = (.e., all un-processor feasble ask ses). The deph of he bucke whch s equal o 4Cmax, gves he processor speedup requred o guaranee a fully non-preempve schedule for any un-processor feasble ask se. Hence, he base of he bucke, where he radus s he smalles, ndcaes he se of all non-preempve feasble ask ses. Each crosssecon of he bucke ndcaes he se of all ask ses feasble under a lmed preempon behavor, guaraneed a he correspondng processor speed (gven by he deph of he cross-secon from he mouh of he bucke). Hence, 4L on ncreasng he processor speed o, every ask n a un-processor feasble ask se can be guaraneed a nonpreempve execuon for a duraon of a leas L uns, fnally becomng feasble under a fully non-preempve scheme a speed = 4Cmax. In he followng, we nroduce some defnons before dervng he resource augmenaon bound ha guaranees a fully non-preempve schedule. Defnon. A non-preempon requremen on a ask τ s defned as he lower bound on he maxmum lengh of he floang NPR of τ, ha, for example, guaranees a user defned upper-bound on he preempon relaed cos on τ. We denoe he non-preempon requremen on a ask τ a speed by L. A non-preempon requremen can also be denoed by n case does no change wh he processor speed. The feasbly of a specfed nonpreempon requremen for every ask τ guaranees he feasbly of a specfed non-preempon behavor for he ask se. Defnon 2. The feasbly of a specfed non-preempon behavor of a ask se s defned as he exsence of a realme schedule ha guaranees he non-preempve execuon of every ask for a user specfed non-preempon requremen, whle ensurng he absence of deadlne msses n he schedule. The feasbly of he specfed non-preempon behavor of he ask se can be ensured by speedng up he processor o conrol he lengh of he non-preempve regons. In our approach, we assume ha durng any arbrary me nerval, he processor s busy execung only he hgher prory jobs. We hen derve he upper-bound on he mnmum ncrease n he processor speed ha guaranees he feasbly of a specfed non-preempon requremen durng ha me nerval. Ths gves us he upper-bound on he mnmum ncrease n he processor speed ha guaranees he exsence of a non-preempve schedule, hereby allowng us o quanfy he sub-opmaly of non-preempve schedulng wh respec o an opmal schedulng scheme. Le us now derve he processor speed ha guaranees he feasbly of a non-preempon requremen for a ask τ. Theorem IV.. The processor speed ha guaranees he feasbly of a non-preempon requremen for a ask τ s gven by { n DBF j () } = max D <D Proof: The lengh of he non-preempve regon for τ a speed s gven by [7], n Q = mn D <D DBFj () Q n DBFj (),, D < D Our am s o fnd he processor speed ha guaranees he feasbly of a non-preempon requremen. Thus, n DBF j (),, D < D olvng for, we ge { n DBF j () },, D < D

5 (slower) Γ p Processor peed Γ l (faser) Γ n Γ p : e of all un-processor feasble ask ses Γ n : e of all ask ses ha are non-preempve feasble on a unprocessor Γ l : e of all ask ses where every ask s guaraneed a non-preempve execuon of lengh L Fgure. The feasbly bucke of real-me asks under processor speed varaons.e., = max D <D { n DBF j () } Corollary IV.. The opmal processor speed op ha guaranees he feasbly of a non-preempon requremen for a ask τ s gven by op = max( ) Consequenly, we fnd he upper-bound on he requred processor speed ha guaranees a specfed non-preempon requremen for any ask τ. Lemma IV.. The speed ha guaranees he feasbly of a non-preempon requremen for any ask τ, durng a me nerval s upper-bounded by where, y = [D, D ). y y Proof: In order o ensure a specfed non-preempon requremen, he oal processor demand durng any me nerval mus be decreased such ha a slack wh a lengh of a mos s generaed: n n DBFj () DBF j () olvng for gves, n DBF j () n DBF j () n The maxmum value of DBF j () on a processor a speed s, snce we assume ha he ask se s feasble under a preempve scheme. ubsung for n DBF j () =, we ge: And, fnally, subsung y =, y y We derve he upper-bound on he requred processor speed ha guaranees he feasbly of a non-preempon requremen, for any τ, durng any me nerval when s no greaer 2. Lemma IV.2. The speed ha guaranees he feasbly of a non-preempon requremen for any ask τ s upperbounded by 2, f 2, [D, D ). Proof: Evaluang he lm of he equaon n lemma IV. a y = 2, we ge, = 2 Evaluang he lm usng l Hopal s rule as y ends o nfny ( ), we ge, = For any value of y [2, ], 2 We now fnd he upper-bound on he requred processor speed ha guaranees he feasbly of a non-preempon requremen for any τ when < 2 n any me nerval. Lemma IV.3. The speed ha guaranees he feasbly of a non-preempon requremen for any ask τ s upperbounded by 4, f < 2 [D, D ).

6 Proof: nce < 2, we have and < 2. Le us now ncrease he processor speed by a facor of 2. We effecvely have = 2 clock cks n he me nerval on a processor of speed 2. Thus, 2 snce < 2. By usng lemma IV.2, he speed-up requred o guaranee he non-preempon requremen for he ncreased processor speed s upper-bounded by 2. As ha we have already ncreased he processor speed by a facor of 2, he upper-bound on he processor speed ha guaranees he nonpreempon requremen for he case < 2 s 4. Lemma IV.4. The speed ha guaranees he feasbly of a non-preempon requremen for any ask τ s upperbounded by 4L, f 0 < <, [D, D ). Proof: In hs case we know ha <. Le us now assume an ncrease n he processor speed o = L. The number of avalable clock cks n he me nerval ncreases from o = L =. We hus oban, =. Ths s a specal case of lemma IV.3, and hence he speed-up requred o guaranee he non-preempon requremen of τ s, 4 nce we had already ncreased he processor speed by L, he upper-bound on he acual speed s: 4 Hence, we oban he upper-bound on he mnmum processor speed ha guaranees a non-preempon requremen for any ask τ n he general case when > 0. Theorem IV.2. The speed ha guaranees he feasbly of a non-preempon requremen for any ask τ s upperbounded by 4L, [D, D ). Proof: In he general case, s bounded by he maxmum of he execuon mes of he asks a speed = (.e., for s non-preempve execuon) n he ask se, and by he shores deadlne and hence > 0. I follows from lemmas IV.2, IV.3, and IV.4 ha he speedup requred n he general case s 4L. When 2, we oban 4 = 4 2 = 2 and when L < 2, we oban 4 = 4 = 4, and when 0 < L < he speed-up requred s 4L. Thus, for any > 0, he speed-up requred s 4L. Corollary IV.2. The speed ha guaranees he feasbly of a non-preempon requremen for any ask τ s upperbounded by 4 4L. Ths s sraghforward as he value of ha maxmzes, [D, D ), s he smalles value of gven by he shores relave deadlne = (remember ha = D ). Hence, we have derved he upper-bound on he processor speed ha guaranees he feasbly of a specfed non-preempon behavor for any ask se Γ. We use hs upper-bound laer n secon V-B o fnd he exac processor speed-up ha guaranees a specfed preempon behavor o conrol he preempon relaed coss. Le us now derve he processor speed-up requred o guaranee he exsence of a non-preempve schedule for any ask se Γ. Corollary IV.3. The speed ha guaranees he feasbly of he non-preempve execuon of τ s upper-bounded by 4C. Ths s easly seen from heorem IV.2 by subsung = C and usng he smalles value of, whch s he shores deadlne. Moreover, Baruah [7] derved he feasbly of lmed preempon schedulng by buldng on he opmaly of EDF schedulng and we have derved he resource augmenaon bounds based on he feasbly of lmed preempon schedulng. Corollary IV.4. The speed ha guaranees he feasbly of a non-preempve execuon of all he asks n he ask se s upper-bounded by 4Cmax, where C max = max(c ) τ Γ. The lmed-preempve execuons of he asks are ndependen of each oher [7]. Hence, he processor speed-up ha guaranees he non-preempve execuon of he ask wh he larges execuon me, wll also guaranee he nonpreempve execuon of all oher asks. In hs secon, we have examned he consequences of havng a faser processor on he preempon behavor of realme ask ses, as llusraed by he feasbly bucke n Fgure. The sub-opmaly of non-preempve schedulng wh respec o an opmal un-processor preempve schedulng scheme for any ask se Γ can be quanfed by he resource augmenaon bound 4Cmax where C max = max(c ) τ Γ. V. BOUNDING THE PREEMPTION RELATED OVERHEAD Preempons can nroduce unpredcable overheads n he schedule [5], and hence mnmzng/conrollng hem s essenal o provde real-me guaranees. However, hs s a challengng ask manly due o he crcular dependency of he preempon behavor on he ask execuon mes [7] [28] [33]. The preempon overheads manly depend on he number of preempons as well as he pons a whch hese preempons occur. Consequenly, by conrollng he maxmum lenghs of he floang NPRs, he number of preempons can be reduced and/or he preempon pons can be placed a opmal locaons wh respec o he preempon coss. Whle n he prevous secon we derved he upper-bound on he requred processor speed-up ha

7 guaranees he feasbly of a user specfed non-preempon behavor, n hs secon we apply hs bound o reduce he preempon relaed coss n he schedule. We propose an approach o frs ranslae he requremens of mnmzng he preempon relaed overheads no a se of ask level non-preempon requremens,.e., a lower bound on he maxmum lengh of he floang NPR for each ask (secon V-A). Then, n secon V-B we calculae he requred processor speed-up ha guaranees he feasbly of he derved non-preempon requremen by usng a bnary search based sensvy analyss mehod ha explos he bound derved n secon IV. Defnon 3. The opmal processor speed op ha guaranees he feasbly of a specfed non-preempon behavor s defned as op = mn(), where he se of avalable processor speeds such ha, τ n Γ, Q op L op Here, L op s he specfed lengh of he non-preempve regon for τ (s non-preempon requremen) ha guaranees he feasbly of a specfed non-preempon behavor per τ. If, for any ask τ, Q does no guaranee he specfed upper-bound on he number of preempons, we can derve he non-preempon requremen L ha guaranees he specfed bound. We can hen calculae he speed-up requred o guaranee he feasbly of he non-preempon requremen L, whch wll n urn guaranee he specfed upper-bounds on he preempon relaed coss. Opmal preempon pons ep ep 2 Dervaon of non-preempon requremens e of ask level non-preempon requremens ensvy analyss Mnmum processor speed ha guaranees he non-preempon requremens Fgure 2. Mehodology overvew Preempon reducon consrans Task arbues Mehodology Overvew: Our approach s performed n wo seps as gven n Fgure 2: ep : Translae he requremens of meeng he specfed upper-bounds on preempon relaed overheads, e.g., mnmze hem, no a se of ask level non-preempon requremens. ep 2: Perform sensvy analyss usng he ask parameers and he non-preempon requremens o derve he opmal processor speed ha guaranees he desred non-preempon behavor. In he followng sub-secons we descrbe each of he seps n deal, followed by an example. A. Dervng Task-level Non-preempon Requremens In he followng, we oulne he frs sep n our approach.e., he ranslaon of he requremens on mnmzng he preempon coss no specfed non-preempon requremens for each ask. Our ulmae am s o fnd he opmal processor speed ha wll guaranee ha he maxmum lengh of he floang NPR per ask a ha speed s greaer han or equal o he non-preempon requremen derved below.. Reducng he number of preempons: The maxmum number of mes a ask τ, characerzed by a floang NPR of maxmum lengh Q, can be preemped whle execung on a speed processor s gven by [7] [29]: C Q Therefore, he non-preempon requremen L, τ Γ, on a speed processor, ha guaranees a mos p preempons on τ, s gven by: L C p + L = C p + Noe ha Q s he acual lengh of he non-preempve regon of τ a speed,.e., gven by he orgnal ask arbues, and L s he lower bound on he lenghs of he floang NPR of τ ha wll guaranee no more han p preempons per τ. When p = 0, he ask τ execues non-preempvely. I s evden ha, on a speed processor, f Q < L, where L s calculaed accordng o equaon, τ can be guaraneed o ncur no more han p preempons. Hence, we have o fnd a processor speed whch ensures ha: C Q L = p +. Enablng preempons a opmal preempon pons: The possbly of enforcng preempons only a opmal preempon pons [28] depends on he maxmum lengh of he floang NPRs on a processor of a gven speed. Remember ha q,j denoes he lengh of execuon of τ up o s j h opmal preempon pon on a speed processor. Hence, he non-preempon requremen for a ask τ s gven by he larges nerval beween any wo consecuve opmal preempon pons of τ when execues on a speed processor: L () = max j<m (q,j+ q,j, q,) (2)

8 Consequenly, our goal s o fnd he processor speed ha sasfes: Q L = max j<m (q,j+ q,j, q,) By selecng he non-preempon requremen as he maxmum of he lenghs calculaed usng equaons and 2, we can boh guaranee he requremens of reducng he number of preempons as well as rean he possbly of preempon placemen a opmal preempon pons. B. ensvy Analyss for Preempon Conrol In mos suaons, changng he processor speed may also change he requremen on he maxmum lengh of he floang NPR o sasfy he desred preempon relaed cos conrol requremens. I also changes he possble maxmum lenghs of he floang NPR of some of he asks n he sysem. Thus, we need o perform a sensvy analyss on he ask se o derve he requred processor speed-up ha guaranees a gven non-preempon requremen. We propose he use of a bnary search based sensvy analyss. The maxmum lengh of he floang NPR of τ s known o be Q a speed (calculaed usng he resuls by [7] [25] and [28]). If Q < L, we need o use a faser processor o ensure ha he maxmum lengh of he floang NPR of τ sasfes he requred non-preempon requremen a ha speed. Remember ha L s he non-preempon requremen ha guaranees a ceran non-preempon behavor for τ on a speed processor. nce we use a bnary search o fnd he opmal speed op, he challenge s o fnd an upper-bound on he processor speed below whch op les. We use he upper-bounds derved n he earler secon. The upper-bound on he processor speed-up ha guaranees a non-preempon requremen of L for any τ on a processor of speed, s gven by: = 4L Thus, he processor speed whch guaranees ha every ask τ can execue for a duraon L non-preempvely s: hgh = max n ( ) However, when we use a faser processor, he execuon mes (C τ ) of all he asks decrease. Ths, n urn, changes he maxmum lenghs of he floang NPRs of he asks. The lowes processor speed ha guaranees he non-preempon requremens les n he nerval [ low =, hgh ]. Remember ha a speed low =, he ask se does no sasfy he specfed non-preempon requremen,.e., Q < L. We can now perform a sensvy analyss on he speeds beween and hgh n order o calculae he lowes processor speed op whch guaranees ha every ask τ can exhb he requred non-preempon behavor. Under our assumpon of a lnear speed-up of ask execuon mes wh he processor speed, can be easly shown ha he maxmum lengh of he floang NPRs ncreases monooncally wh he processor speed. Ths s because, under our assumpons, ncreases wh decrease n he demand bound [7]. Hence he correcness and opmaly of our mehod s gven by he correcness of he bnary search. C. Example We llusrae our mehod usng a smple example. Consder he ask se gven n able I execung on a processor of speed. We assume an execuon me model where he Task C D T Q Max. no. of preempons τ τ τ τ τ Table I EXAMPLE TAK ET (PEED=) ask execuons scale lnearly wh he processor speed. In oher words, f he processor speed s ncreased o 2 from a defaul speed of, he asks execue wce as fas. Accordng o he mehod proposed by [7], he maxmum lengh of he floang NPRs per ask a speed = s gven n able I. A speed =, here are a mos 6 preempons on ask τ 2, 23 preempons on τ 3, 9 preempons on τ 4 and 26 preempons on τ 5. Le us assume ha more han 3 preempons on τ 4 wll lead o a deadlne mss n he schedule. Noe ha he maxmum lengh of he floang NPR of τ 4 s gven by Q 4 = 3, and can only guaranee ha τ 4 s preemped no more han 9 mes. We perform a Task peed ()=3.4 ( op) C Q Max. no. of preempons τ τ τ τ τ Table II THE PREEMPTION BEHAVIOR OF THE TAK ET AT PEED op sensvy analyss, as descrbed n he prevous secon, o fnd he lowes processor speed ha guaranees ha ask τ 4 s preemped no more han hree mes. In hs case, our algorhm gves an oupu of op = 3.4. The lengh of he non-preempve regon of each ask and he number of preempons a hs speed are enumeraed n able II where we can see ha τ 4 s preemped no more han 3 mes. In order o show ha our derved speed s he lowes one whch can guaranee he desred non-preempon behavor, we also calculaed he number of preempons ha he ask se would ncur a a speed less han op. I can be easly seen ha usng a processor of speed = ncreases he number of preempons on τ 4 from 3 o 4.

9 VI. DICUION In secon IV, we presened a unfed resul on how he preempon behavor of a se of real-me asks changes wh he processor speed. We showed n lemmas IV.3 and IV.4, ha he upper-bound on he mnmum processor speed ha guaranees a non-preempon requremen for any ask τ s gven by 4, f < 2, and s equal o 4L, f 0 < <, [D, D ). In some cases, f we consder he nerdependency beween he processor speed and he ask execuons, a gher bound can be obaned, whch ndcaes ha bound on he speed-up requred o guaranee a specfed preempon behavor, n pracce, s even lower (Ths s due o he fac ha n he proof of lemma IV.3 we used he bound derved n lemma IV.2 o derve he bound of 4. mlarly, we used lemma IV.3 o derve he bound 4L for he case 0 < < n lemma IV.4.). These cases are dealed n he observaons VI. and VI.2. However, as dealed n observaon VI.3, for he sake of obanng a unfed resul on he relaonshp beween he processor speed and he preempon behavor of a ask se, we do no negrae hese resuls o our man heorems. Observaon VI.. A gher bound on he speed ha guaranees he feasbly of a specfed non-preempon requremen for any ask τ s gven by 2, f < 2 [D, D ). We know ha < 2 and hus we have and < 2. A speed =, here are clock cks avalable n any me nerval. Thus s evden ha n he wors case, when he processor s fully occuped durng he nerval, compuaons of he non-preempon requremen canno be feasbly execued whn he nerval. Le us assume an ncrease n he processor speed by a facor of 2. Ths mples ha whn an nerval of me, here are n effec = 2 clock cks. In hs case, s clear ha 2 + snce. Thus, a non-preempon requremen can be successfully guaraneed whn whou causng any deadlne mss. Hence, n hs case he gher upper-bound s gven by 2. Observaon VI.2. A gher bound on he speed ha guaranees he feasbly of a non-preempon requremen for any ask τ s gven by 2L, f 0 < < [D, D ). On ncreasng he processor speed o = L, he number of clock cks n he me nerval ncreases from o = L =. Hence we can execue he orgnal compuaons of he demand bound and only compuaons of he non-preempon requremen a speed = L. Ths means ha here wll be a deadlne mss a me. The remanng non-preempon requremen ha canno be execued n he nerval s L =. Thus we have o execue L compuaons of he non-preempon requremen n he me nerval a speed = L. We know ha <, hus a speed = L n effec we ge L = L >. Usng lemma IV.2 and observaon VI. he upper-bound on he speed, denoed by, s 2. nce we had already ncreased he processor speed by L, he gher upper-bound s: 2 Observaon VI.3. The bound on he speed-up requred ha guaranees a non-preempve execuon of τ for a duraon canno be generalzed as 2L, for any > 0, and hence does no gve us a unfed resul on how he preempon behavor of he ask se changes wh he processor speed. Ths s nuve snce, when 2L 2, we ge whch s no he case as shown n lemma IV.2. nce we canno generalze he resul n observaon VI.2, we canno use he resul n observaon VI. n our man heorems for he same reason. However, hey are neresng snce hey ndcae ha he acual bound on he speed-up requred o guaranee he feasbly of a specfed preempon behavor s, n pracce, lower han he heorecally derved one. VII. CONCLUION In hs paper, we have quanfed he sub-opmaly of non-preempve real-me schedulng wh respec o a unprocessor opmal preempve schedulng algorhm e.g., EDF. We have proved ha he speed-up requred o guaranee he non-preempve execuon of any ask τ, for a duraon, s no greaer han 4L, where s he smalles relave deadlne n he ask se. Consequenly, he upper-bound on he mnmum processor speed ha guaranees a fully non-preempve schedule s gven by 4Cmax, where C max s he larges execuon me n he ask se. Our sensvy analyss based mehod derves he opmal processor speed ha guaranees specfed upper-bounds on he preempon relaed coss n he schedule. The mehod empowers a realme sysem desgner o guaranee user specfed bounds on he preempon relaed coss, usng a faser processor, whle mananng schedulably. Ongong effors nclude dervaon of a ulzaon based es for non-preempve schedulng and exensons o mulprocessor sysems. ACKNOWLEDGMENT The auhors would lke o hank Anono Ccche and he anonymous revewers for her useful commens on hs paper. Ths work was parally suppored by he wedsh Research Councl projec CONTEE ( ). REFERENCE [] C. L. Lu and J. W. Layland, chedulng algorhms for mulprogrammng n a hard-real-me envronmen, The Journal of ACM, 973.

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11 VIII. APPENDIX Ths appendx correcs a mnor represenaonal error n he paper, specfcally n Theorem IV.2. In Theorem IV.2, he speed-up bound n gven as, 4 However, he above equaon does no emphasze on he fac ha, nsead of he value gven by L, we should consder he lmng values of L, gven by, 2 f 2 f L < 2 f 0 < < In order o negrae hs nformaon o he heorems, we defne a funcon f(l, ) gven by, 2 f 2 f(l, ) = f L < 2 f 0 < < The speed-up bound n Theorem IV.2 should be: 4f(, ) Therefore, he speed-up bound n Corollary IV.2 should be: 4f(, ) The speed-up bound n Corollary IV.3 should be: 4f(C, ) mlarly, he speed-up bound n Corollary IV.4 should be: 4f(C max, ) Consequenly, he revsed unprocessor feasbly bucke s gven n Fgure 3. (slower) Processor peed (faser) Γ p : e of all un-processor feasble ask ses Γ n : e of all ask ses ha are non-preempve feasble on a unprocessor Fgure 3. 4 f (L, ) 4 f (C max, ) Γ n Γ p Γ l # % 2 % % f (x, ) = $ % 2 x < 2 x % x % & 0 < < x Γ l : e of all ask ses where every ask s guaraneed a non-preempve execuon of lengh L The revsed unprocessor LP-EDF feasbly bucke