CMU Fall VLSI CAD

Transcription

1 CMU Fall VLSI CAD [5 pts] HW 5. Out: Tue Nov 7, Due: Tu. Dec 0, in class. (V). Quadratic Placement [5 pts] Consider tis simple netlist wit fixed pins, wic as placeable objects. All te -point wires ave Cij= except te two wires labeled W in te fiure: x=0.666, y= W W x=0, y=0 x=, y=0 Do tis: Assume W= so all wires ave unit weit, and sow ow to formulate and solve te quadratic placement problem as in te class notes. Sow te [Cij] matrix, te [A] matrix, te two b vectors (one for solvin te x problem, one for te y problem). Solve te two resultin x matrix problems (owever you want to do it) to et a placement. Plot te placement as in class (you can do it by and, or you can be fancy and use a proram; eiter is OK). Now, assume W=0, and repeat te above placement exercise, aain sowin all te matrices, vectors, and final placement. CMU Fall VLSI CAD November 5, 00

2 . Static Timin Analysis: Computation [5 pts] Consider te simple circuit below. Do te followin: Assume eac ate as delay equal to te number of its inputs, i.e., te inverters ave delay=, te NANDs ave delay=. Inore te wires for delay. Draw te full delay rap wit one source and one sink node. Wat te fastest cycle time we could use if tis was te loic we ad between latc staes in our desin? Sow ow you computed tis. Usin tis cycle time number, sow te Arrival Time (AT(node)) and Required Arrival Time (RAT(node)) times for eac node in your rap. Use te aloritms from te class notes: you can do te topoloical sorts by eye, ten use tese to enerate te AT and RAT numbers. Don t worry about early mode and late mode delays; just use te sinle delay per ate ( delay = te number of ate inputs ). Given te AT and RAT numbers, sow te slacks at eac node too. Is te lonest pat statically sensitizable? Explain wy or wy not. A B C D 5 8 E F 6 CMU Fall VLSI CAD November 5, 00

3 . Basic Maze-Routin Aloritms [5 pts] Consider te simple -point maze-routin problem sown below. All te unblocked cells are wite, and for convenience are labeled wit a sinle letter in te lower left corner so we can refer to tem later. Assume cells ave unit cost unless tey are labeled wit a number in te lower rit corner (e.., cells f, j). Black cells are blockaes. a b c d e f T S i j k l m n p Cells witout a number ave cost= Answer tese questions: Suppose we use te plain vanilla maze routin sceme (no predictor function) to route from te source S cell to te taret T cell in tis rid. Assume tat wen a cell is removed from te wavefront (expanded) and used to reac its neibors, you look at (i.e., reac) te neibor cells in tis compass order: Nort, East, Sout, West. Assume also tat reaced cells added to te wavefront wit te same cost are stored in a queue: first in is first out. Redraw te rid twice, and in one drawin label te cells in te order tey are reaced (added to te wavefront); in te oter drawin label te order in wic cells are expanded. Also sow te final pat and tell its cost. To be clear ere: you start wit just cell i on te wavefront wit cost=. You expand i, and you reac first f, and ten j, and ten m, ten, in order. f as cost=, all oters ave cost=. Tese cells o on te wavefront in order f, j, m,. Given te queue structure of te wavefront, te next cell to expand is j, since it s te first cell of cost= on te wavefront. Continue from ere... Suppose instead tat we use a dept-first predictor sceme? Assume te same Rubin sceme as discussed in class. Assume te order for reacin neibors is te same order as above. Recall: eac cell now as a patcost, and a distance-to-taret (estimated) cost. Answer te same questions for te last part for tis new searc sceme. Aain, to be clear. Cell i is te first one on te wavefront wit patcost= and estimated distance-to-taret =. So, cell i is on te wavefront wit total cost = 4. You reac te neibor cells in tis order: f, j, m,. f as patcost = and distance-to-taret =, so f oes on te wavefront at total cost = 5. j as patcost=, and distance-to-taret =, so j oes on te wavefront at total cost = 4. Similarly, m and end up on te wavefront eac at a total cost of +4=6. Continue from ere... CMU Fall VLSI CAD November 5, 00

4 4. Elmore Delay for a Parameterized Clock Tree [5 pts] Consider te symmetric clock tree layout sown below. It as 7 sements wit fixed lent, wit of tese avin variable widt. It as 4 leaf nodes. Now assume tat te resistance and capacitance can be calculated as: R = r L/W, were r=50 x 0 - C = c L W, were c = 0. x 0-5 Assume tat L, W must be in units of microns for te above formulas to work rit. Note tat some lents in te picture are in millimeters. Remember to convert! Suppose we want to make te delay as small as possible ere. One simple way is a monotone widenin sceme: te bottom-most wires are all widt=um, and eac level up te clock tree as wires k times wider tan te level below. Tere are 7 sements in tis clock, but only one desinable variable now: k. Do tis: Wat is te root to leaf delay of tis clock if we just set k=? How fast can we make tis clock run, ie, wat is te minimum Elmore delay τ tat we can acieve if we can set k to any positive number? (k does not ave to be an inteer). How fast can we make tis clock if we limit te maximize widt of te widest wire to 5 um? Suppose we also ave a power limit. To first order, te power in te clock is CV f, were C is te total capacitance of te entire clock (sements + leaf nodes), V is te voltae of te clock sinal (let s call it V to make life easy), and f is te frequency of operation (Hz) of te clock. Let s assume we can approximate f as /τ. How bi can we make f if we ave a total limit of milliwatts dissipated in te clock, i.e., CV f <= 0.00? (Hint: Turn eac sement into a pi model as a function of k, write delay as a function of k, and total capacitance as a function of k. You can solve nonlinear equations rapically by plottin for various values of te variable) L=.5mm, W=um L=.5mm, W=um Resistance of te clock driver is 00 oms. L=5mm, W=k L=.5mm, W=um L=.5mm, W=k L=.5mm, W=k L=.5mm, W=um Capacitive load at eac of te 4 leaf nodes is 0 - F CMU Fall VLSI CAD November 5, 00 4

5 5. Geometric Data Structures [5 pts] Consider tis simple layout, wic as rectanles (labelled a-k) on layers: te dark rey layer, and te liter (it s actually striped) layer: k a b i k j b f e c d f Dots wit letters sow te corners of rectanles tat are idden under anoter rectanle in tis picture, just to avoid any ambiuity Do tis: Draw te quadtree tat represents tis layout. You don t need to try to draw te actual rectanle in eac node of te quadtree, just sow te quadtree s overall structure (quadrants, cut lines, ierarcy) and wat rectanles (by letter) live in eac part of te tree. Explain any assumptions you need to make. Draw te maximally orizontal corner stitced tileplane tat represents tis layout. Assume we want one sinle tileplane, so tat eac tile will be a unique combination of layers. So, we will ave space tiles, dark-rey tiles, striped tiles, and dark-rey-andstriped tiles. Label tins clearly so we can tell wat eac tile is. Draw te rid coordinates as above so we can see were te edes of eac tile fall. Remember te canonical form for te tileplane: solid tiles are maximally wide and ten maximally i; solid tiles cannot ave same-color tiles at teir extreme left/rit ends. In tis case, it s OK to ave anoter solid tile wit a different color, ie, a different set of solid layers inside a orizontally neiborin tile. Explain any assumptions you need to make. CMU Fall VLSI CAD November 5, 00 5