An algorithm to improve the error rate performance of Accumulate-Repeat-Accumulate codes Tae-Ui Kim

Transcription

1 An algorithm to improve the error rate performance of Accumulate-Repeat-Accumulate codes Tae-Ui Kim The Graduate School Yonsei University Department of Electrical and Electronic Engineering

2 An algorithm to improve the error rate performance of Accumulate-Repeat-Accumulate codes Tae-Ui Kim A Thesis Submitted to the Graduate School of Yonsei University in Partial Fulfillment of the Requirements for the Degree of Master of Science Supervised by Professor Hong-Yeop Song, Ph.D. Department of Electrical and Electronic Engineering The Graduate School YONSEI University December 2006

3 This certifies that the thesis of Tae-Ui Kim is approved. Thesis Supervisor: Hong-Yeop Song Jong-Moon Chung Soo-Yong Choi The Graduate School Yonsei University December 2006

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6 Contents List of Figures iv List of Tables v Abstract vi Introduction. Motivation....2 Overview ARA Codes and concepts of EMD 4 2. Protograph and ARA codes Construction of parity check matrix of ARA codes Concepts of EMD Improvement of waterfall and error rate performance in high SNR 5 3. Analysis of cycles of ARA codes Criterions for new connection Proposed algorithm i

7 3.4 Simulation results Concluding Remarks 30 Bibliography 3 Abstract (in Korean) 34 ii

8 List of Figures 2. Rate /3 RA code Rate /2 ARA code Parity check matrix involved in entire encoding process Reducing procedure of parity check matrix Parity check matrix of ARA codes Parity check matrix and bipartite graph description of a (9,3) code Venn diagram for relationship of C d,s d and L d A Cycle with EMD An example of consecutive parity bits cycle set L 4 with EMD An example for union of two L d s with size 7 and EMD An example for self return distance Selection of a parity bit and a check node All parity cycle produced by new edge connection Implementation of encoder for proposed algorithm Summary of proposed algorithm Performance comparison of RA and ARA codes iii

9 3.9 Performance of ARA code () Performance of ARA code (2) iv

10 List of Tables 3. Local girth distribution of two ARA codes Consecutive parity bits cycle set distribution of two ARA codes v

11 ABSTRACT An Algorithm to Improve the Error Rate Performance of Accumulate-Repeat-Accumulate Codes Tae-Ui Kim Department of Electrical and Electronic Eng. The Graduate School Yonsei University Contrary to the low threshold of ARA codes their high error floor does not make the waterfall last for a long range with respect to the error rate. In the thesis we propose an algorithm to keep up the waterfall steeper and improve the error rate performance of ARA codes in high SNR using EMD concepts. The algorithm analyzes the cycles containing some part of the dual diagonal and defines the consecutive parities cycles which consist of one interleaved bit and parity bits. After identifying the consecutive parities cycles of the ARA codes the algorithm supplies additional EMD to the consecutive parities cycles. Applying the proposed algorithm to ARA codes with two different interleavers achieves 0.35dB and 0.5dB gain respectively over AWGN channel with maximum iteration 200 and which only adds 9 and 5 edges for each code. Simulation results show that the proposed algorithm derives an improvement of waterfall and error rate performance in high SNR with little complexity burden to both encoder and decoder vi

12 without loss of performance in low SNR. Key words : Low-Density Parity-Check codes, Accumulate-Repeat-Accumulate Codes, EMD, stopping set, Error floor vii

13 Chapter Introduction. Motivation The codes based on iterative decoding are paid much attention after Berrou et al. introduced the turbo codes in 993. Another codes with iterative decoding, LDPC (Low- Density Parity-Check) codes are devised by Gallager in 963 and Mackay rediscovered the genuine value of LDPC codes [] [2]. Since the rediscovery many types of LDPC codes have been appeared. And the codes with turbo structure which can be decoded by decoding algorithm for LDPC codes have been prosed. RA (Repeat-Accumulate) codes, ARA (Accumulate-Repeat-Accumulate) codes and ARAA (Accumulate-Repeat- Accumulate-Accumulate) codes are the representatives of the codes [3] [4]. They are subclasses of LDPC codes. Since this type of codes consists of accumlators, repetition codes and interleavers they can be constructed based on the protograph which is tiny size of Tanner graph and the threshold can be derived from the protograph. The threshold of these codes is low. Divsalar et al. showed that these codes can provide near Shannon limit performance by the maximum likelihood decoding [5]. ARA codes are concatenated RA codes with rate outer accumulator to RA codes in order to achieve

14 lower threshold than RA codes. ARA codes are known that they have threshold 0.08 db for rate /2 and maximum bit node degree 5 as the block length goes to infinity [3]. However ARA codes have narrow waterfall region with respect to the error rate due to their high error floor even if the codes provide low threshold. Error floor can be improved by increasing the minimum distance. There are some researches to increase the minimum distance by achieving large girth of the graph [6]. In addition a scheme to improve the error floor by avoiding small size of stopping set was also proposed [7]. In this thesis, we analyzed the cycles produced by dual diagonal in the parity check matrix of ARA codes. Then, we propose a scheme to improve waterfall and performance in high SNR of ARA codes by increasing the EMD (Extrinsic Message Degree) of the particular cycles containing some part of the dual diagonal. We show that the proposed scheme is not only too simple to burden the much complexity to both encoder and decoder but also provide improvement of waterfall and performance in high SNR without loss in low SNR.2 Overview In chapter 2, We introduce the protograph codes and ARA codes as its application. After that we explain how to construct a parity check matrix of ARA codes in order to reduce the erasure bits. End of chapter 2 we give some theoretical definitions, theorems and examples which are bases of the proposed scheme. In chapter 3, we analyze the cycles produced by dual diagonal in the parity check matrix of ARA codes. We can find some particular cycles containing part of the dual diagonal which have small EMD. Based on the analysis we propose an algorithm to replenish the cycles with EMD to avoid 2

15 generation of small size of stopping set. It will enlarge the waterfall region and make it steeper and improve the error rate performance of ARA codes in high SNR ultimately. We present the simulation results to verify the proposal at the end of the chapter. Finally chapter 4 summarizes the remarks of the paper and gives some limits of the proposed scheme. 3

16 Chapter 2 ARA Codes and concepts of EMD In this chapter we first introduce ARA codes based on protograph and some basic theory about error floor and performance in hign SNR 2. Protograph and ARA codes Protograph is a Tanner graph with relatively small number of nodes [3]. A protograph consists of a set of variable nodes V, a set of check nodes C and a set of edges E. Each edge e E connects a variable node v e V to a check node c e C. The edges are permuted, so the mappings e (v e,c e ) V C construct an interleaver. One can obtain a larger graph with desired size by copy and permutation of a protograph. The resulting large graph is called derived graph and the corresponding LDPC code is protograph code. As a simple example we consider the protograph shown in Figure 2.a. This protograph code may be recognized as the Tanner graph of LDPC code (N = 3,K =)and give rise to rate /3 RA codes with encoder in Figure 2.b. In Figure 2.a black circles are variables nodes connected to the channel, white circles are erasures not connected to the channel and circles with plus sign are check nodes. 4

17 D (a) Protograph of RA (b) Encoder for RA Figure 2.: Rate /3 RA code D XO OX Rep 3 Rep 3 D OOX (a) Protograph of ARA (b) Encoder for ARA Figure 2.2: Rate /2 ARA code ARA codes are concatenated RA codes with rate outer accumulator having interleaver between them and can be also constructed based on a protograph and corresponding encoder. Figure 2.2 represents rate /2 ARA codes with regular repetition 3 and periodic puncturing pattern OOX, where O indicates the puncturing position. Outer accumulator provides precoding gain to achieve lower threshold than RA codes [3] [5]. But outer accumulator and puncturing for desired rate bring into production of many erasure bits. Protograph 2.2a of ARA code has erasure bits as many as /5 code length but erasure bits more than /5 are produced through the encoding process in real since the encoder adopts puncturing and outer accumulator. Hence the parity check matrix corresponding to protograph does not match to encoder and produced bits. In the next section we will explain how to construct a parity check matrix of ARA codes. 5

18 2.2 Construction of parity check matrix of ARA codes In the thesis we use ARA code in Figure 2.2. Entire encoded bits produced through the encoding process are composed of K information bit, K erased outer accumulator output bits and 3K parity bits of which 2/3 are erased parity bits. Hence the ratio of erasure bits for originally encoded codeword is 3/5. The ratio is very high and that degrades the peformance of the ARA codes. Erasure bits slow down the convergence speed since they pass no message by sum-product algorithm. Therefore we need to reduce the portion of erasure bits. The Figure 2.3 shows that the parity check matrix of ARA codes involved in all the bits produced through the encoding process, where the length of information bit k is 8 and the portion of erasure bits are 3/5. Two dual diagonal represents the inner and outer accumulator repectively. Outer accumulator produces 8 intermediate erasure bits e 0,e,,e 7 and 24 parity bits p 0,p,,p 23 with 8 information bits. Even numbered information bits and odd numbered intermediate erasure bits are repeated 3 times and put into the interleaver. Inner accumulator produces the 24 parity bits with interleaved input bits and transmit the bits indexed by 3k +2,k =0,,, 7. Only 6 bits of 40 bits are transmitted to the channel in total. But we can reconstruct the parity check matrix such that the codewords have small number of erasure bits. Let us see the parity check equations which produce intermediate erasure bits. 6

19 e 0 = k 0 e = e 0 + k e 2 = e + k 2 e 3 = e 2 + k 3. We can rewrite the parity check equations without even numbered punctured intermediate erasure bits as following e = k 0 + k e 3 = e 2 + k 3 = e + k 2 + k 3. These parity check equations give the parity check matrix with small number of intermediate erasure bits. Then we reorder the information bits by column permutations. By the procedures we obtain the reduced parity check matrix of outer accumulate code such as Figure2.4 We can apply these reducing procedure to the inner accumulate code in the same way. Finalizing whole procedure we get the parity check matrix in Figure 2.5 of which size are N = 5 2 K and M = 3 2K where K is the length of information. Now we call this reduced matrix as a parity check matrix of ARA codes and corresponding codeword of length N = 5 2K as a codeword of ARA codes. Note that the length of transmitted codeword is 2K since 2K erased bits are not transmitted. 7

20 k 0 k k 2 k 3 k 4 k 5 k 6 k 7 e 0 e e 2 e 3 e 4 e 5 e 6 e 7 p 0 p 23 p 22 p 2 p 20 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p p 0 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p Figure 2.3: Parity check matrix involved in entire encoding process 8

21 k 0 k k 2 k 3 k 4 k 5 k 6 k 7 e 0 e e 2 e 3 e 4 e 5 e 6 e 7 k k 3 k 5 k 7 k 0 k 2 k 4 k 6 e e 3 e 5 e 7 Figure 2.4: Reducing procedure of parity check matrix Parity check matrix with reduced erasure bits has erasure bits as much as /5 code length while the original parity check matrix has 3/5. The procedure needs a caution. When we carry out the method for the inner accumulate code consecutive three rows are merged in to one row. If a column has two s in these consecutive rows two s are deleted by modulo two sum since the bits corresponding to the column participate in merged check equation twice. To avoid this phenomenon we construct interleaver after reducing the parity check matrix. It doesn t makes the codes lose bit node degree, which may also degrade the performance of the code. ARA codes have interleaver. There are many ways to construct an interleaver such as interleavers for turbo codes. Under belief propagation PEG algorithm provides a graph with comparatively good performance [6]. It is reasonable to construct an interleaver by PEG algorithm since ARA codes are subclasses of LDPC codes. In Figure 2.5 PEG interleaver means that 3 repetition and interleaver are constructed using PEG algorithm from already given graph by protograph. Although parity check matrix and codeword have reduced portion of erasure bits the portion is still high. These erasure bits slow down the speed of convergence and degrade 9

22 d, d 3,3 v c Figure 2.5: Parity check matrix of ARA codes the performance of the iterative decoder. In addition ARA codes have small minimum distance bring into high error floor which let the codes loses their advantages. In the next section we will study the researches concerned in error floor and minimum distance of LDPC codes. 2.3 Concepts of EMD Minimum distance determines the performance of codes at high SNR. Large minimum distance reduces the probability that the decoded codeword satisfies the all check equation but it is not correct codeword. In order to derive the technique which increases minimum distance we introduce some definitions and theorems [7]. Figure 2.6 is an example for the definitions and theorems. The parity check matrix H can be divided by 2 matrices H and H 2. H represents message bits and H 2 represents parity bits. 0

23 v0 v v2 v3 v4 v5 v6 v7 v H H 2 (a) Parity check matrix c 0 c c 2 c 3 c 4 c 5 (b) Bipartite graph Figure 2.6: Parity check matrix and bipartite graph description of a (9,3) code Definition 2. Cycle A cycle of length 2d is a set of d variable nodes and d check nodes connected by edges such that a path exist and the path travels through every node in the set and connects each node to itself without traversing an edge twice. Definition 2.2 Cycle set C d A set of variable nodes in a bipartite graph is a set C d if it has d elements, and one or more cycles are formed between this set and its neighboring check node set. A set of d variable nodes does not form a set C d set only if no cycles exist between these variables and their check neighbors. The maximum cycle length that is possible to exist in a C d is 2d. Figure 2.6 shows a length-6 cycle of a bold line and a length-4 cycle of a dotted line. Note that the variable node set {v 4,v 5,v 6 } is also a set C 3 although v 5 is not contained in the length-4 cycle.

24 Definition 2.3 Stopping set S d A stopping set S d is called a set S d if it has d elements and all its neighbors are connected to it at least twice. Variable nodes set {v 0,v 4,v 6 } in Figure 2.6 is a set S 3 because all its neighbors c 0,c,c 3 and c 5 are connected to this set at least twice. In a bipartite graph without singly connected variable nodes, every stopping set contains cycles. Edges of variable node play a role of leaving from the node and arriving at node. This combination of leaving and arriving makes the cycles. Furthermore in a bipartite graph without singly connected variable nodes, stopping sets are comprised of multiple cycles in general. The only stopping set formed by a single cycle is one that consists of all degree-2 nodes. Definition 2.4 Linearly dependent set L d A variable node set is called an L d set if it is comprised of exactly d elements whose columns are linearly dependent but any subset of these columns is linearly independent, where the columns are column vectors of parity check matrix H corresponding to variables in L d. Variable node set {v 0,v 4,v 6 } in Figure 2.6 is an L 3 set. The N tuple vector with d s at positions corresponding to the variable nodes in L d and 0 at other positions satisfies all the parity check equations by the definition of L d. Hence a code with minimum distance d min has at least one L dmin because the variable nodes in the set are identical to the positions at which the minimum distance codewords have s. But L d with d<d min cannot exist since there is no codeword with hamming weight less than d min. Next theorem gives the relationships between L d s and S d s. 2

25 C d d S L d Figure 2.7: Venn diagram for relationship of C d,s d and L d Theorem 2. A set of variable nodes which form a set L d must form S d. Proof: The binary sum of all columns corresponding to the variable nodes in L d is the all-zero vector. Thus any neighbor of an L d is connected by the variable nodes in the set even number of times, that means at least twice. Theorem 2. implies that preventing small size of stopping set also prevents small d min. Since L dmin always forms S dmin a code with minimum distance d min always have L dmin and S dmin. Therefore, if we forbid a code to have all stopping sets S d for d t we can assure ourselves that the minimum distance d min of the code will be larger than t. However the converse is not true. Even if the small stopping set S d with d<texists minimum distance d min can be larger than t. Figure 2.7 shows the relationship between C d, S d and L d. Di, et al [8] showed that after we decode the received word in an iterative fashion until either the codeword has been recovered or until the decoder fails to progress further, a set of variable nodes left as erased is exactly equal to the maximum size stopping set that is a subset of originally erased symbol by the channel. The role of the stopping set under belief propagation is applicable to ARA codes since the codes contains erasure bits 3

26 in general. Even if the codes does not contain erasure bits it makes the theory applicable that the received bits with very small reliability can be considered as erasure bits. As we have known that preventing small size of stopping set also prevent small d min our purpose is to increase size of stopping set. Now we are going to present another definition to obtain a large size of stopping set. Definition 2.5 Extrinsic message degree (EMD) An extrinsic constraint node of a variable node set is a constraint node that is singly connected to this set. The EMD of a variable node set is the number of extrinsic constraint nodes of this variable node set. The EMD of stopping set is zero since every constraint nodes of variable nodes in the stopping set are connected to the set. A set of variable nodes with large EMD it will require more additional closure constraint nodes to be a stopping set. Therefore it will result in increased minimum distance that we make a set of variable nodes have large EMD. Figure 2.8 shows a cycle with EMD 2. The set requires additional variable nodes so that it may be a stopping set. Figure 2.8: A Cycle with EMD 2 4

27 Chapter 3 Improvement of waterfall and error rate performance in high SNR In this chapter we analyze the cycles in ARA codes and find particular cycles with small value of EMD containing some part of the dual diagonal. Then we propose a scheme to keep up the waterfall steeper and improve the error rate performance of ARA codes in high SNR by selective accumulation. 3. Analysis of cycles of ARA codes Now we are going to analyze the cycles in the bipartite graph of ARA codes. The bipartite graph structure is semi-deterministic due to protograh of the codes. Dual diagonal made by accumulator is such an example. Through the analysis of the dual diagonal which produces parity bits we can find some particular cycles with small value of EMD containing some part of the dual diagonal. The cycles passing through parity bits are comprised of interleaved bits and parity bits but we can find a special type of cycles passing through parity bits. 5

28 p i c j pi c j pi 2 c j 2 b k c j 3 i L4 (a) Consecutive parity bits cycle L i 4 (b) Appearance in parity check matrix Figure 3.: An example of consecutive parity bits cycle set L 4 with EMD 2 Definition 3. Consecutive parity bits cycle set L d A set of variable nodes and check nodes which consist of d consecutive parity bits, iterleaved bit and d consecutive check nodes, which contains some part of dual diagonal of the parity check matrix. Figure3. is an example for L 4 = {p i,p i+,p i+2,b k,c j,c j+,c j+2,c j+3 } where p s are parity node, b is interleaved bit and c s are check nodes. Superscript i is just an index of set according to size order. The parity bits provide no EMD since the degree of d parity bits in L d is 2 and all of them participate in the cycles. Thus EMD of consecutive parity bits cycle set is determined by degree of a interleaved bit node. Let us E(L d ) denote EMD of L d. We can calculate the E(L d ) as following. E(L d )=Degree(b k ) 2 The set size of L d is not only small but its EMD is also relatively small compared to the cycles of same size in the conventional LDPC codes. Since L d with small d has 6

29 small EMD and small size it is likely to be a small size of stopping set. In addition the parity bits receive low reliable message due to their low degree of two. Furthermore the union of some L d s also has small EMD compared to the cycles of same size in the conventional LDPC codes as well. But the union of L d s more than three are complicated to consider and the size and EMD of union are not too small. Thus in the thesis we are going to only consider the unions of two consecutive parity bits cycle sets. Let us consider unions of two L d s. Depending on the graph structure the event that EMD of the union is less than sum of individual EMD of the component set may occur. This event can happen when the two component set of uinon L i d and Lj d share the extrinsic check nodes or one set contains extrinsic check nodes of the other. Figure 3.2 shows an example that the union of an L 0 3 and an L 4 share the extrinsic check nodes. The size of the union is 7 and the EMD is 3. Their individual EMD s are 3 and 2 but the EMD of union is not 5 since they share a check node c s. These unions are especially weak in term of EMD compared to any other unions of L d s. Let us define deficient EMD for union of L i d and Lj d as measure of weakness in terms of EMD. Deficient EMD of union : E Def (i, j) E(L i d )+E(Lj d ) E(L i d Lj d ) The larger E Def, The weaker the union is in terms of EMD. We have investigated the specific cycles in ARA codes so far. Our proposed scheme to improve error floor of ARA codes is based on the consecutive parity bits cycles. We want to increase EMD of the consecutive parity bits cycle so that they may be a large size of stopping set. In order to do we will make a new edge connection to consecutive 7

30 c m 0 L 3 p n pi L 4 c j cm pn pi c j cm 2 bt pi 2 c j b k c j 2 c s Figure 3.2: An example for union of two L d s with size 7 and EMD 3 parity bits cycles and it can be identified by appearing new s down the dual diagonal. We have problems which L d, parity and check node do we choose. Next section will give the criterions. 3.2 Criterions for new connection It is preferred that new path induced by new edges involves more nodes in order that the new edges may make the L d s be a large stopping set when we add new edges to L d.we are going to define self return distance l s. Definition 3.2 Self return distance l s Self return distance is the shortest number of edges from L d to L d by spreading a tree from edge outside L d. Once the consecutive parity bits cycles are found we can calculate initial self return distance ls ini. We make a new connection so that adding a new edge does not get l s shorter 8

31 ini ls 4 ls 7 Figure 3.3: An example for self return distance than ls ini. Large l s lets the more variable nodes participate in stopping set including L d and increase EMD of union set. But l s does not have to be maximized since proper number of variable nodes involved in new path is enough. Figure 3.3 shows an example with l ini s =4. A new path involves in 3 variable nodes. The union of L d and these variable nodes will require more additional nodes to be a stopping set than the union Adding a new edge means we have to choose a parity bits and a check node. We keep the following rule when we choose a parity and a check nodes. Parity bits selection ARA codes have erasure bits in general as explained in chapter 2. We take a ARA code in Figure 2.2 as an example. A parity bit is connected to two check nodes and the check nodes are connected to another 4 variable nodes. These four variable nodes are composed of one parity bit, information bits and erasure bits. The more erasure bits a check node are connected to, the lower reliability the check nodes gives to a parity bit since 9

32 erasure bits passes no message under belief propagation. We call this scenario erasure and information bit connectivity. Therefore we choose a parity bits which is likely to receive low reliability from their check nodes considering erasure and information bit connectivity. If there are multiple choices of parity bits we select randomly. Check node selection Once selecting a parity bit we are faced to choose a check node to be connected to a chosen parity bit. Selecting a check node we keep the erasure and information bit connectivity in mind. In the sense of the connectivity it is also reasonable to choose a check node which has more information bits than erasure bits. Figure 3.4 shows selection of a parity bit and a check node in terms of erasure and information connectivity. But selection of a check node is more complicated. We have to consider things related to l s, EMD and cycles since there are so many candidate check nodes satisfying erasure and information connectivity. We prepare some criterions to choose a good check node.. Candidates have to satisfy erasure and check nodes connectivity. 2. New path induced by selection a pair of parity and check node does not make l s shorter than l ini s. 3. New connection makes E Def (i, j) decreased and E(L i d ) increased for a set Li d to be added with new edge compared to previous graph. 4. If there are multiple candidates choose a check nodes that gives maximum cycle length 20

33 Condition 3 means that new connection not only increase EMD of L d but does not also make the cases that union individual EMD of component set such as Figure 3.2. For every candidate check node to be connected to a consecutive cycle L i d the E(Li d ) and E(i, j) for j i is calculated from resulting graph. Assuming that new connection by the candidate is done new E(L i d ) have to be increased and new E(i, j) have to be decreased compared to previous E(L i d ) and E(i, j) respectively. Once we connect a new edge the new cycle comprised of only parity bits is produced as shown in Figure 3.5. Since this cycle consists of only parity bits the message passing through the cycles has low reliability. In order to overcome the resulting bad effect it is recommended to increase the length of the resulting all parity bits cycle. It is realized by permitting a check node apart from the previous check nodes of a chosen parity by some value D s. Then the length of resulting all parity bits cycle is 2(D s +). p p k k e p p k e e p k e e p k e e Figure 3.4: Selection of a parity bit and a check node 2

34 L 4 D s Figure 3.5: All parity cycle produced by new edge connection 3.3 Proposed algorithm Based on the previous discussion we will summarize the algorithm in Figure 3.7. Let us T, A max, A i and S denote total number of consecutive parity bits cycles, maximum number of added edges, number of added edges to L i and length of shortest all parity cycle respectively. In setp. all L d s are identified by analyzing the shortest cycles passing through the parity bits. For encoder implementation of proposed algorithm we take selective accumulations with chosen parity by a value D s corresponding to its added check nodes. Figure 3.6 shows the encoder implementation for proposed algorithm. The encoder for proposed algorithm contains only additional block for D s compared to original encoder Figure 2.2b The proposed algorithm raises little encoding and decoding complexity. The number of added s in the parity check matrix is not too many parity bits are selected 22

35 D s Figure 3.6: Implementation of encoder for proposed algorithm by the algorithm for ARA codes with K = 50 and code rate R =/2 in next section. And for a chosen parity the maximum number of added edges A max cannot be large since too many edges for a parity result in many all parity bits cycles. 23

36 step. Analysis Identify all L d s and index them from 0 to T according to increasing size. Determine D s and A max step 2. Initialization Calculate E(L d ), E Def (i, j) for 0 i, j T and l ini s A i =0 for all i stpe 3. Adding new edges begin for union if E Def (i, j) > 0 for 0 i<j T if A i <A max L i new edge such that l s ls ini, S>2Dand E Def(p, q) not increased A i = A i + end if A j <A max L j new edge such that l s ls ini, S>2Dand E Def(p, q) not increased A j = A j + begin for single cycle end if A i <A max for 0 i, j T L i new edge such that l s ls ini, S>2Dand E Def(p, q) not increased A i = A i + Figure 3.7: Summary of proposed algorithm 24

37 3.4 Simulation results In this section we present simulation results for ARA codes applying proposed algorithm over AWGN channel. We generate two ARA codes in Figure 2.2 with information bit K = 50 and code rate R =/2using PEG interleaver. The two ARA codes have local girth distributions shown in table 3.. Analyzing the shortest cylces passing through parity bits of ARA codes we can obtain distribution of consecutive parity bits cycles shown in the table 3.2. Based on the Table 3. and 3.2 we can expect that the code (2) tends to show better performance than the code (). local girth ARA code () ARA code (2) Table 3.: Local girth distribution of two ARA codes ARA code () ARA code (2) L L L L Table 3.2: Consecutive parity bits cycle set distribution of two ARA codes Following simulation results give performance evaluations. We transmitted all-zero codewords and used sum-product algorithm for decoding with maximum iteration 00 for Figure 3.8 and 200 for Figure 3.9 and 3.0. ARA codes are concatenated RA code with rate outer accumulator to achieve lower threshold than RA codes in the 25

38 0 0 Comparison to RA Code and Irregular LDPC code BER and FER RA code FER Irregular LDPC FER ARA code () FER ARA code (2) FER RA code BER Irregular LDPC BER ARA code () BER ARA code (2) + BER Eb/No Figure 3.8: Performance comparison of RA and ARA codes waterfall. Figure 3.8 shows the gain of ARA codes in the waterfall region, where RA codes with same repetition as one of ARA codes is used. Figure 3.8 also shows the performance comparison to irregular LDPC codes with degree distribution λ(x) = x x x x x x x 4 [9]. In the waterfall region ARA codes present better performance than irregular LDPC code but they give high error floor and narrow waterfall region with respect to error rate. We applied proposed algorithm to the ARA codes () and (2). The maximum number of added edges for each consecutive cycle is set to and D s is set to 0 for ARA code 26

39 () and 30 for ARA code (2) repectively. Thus the resulting the length of all parity bits cycle is guaranteed to be more than 20 and 60 for each code. We obtain results in Figure 3.9 for ARA code () with 9 edges added and Figure 3.0 with 5 edges added. The ARA code (2) shows better performance than ARA code () as expected. It is caused by distribution of local girth and consecutive parity bits cycles. The ARA code () contains more small size of consecutive parity bits cycles than ARA code (2) relatively. The proposed scheme provides 0.35 db gain for ARA code () and 0.5 db gain for ARA code (2) at FER 0 4. In terms of waterfall proposed algorithm makes the waterfall steeper and preserved longer than the original one. For comparison we added same number of edges to randomly selected parity bits using PEG algorithm which is known that gives reasonably good performance under iterative decoding. Adding new edges using PEG algorithm does not deteriorate the girth condition surely but gives no gain. The results are nearly same as original codes. On the observation of the simulation results we discuss the relationship between the measure of performance improvement and the distribution of consecutive parity bits cycles. It is significant that applying scheme to ARA code () derives more improvement than to ARA code (2). Proposed scheme utilizes the short consecutive parity bits cycles to improve waterfall and error rate performance in high SNR. That is the reason why application to ARA code () is more effective than ARA code (2). The improvement is caused by effective utilization of consecutive parity bits cycles. If there is no consecutive parity bits cycles we cannot use the propose scheme. But it is hardly possible to remove all the consecutive cycles. 27

40 0 0 Performance of proposed scheme,200 Iterations BER and FER ARA code () FER ARA code () + PEG 9 edges FER ARA code () + proposed FER ARA code () BER ARA code () + PEG 9 edges BER ARA code () + proposed BER Eb/No Figure 3.9: Performance of ARA code () 28

41 0 0 Performance of proposed scheme, 200 Iterations BER and FER ARA code (2) FER ARA code (2) + PEG 5edges FER ARA code (2) + proposed FER ARA code (2) BER ARA code (2) + PEG 5edges BER ARA code (2) + proposed BER Eb/No Figure 3.0: Performance of ARA code (2) 29

42 Chapter 4 Concluding Remarks ARA codes have particular cycles with small EMD and small size containing some part of dual diagonal. This cycles tends to be small stopping sets and result in small minimum distance of codewords. In the thesis we define consecutive parity bits cycle L d and propose a scheme to improve waterfall and error rate performance of ARA codes in high SNR by increasing their EMD. We verified that the proposed scheme is available to improve the performance by the simulation results. The proposed scheme is attractive since the scheme achieves the improvement of waterfall and error rate performance in high SNR with no loss in low SNR. In addition hardly the scheme burdens complexity to both encoder and decoder. However the proposed scheme have some limits.. If ARA codes does not have enough short consecutive cycles the proposed scheme is not effective. Because the proposed scheme utilize the short consecutive cycles. 2. Applying to RA codes is not effective. Through the analysis of cycles in RA codes we have known that RA codes does not have enough short consecutive cycles. It 30

43 is one reason why the proposed scheme is not useful for RA codes as. But we conjecture that other reasons make it unuseful for RA codes. 3. Analyzing the cycles and finding consecutive parity bits cycles are practical when the code length is moderate. Tree spreading of a graph has exponentially increasing complexity. If the code length is long proposed algorithm is no longer useful. 3

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46 כ SNR Accumulate-Repeat-Accumulate ARA כ waterfall. EMD SNR ARA waterfall. ARA EMD EMD. ARA FER dB 0.5dB. SNR. : LDPC, Accumulate-Repeat-Accumulate, EMD, stopping, 34