Cisco [ advertises 64K cells output buers per link for its LightStream 00 ATM switch. Stratacom provides 64K cells

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1 Analysis of Queueing Displacement Using Switch Port Speedup Israel Cidon y Department of Electrical Engineering Technion - Israel Institute of Technology Haifa 3000, Israel cidon@ee.technion.ac.il Moshe Sidi z Department of Electrical Engineering Technion - Israel Institute of Technology Haifa 3000, Israel moshe@ee.technion.ac.il Asad Khamisy SUN Microsystems Labs 550 Garcia Avenue Mountain View, CA 94043, U.S.A. asad@eng.sun.com Abstract Current high-speed packet switching systems, ATM in particular, have large port buering requirements. The use of highly integrated ASIC technology for implementing high-degree and high-speed switch fabrics is facing a technology mismatch in the sense that today's chip technology does not allow to integrate on-chip the high-speed switching fabric with the large buering requirements. Consequently, many designs are based on the principles of queueing displacement, i.e., they attempt to move the queueing point o-chip. This is usually done by considerably speeding-up the on-chip switch output ports and placing a second external stage of buering between the switch fabric and the outgoing link circuitry. Such designs are very popular and are used by many current ATM switch vendors. While such schemes are widely used, no rigorous analysis has so far been oered to evaluate the design trade-os and to quantify the design points. The model we use to analyze the performance ofthe above system is a two-node tandem queueing system. The rst node in the tandem corresponds to the internal buer while the second node in the tandem corresponds to the external buer. It is assumed that the internal buer is capable to transfer c cells per time unit to the external buer, while the external buer is served at a lower rate of c cells per time unit. The work of I. Cidon and M. Sidi was partially supported by Intel, Israel and by the Fund for the Promotion of Research at the Technion. y also with SUN Microsystems Labs, 550 Garcia Avenue, Mountain View, CA 94043, U.S.A. z Part of the work of this author was done while visiting SUN Microsystems Labs, Mountain View CA, U.S.A. Introduction This paper addresses basic design and performance issues in the architecture of hardware based fast packet switches. The ability to implement cost-eective high-speed switches in silicon is (along with the advance of ber-optic technologies) the enabling technology behind the recent rise of broadband integrated networks, in particular the ATM architecture [,, 3, 4, 5, 6]. Fast hardware based switches have also been at the core of the emerging switched LAN (also termed switching hubs) products as well as the new generation of Gigabit routers [ Current switching system designs in high-speed packet-switching networks and in particular the emerging ATM market have large and consistently growing port buering requirements. This trend follows the expected use of ATM networks for bursty data applications, the use of reactive ow control over ever increasing link speeds and the separation of dierent QoS classes and connection groups to dedicated buers. While in the past ATM vendors have frequently oered switches with less than a hundred cell (5Kbytes) buers, the numbers today have grown typically to more than 0K cell buers. These numbers are expected to continue to grow with the speed of links, with the geographical distances, as well as with the use of more sophisticated buer scheduling mechanisms. For example, Fore System [ html] advertises buer sizes of 53K cells (almost 3Mbytes) and K cells (Mbytes) for its AS- 00 and AS-000 ATM switches, respectively /97 $ IEEE

2 Cisco [ advertises 64K cells output buers per link for its LightStream 00 ATM switch. Stratacom provides 64K cells per port at its BP switch [ The GTE [ span4000.html] SPANet 4000 ATM switch is designed with a buer size of 6K cells. Most hardware based switch designs rely on the new generation of CMOS ASICs which are very popular within products which require fast turn-around and at the same time high integration and high performance. (Nevertheless, these following statements are also correct for today)s fully custom VLSI designs.) The use of highly integrated ASIC technology for implementing high-degree and high-speed switch fabrics (88 to 33 with 55-6Mbps) is facing a technology mismatch in the sense that today)s technology does not allow tointegrate within the same ASIC the high-speed switching fabric logic of many ports with the large amount of fast memory required to buer all switch output ports. Switch Fabric ASIC Figure : Speedup used to extend the memory in an ASIC based switch Consequently, many designs are based on the principles of queueing displacement, i.e., the attempt to move the queueing point o-chip and implement the main buer using standard RAM technology. This is usually done by considerably speeding-up the integrated switch output ports (compared to the actual link speed supported) and placing a second stage (external to the switch) of buering between the switch fabric and the outgoing link. The much higher speed at which the internal buer is o-loaded, considerably reduces its memory requirements for a given overow probability design point. Such a design is very popular and is used by many current C C ATM switch vendors (usually termed as speedup). In particular, the ones which base their buering design on output queueing techniques. (Other designs are also possible, for example, pure input queueing or a shared memory design based exclusively on o-the-shelf RAM.) Figure depicts an ASIC with a limited on-chip buer at the switching fabric being extended with an external memory using the speedup technique. For example, the IBM switch-on-a-chip Prizma chip is limited by the number of on-chip buers and employs speedup technique [ and [8]. Bay Networks, uses speedup in its Lattice Cell switch design to increase the eective amount of buers in its multi-stage switching fabric. While speedup schemes are widely used, no rigorous analysis has so far been oered to evaluate the design trade-os and to quantify the design points. The designer would like toevaluate the size of the internal and external buers required for a certain design point aswell as the speed of the path connecting them together. In particular, it is attractive to map (or lower bound) such dual stage designs to the performance of an \ideal" output queueing design in order to be able to compare dierent switches of different design points. The following works have addressed the speedup problem or have used queueing models which are related to our problem. In [0], the speedup eect was explored using a tandem system model composed of an M/M/C queue feeding a dependent M/M/ queue. This model was investigated by extensive simulation and no rigorous analysis was carried out for the speedup problem. In the relevant tandem queues models only limited results are available. In [9] a tandem of two single server discrete-time queues with independent and identically distributed external arrival processes, where the output of one queue is fed as an additional input for the other queue is solved. This is a special case of our solution when no speedup exists and the server can serve only a single cell at a time slot. In [, ] Boxma analyzes two exponential single server queues in series where the rst queue has a Poisson arrival process and the second is fed by the output of the rst. In both queues the same customers have the same service times. In this case, again, the system in question has no speedup. In [3] a tandem of multiple queues in which message sizes are preserved is considered. Several properties of the joint work load distribution (but no full solution) are presented and proved for such a system. The model we use to analyze the performance of the system with speed-up is a two-node tandem discrete /97 $ IEEE

3 time queueing system. The rst node in the tandem corresponds to the internal (in-asic) buer while the second node in the tandem corresponds to the external buer. We begin the analysis of this system assuming that the external buer can output at most one cell per slot and derive the generating function of the joint probability distribution of the lengths of the two buers. Moments of the queue lengths are then derived. In addition, we introduce an explicit recursion to compute the joint probability distribution. From this we are able to compute tail probabilities that enable us to dimension the length of the buers required to guarantee small loss probabilities when the buers are nite. Speedup of two has special implementation importance as it is a very common and convenient speedup to design and use. It usually does not require tricky clock resynchronizations as either one clock is derived from the other or the path that connects the two buer stages is of double width. Intuitively, with such speedup, the load on the rst buer stage is only half the load on the output port. In a well controlled network, no link should be overloaded (on the average) and hence the rst port has a load limitation of 0.5. This rather low load should enable us to use very few buers at the internal rst stage. Our main numerical conclusion supports this intuition and shows that the internal buer can be kept small without damaging the performance of the whole system. We extend the analysis to more general models in which the external buer can output several cells per slot, and again obtain the generating function of the joint probability distribution of the lengths of the two buers and the moments. The conclusions obtained are similar to the above. The Model The model we use to analyze the performance of the system with speed-up is a two-node tandem discretetime queueing system. The rst node in the tandem corresponds to the internal (in-asic) buer while the second node in the tandem corresponds to the external buer. Time is slotted into xed size slots. It is assumed that during each slot the internal buer is capable to transfer c cells to the external buer, while the external buer is capable to output from the system c cells. Since the internal buer is faster than the external buer, c >c. Note that when c = wehaveintegral speedups (c : ), while for a general c we can have any rational speedup (c : c ). Let A (n) and A (n) be the number of new cells arriving (from outside the system) during slot n to the rst node and the second node, respectively. The arrival process of these new cells at the system is assumed to be an independent and identically distributed (in each slot) process, namely, fa (n) ;A(n) g is independent of fa (k) ;A(k) g for any n 6= k, and Prob(A (n) = i; A P (n) = j) = a i;j is independent of n. Let A(z ;z )= P a i;jz i zj be the joint generating function of the arrival processes to the two nodes. Note that arrivals to the two buers in P the same slot may be correlated. We let r l = i =0P i i =0 la i;i ;z )=@z l j z=z= be the arrival rate of cells to node l (l =;). For the sake of the analysis, we assume that both buers are of in- nite size. We will later discuss how this assumption can be dealt with to attain the performance of realistic switches. (Note that the speedup based output port system corresponds to the case with no external arrivals to the second node, i.e., a i;j =0; j >0.) 3 Analysis We begin our analysis with c =, namely, a single cell can be transmitted by the second node and leave the system during a slot. Note that when c =,our system is identical to the system analyzed in [9]. In our analysis we are interested in computing the steadystate probabilities of the lengths of the two nodes. Since at most one cell can leave the system during a slot, steady-state exists if r r <. Assume that departures take place at the end of slots and arrivals within slots. Let Q (n) and Q (n) denote the lengths of the rst node and the second node at the end of slot n, respectively. Let p (n) i;j = Prob(Q P (n) = i ; Q (n) = j) and G (n) (z ;z )= P p(n) i;j zi zj be the generating function of the joint queue length distribution at both nodes. We let p i;j = lim n! p (n) i;j and G(z ;z ) = lim n! G (n) (z ;z ). The evolution equation of the queue lengths for n 0 is given by Q (n) = (Q (n) c ) A (n) Q (n) = (Q (n) ) min(q (n) ;c )A (n) () From which we have in steady-state (n!), c G(z ;z )=A(z ;z )fp 0;0 p i;0 z i z i zi i= j= j= i= p i;j z i zj z i zi p 0;j z j z p i;0 z i z c z c i=c /97 $ IEEE

4 i=c j= p i;j z i zj z c z c g () Simple algebraic manipulations yield the following, B(z ;z ) G(z ;z )=A(z ;z ) z c z z c A(z ;z ) where B(z ;z )= P c [p i;0(z ) g i (z )](z c z i zc )G(z ; 0)z c (z ) and g i (z )= i! i (z ;z i (3) z =0. In (3), we encounter a common phenomenon in dependent queues, namely, that the generating functions G(z ;z ) is expressed in terms of several boundary functions. In order to uniquely determine G(z ;z ) we will have to determine the boundary functions, G(z ; 0) and g i (z ); 0 i c. In what follows, we develop the method for obtaining these boundary functions. Along this process we mainly use the analytic properties of the generating functions G(z ;z ) in the disk jz i j < ; i =;. We begin by letting z! 0 in () to obtain G(z ; 0) = A(z ; 0)[p 0;0 p 0; ]. When z =0wehave that p 0;0 = a 0;0 (p 0;0 p 0; ) (4) Therefore we can express G(z ; 0) (and the corresponding probabilities p i;0 ; i ) in terms of the constant p 0;0 as follows, G(z ; 0) = A(z ; 0) p 0;0 a 0;0 ; p i;0 = a i;0 p 0;0 a 0;0 i (5) To determine g i (z ); 0 i c, we use the fact that for any jz j <, the denominator z c z z c A(z ;z ) of (3) has exactly c roots within the unit disk jz j < (the proof is based on Rouche`s Theorem). Let these roots be denoted by l (z ); l c. Since G(z ;z ) is an analytic function in the disk jz i j < ; i =;, the nominator of (3) must vanish at each of these roots, i.e., B( l (z );z ) = 0 ; l c (6) where in the above we use p i;0 from (5) and G( l (z ); 0) = A( l (z ); 0)p 0;0 =a 0;0. Expression (6) is a set of c (linear) equations that determines the functions g i (z ); 0 i c up to the constant p 0;0. To complete the derivation of the generating function we need to compute that constant. To that end, let z = z = z in (3) to obtain, G(z;0)(z ) G(z; z) = A(z; z) z A(z; z) = A(z; z) A(z;0)p 0;0(z ) a 0;0 [z A(z; z)] at (7) Letting z! in the above and assuming that the steady-state condition r r < holds, we obtain by using L)H^opital)s law, p 0;0 = a 0;0( r r ) A(; 0) (8) This completes the derivation of the joint generating function of the queue-length probability distribution. Using the generating function we can obtain the average number of cells in node i (i =;), denoted by L i. Letting z = in (3) we have G(z ;) = A(z ; ) g i ()(z c z i ) z c A(z ; ) Taking the derivative of the above expression with respect to z and letting z! we obatin, L = r g i ()(c i )r c ^A (c r ) (9) where ^A = d A(z; )=dz j z=. Taking the derivative of (7) with respect to z and letting z! we obatin (using (8)), d A(z;z) dz j z= da(z; 0) L L = r r j z= dz ( r r ) (0) Subtracting (9) from (0) we obtain the average number of cells in the second node L. 4 The Probability Distribution The joint generating function derived in the previous section allows us to compute p 0;0 and the average quantities easily. However, the computation of the probabilities themselves is dicult. In this section we develop a recursion for the computation of the steadystate probabilities p n;n.from equation (4) we obtain p 0; = p 0;0 ( a 0;0 )=a 0;0.Together with equations (5) and (8) wehave the initial conditions for the recursion, i.e., we know p i;0 ; i0 and p 0;. Next, we compute the probabilities p n;n for n 0 and n c (except for p 0; that is known already). In order to have n ; n c ; cells in the second queue, the number of cells in the rst queue at the end of the previous slot have to be less or equal to n. Assume the number of cells in the rst queue is i; 0 i c ; then in order to have n cells in the rst queue, all n cells have to arrive from the external source. Further, assuming that j cells arrive to the second queue from the external source, /97 $ IEEE

5 the total number of cells that arrive to the second queue is i j. If the second queue is not empty at the end of the previous slot, then in order to have n cells, the number of cells at the end of the previous slot have to be n i j, where the plus accounts for the cell that must have departed the second queue. We have for n 0; n c that p n;n = n n n p i;0 a n;n i i p i;n i ja n;j () where the rst sum corresponds to the case where the second queue is empty at the end of the previous slot. Note that n appears in the right hand side of equation () only in a n;l for some l (and does not appear in any ofthep)s). In equation () we compute the probabilities p n;n in increasing order of n as follows. We assume that p i;j for i 0; 0 j n aswell as p 0;n are known (initially, for n = this is true as explained at the beginning of this section). Next, we compute p 0;n ; p ;n by solving two equations with two unknowns. These equations correspond to equation () with p 0;n and p ;n in the left hand side. Note that the unknown p 0;n appears only in the right hand side of (), while the unknown p ;n appears also in the left hand side. After some simple algebra we obtain the solution for p 0;n ; p ;n as, p 0;n = ( ;n ()a 0;0 ;n (0)(a ;0 ))=a 0;0 p ;n = ( ;n (0)a ;0 ;n ()a 0;0 )=a 0;0 () where we dene ;n (l) =fl=0gp 0;n min(c ;(n )) n i min(c ;(n )) i= j= p i;n i ja l;j fj=n ig p i;n ia l;0 l =0; (3) Now the probabilities p n;n for n are computed directly from equation (). Recursing this procedure completes the computation of the probabilities p n;n for n 0 and n c. Next, we compute the probabilities p n;n for n 0 and n c. There are two cases to consider in the recursion, the rst is when the number of cells in the rst queue is less than c in which case all cells move to the second queue, and the case where the number of cells in the rst queue is greater or equal to c in which case only c cells move from the rst queue to the second queue. Similar to the previous recursion, we have for n 0;n c, p n;n = p i;0 a n;n n i n c i p i;n i ja n;j i=c p i;0 a nc i;n c n c n c i=c p i;n c ja nc i;j(4) In the same way as before, we write two equations for p 0;n and p ;n, from which we obtain the probabilities p 0;n ; p ;n. Then we use equation (4) to compute the probabilities p n;n for n. The solution for p 0;n ; p ;n in this case is given by: p 0;n = ( ;n ()a 0;0 ;n (0)(a ;0 ))=a 0;0 p ;n = ( ;n (0)a ;0 ;n ()a 0;0 )=a 0;0 (5) Where we dene ;n (0) = ;n (0) and ;n () P n = ;n () c p c;n c ja 0;j fj=n c g. Now the probabilities p n;n for n are computed directly from equation (4). This completes the computation of the probabilities p n;n for n 0 and n c. The computation complexity of the probabilities p n;n for 0 n N and 0 n N is in the order of O(N N ). 4. Overow Probability Since we use innite buers in our model, we approximate the cell loss probability by the buer over- ow probability. The rst (second) node is in overow state when the number of cells in the buer exceeds N (N ). If the state upon arrival is (n ;n ), then the the number of cells in the second queue in front of this cell, when this cell arrives to the second queue, will P d(n)=c e i= A (i) d(n )=c e, where be n n A (i) denotes the number of cells that arrive to the second queue in slot number i (the slot of arrival of the cell is marked as slot number ). This is true since. The cell will arrive at the second queue d(n )=c e slots after it arrived to the system, and. c > and hence the second queue will not empty in the next d(n )=c e slots after the arrival of this cell. Correspondingly, we dene the overow probability in the system as the probability that the number of /97 $ IEEE

6 cells in the rst and second nodes at slot boundaries full the relation (n ;n )f(n ;n ) j n >N ; n n d(n )=c e >N g. Next, we consider a system without external arrivals to the second queue, i.e., a i;j =0;j>0. Then, the overow probability in the system is equal to P overflow = N n =0 N d(n )=c e n p n;n (6) n =0 5 The case c > We now consider a system with c >, namely, several cells (c ) can be transmitted by the second node and leave the system during a slot. As before, we are interested in computing the steady-state probabilities of the lengths of the two nodes. Since c > cells can leave the system during a slot, steady-state exists if r r <c. With the same notations as in Section 3 the evolution equation of the queue lengths for n 0 is given by Q (n) = (Q (n) c ) A (n) Q (n) = (Q (n) c ) min(q (n) ;c )A (n) (7) Similar to the method for obtaining (), we obtain in this case, G(z ;z ) = A(z ;z )f i=c i=c p i;j z i zj z i j=c p i;j z i zj z i zi j zi c p i;j z i zj z c z c j j=c p i;j z i zj z c c c z and after simple algebraic manipulations we get, B(z ;z ) G(z ;z )=A(z ;z ) z c zc z c A(z ;z ) where B(z ;z ) = z i )g i(z )](z c zi z i zc ) c c c [ g (8) p i;j (z c (9) f j (z )z c (zc z j ) and g i (z i (z ;z ) j z=0, f i j (z j (z ;z ) j z=0. j In order to uniquely determine G(z ;z )we will have to determine the boundary functions, f j (z ); 0 j c and g i (z ); 0 i c. In what follows, we demonstrate the method for obtaining these boundary functions. Along this process we mainly use the analytic properties of the generating functions G(z ;z ) in the disk jz i j < ; i =;. We begin by taking the l-th derivative (0 l c ) of both sides of (8) with respect to z and let z! 0 to obtain, f l (z )= l k=0 A l k (z ) u k (l k)! (0) where A i (z ) i (z ;z )=@zj i z=0, and u k = P P c p k k;j p j;c k j. Consequently, f l (z ) (and the corresponding probabilities p i;l ; i0) are expressed in terms of the constants u k ; 0 k l. To determine these constants, we let z = z = z in (9) to obtain, ^B(z) G(z; z) =A(z; z) () z c A(z; z) where ^B(z) = P P c (zc z j j ) k=0 A j k(z) u k =(j k)!. Letting z! in the above and assuming that the steady-state condition r r <c holds, we obtain c r r = (c j) j k=0 A j k () u k (j k)! () Furthermore, the denominator z c A(z; z) of () has one root at z = and exactly c roots within the unit disk jzj < (the proof is based on Rouche`s Theorem). Let these roots be denoted by l ; l c. Since G(z; z) is an analytic function in the disk jzj <, the nominator of () must vanish at each of these roots, i.e., for l c, ( c l j l ) j k=0 A j k ( l ) u k (j k)! =0 (3) Equation () together with (3) is a set of c (linear) equations that determines the constants u k ; 0 k c, and hence the boundary functions f j (z ); 0 j c are determined (using (0)). From f j (z ) we can obtain p i;j ;j0by taking the i-th derivative of f j (z ) with respect to z and letting z! 0. To determine g i (z ); 0 i c, we use the same procedure described in Section 3. In particular, we note that for any jz j <, the denominator z c zc z c A(z ;z ) of (9) has exactly c roots within the /97 $ IEEE

7 unit disk jz j < (the proof is based on Rouche`s Theorem). Let these roots be denoted by l (z ); l c. Since G(z ;z ) is an analytic function in the disk jz i j < ; i =;, the nominator of (9) must vanish at each of these roots, i.e., B( l (z );z ) = 0 l c (4) Expression (4) is a set of c (linear) equations that determines the functions g i (z ); 0 i c. This completes the derivation of the joint generating function of the queue-length probability distribution. In [4] we provide the procedure for computing the joint probability distribution in this case. Using the generating function we can obtain the average number of cells in node i (i =;), denoted by L i,aswas done in Section 3. In fact, the average number of cells in the rst node does not change with c, hence is identical to (9). Taking the derivative of () with respect to z and letting z! we obatin, L L = r r where ^A = ^A c (c ) (c r r ) j k=0 d A(z;z) dz j z= (c r r ) u k (j k)! f[c (c ) j(j (5) )]A j k ()(c j)da j k (z)=dzj z= g. Subtracting (9) from (5) we obtain the average number of cells in the second node L. 6 Numerical Results In the rst example cells arrive to the system (through the rst node only) according to a Poisson process with rate. We set c = and c =. In Figure we plot the overow probability in the system versus the internal buer size for external buer size of 80 cells and load of =0:9. We also plot the overow probability in the internal buer, external buer and in an \ideal" output buer switch with c =. From Figure we notice that for internal buer size greater or equal to 5, the overow probability in the system is less than the overow probability in the \ideal" system. Also, the main contribution to the total overow probability for small (large) internal buer sizes comes from the internal (external) overow probability. Notice that the internal buer reduces the burstiness of the input process to the external buer by limiting the maximum number of cells that can arrive to the external buer to c =, and hence the overow probability in the system and in the external buer is smaller than the overow probability in the \ideal" system. We obtained numerical results for dierent external buer sizes and loads where the overow probability in the \ideal" system was kept at 0 7. In all examples, an internal buer size between and 4 cells was sucient to bring the overow probability in the system below 0 7. The same phenomena described in Figure were observed in all examples. Overflow Probability System Overflow Probability _._._ Internal Overflow Probability... External Overflow Probability Ideal Overflow Probability Internal Buffer Size Figure : Overow probability versus internal buer size for load of 0.9 and external buer size of 80 cells. More numerical results are provided in Figure 3 where we plot the overow probability versus the average load for internal buer size of 5 and external buer size of 40. We see again that internal buer size of 5 is enough to achieve smaller overow probability in the system compared to the \ideal" system, for average load of 0.75 or larger (for the range of 0 9 overow probability this is the relevant load range). Numerical results for the case c > are provided in [4]. Overflow Probability Total Overflow Probability _._._ Internal Overflow Probability... External Overflow Probability Ideal Overflow Probability Average Load Figure 3: Overow probability versus average load for internal buer size of 5 and external buer size of /97 $ IEEE

8 We also simulated a system with bursty trac model that corresponds to VBR trac class. Here we used three groups of sources. Each group consists of 0 identical sources. Each source corresponds to Interrupted Poisson Process (IPP) model, with sources in the rst group having an average ON period of 00 slots and average OFF period of 00 slots. The second and third group sources have average (ON, OFF) periods of (00, 300) and (00, 900), respectively. The average load in the system is termed "VBR Load" and the total load of each group is "VBR Load"/3. Table 6 contains the overow probability in the \ideal" system and in the system versus "VBR Load" for dierent internal buer sizes. The conclusions are similar to the Poisson model. [6] J. Hui, "A broadband packet switch for multirate services," Proc. of International Conference on Comm. (ICC'87): 78{788, June 987. [7] AT(T Microelectronics, Microelectronic Products Selection Guide, AT(T Microelectronics, Jan [8] W. E. Denzel, A. P. J. Engbersen, I. Iliadis, and G. Karlsson, "A highly modular packet switch for GB/S rates," Proc. of International Switching Symposium, :A8.3, Oct. 99. [9] J. A. Morrison, "Two discrete-time queues in tandem," IEEE Trans. on Comm., COM-7:563{ 573, 979. VBR Load Ideal IB = 8 IB = 0 IB=5 IB = 0 0:6 : : : : : :66 7: : : : : :70 : :8 0 3 : : : :74 3: : : : : :78 6: : : : : :8 :04 0 :06 0 :04 0 :03 0 :03 0 Table : Overow probability versus VBR Load for external buer size of 00. References [] J. S. Turner, "Design of an integrated services packet network," IEEE Journal on Selected Areas in Comm., SAC-4:373{380, Nov [] I. Cidon and I. S. Gopal, "PARIS: An approach to integrated high-speed private networks," International Journal of Digital and Analog Cabled Systems, ():77{85, April 988. [3] J. N. Giacopelli and et al, "Sunshine: A high-performance self-routing broadband packet switch architecture," IEEE Journal on Selected Areas in Comm., SAC-9:89{98, Oct. 99. [4] P. Newman, "A fast packet switch for the integrated services backbone network," IEEE Journal on Selected Areas in Comm., SAC-6:468{ 479, 988. [5] Y. S. Yeh, M. G. Hluchyj, and A. S. Acampora, "The knockout switch: A simple, modular architecture for high performance packet switching," IEEE Journal on Selected Areas in Comm.,SAC- 5:74{83, Oct [0] J. S. C. Chen and T. E. Stern, "Throughput analysis, optimal buer allocation, and trac imbalance study of a generic nonblocking packet switch," IEEE Journal on Selected Areas in Comm., SAC-9, 3:439{449, 99. [] O. J. Boxma, "On a tandem queueing model with identical service times at both counters, I," Adv. Appl. Prob., ():66{643, November 979. [] O. J. Boxma, "On a tandem queueing model with identical service times at both counters, II," Adv. Appl. Prob., ():644{659, November 979. [3] S. B. Calo, "Message delays in repeated-service tandem connections," IEEE Trans. on Comm., COM-9:670{678, May 98. [4] I. Cidon, A. Khamisy and M. Sidi, "Analysis of Queueing Displacement Using Switch Port Speedup," CC PUB 70, October /97 $ IEEE