Autotuning of Digitally Controlled Buck Converters based on Relay Feedback

Transcription

1 Autotuning of Digitally Controlld Buck Convrtrs basd on Rlay Fdback W. Stfanutti, P. Mattavlli DIEGM Univrsity of Udin Italy S. Saggini ST Microlctronics Industrial & Powr Convrsion Division Cornardo (MI)-Italy M. Ghioni DEI Politcnico of Milano Italy Abstract This papr proposs a simpl autotuning tchniqu for digitally controlld dc-dc synchronous buck convrtrs. Th proposd approach is basd on th rlay fdback mthod and introducs prturbations on th output voltag during convrtr soft-start. By using an itrativ procdur, th tuning of PID paramtrs is obtaind dirctly by including th controllr in th rlay fdback and by adjusting th controllr paramtrs basd on th spcifid phas margin and control loop bandwidth. A nic proprty of th proposd solution is that output voltag prturbations ar introducd whil maintaining th closd-loop control of th digitally controlld convrtrs. Th proposd algorithm is simpl, rquirs small tuning tims and it is compliant with th cost/complxity constraint of intgratd digital ICs. Exprimntal invstigation has bn prformd using discrt componnts, implmnting th digital control in a Fild Programmabl Gat Array (FPGA). Simulation and xprimntal rsults of a.5v 5 A synchronous buck convrtr confirm th ffctivnss of th proposd solution. I. INTRODUCTION Intgratd digital controllrs for Switch-Mod Powr Supplis (SMPS) ar gaining growing intrst, sinc it has bn shown th fasibility of digital controllr ICs spcifically dvlopd for high-frquncy switching convrtrs [-4]. On vry intrsting potntial bnfit is th us of autotuning of controllr paramtrs, so that th dynamic rspons can b st at th softwar lvl, indpndntly of output capacitor filtrs, componnt variations and aging. In ordr to b an intrsting solution, howvr, th autotuning procss should satisfy two important rquirmnts: ) it should not affct convrtr opration undr nominal condition and ) it should b basd on a simpl and robust algorithm whos complxity dos not rquir a significant incras of th silicon ara of th IC controllr. Th first issu may b handld by prforming controllr autotuning during convrtr soft-start, whr thr ar som dgr of frdom for th introduction of output voltag prturbations. Th scond issu is much mor challnging and rquirs th dvlopmnt of ad-hoc autotuning tchniqus spcifically tailord for intgratd digitally-controlld convrtrs. Svral auto-tuning tchniqus for classical rgulator structurs (such as Proportional-Intgral-Drivativ (PID)) hav bn widly discussd in litratur [5-9]. Th grat ffort was motivatd by th fact that PID rgulators ar widly accptd in industrial applications and by th fact that th applications of microcontrollrs and DSPs hav bn rapidly incrasd in powr lctronics/drivs applications, mainly in th mdium/high powr rang. Not, howvr, that most of th xisting solutions ar too complx for small-powr dc-dc convrtrs with intgratd digital controllrs du to th cost/complxity constraints xisting in ths applications. Som rsults of non-paramtric mthods for th on-lin assssmnt of systm dynamics in dc-dc convrtrs ar discussd in [,]; th mthods rportd in [,] ar vry intrsting for convrtr transfr functions idntifications, but thy rquirs opn-loop opration during th idntification procss and complx signal procssing. This papr proposs a simpl autotuning mthod for voltag-mod synchronous buck convrtrs, applid as Point of Load convrtrs (PoLs), by using th rlay fdback [5]. By mans of th rlay control, small oscillations on th output voltag ar gnratd during convrtr soft-start. Basd on th masurmnts of th frquncy and amplitud of th oscillations, th gain and phas of th convrtr transfr function at th oscillation frquncis ar drivd. Instad of stimating th convrtr transfr function at diffrnt frquncis, th papr proposs an itrativ procdur, whr th tuning of PID paramtrs is obtaind dirctly by including th controllr in th rlay fdback and by adjusting th controllr paramtrs basd on th spcifid systm phas margin and loop bandwidth. Th proposd algorithm is simpl and it rquirs small tuning tims. Simulation and xprimntal rsults on a synchronous buck convrtr confirm th ffctivnss and limitations of th proposd solutions. II. BASICS OF AUTOTUNING USING RELAY FEEDBACK Th basic principl of rlay fdback mthod can b xplaind following Fig.. Th convrtr transfr function, which is going to b controlld, dnotd with G(s), is rgulatd firstly using a rlay (s Fig. a). Thus, an oscillation on signal y with priod T u (or angular frquncy ω u) and amplitud a is gnratd (s Fig. b). Th oscillation wavform is almost sinusoidal assuming that th low-pass filtr action of G(s) filtrs th highr harmonics gnratd by th rlay. Th condition for th oscillation to b maintaind is th following N( a) G( jω u ) = ()

2 whr N(a) is th rlay transfr function modld using th dscribing function mthod, i..: 4 D N ( a) = r () π a and D r is th amplitud of th squar-wav gnratd by th rlay. Condition () is also rprsntd in th Nyquist diagram of Fig. c whr G(jω) intrscts -/N(a) and it clarly shows that th systms oscillats whn th phas of G(jω) is -8. Practical implmntation of th schm of Fig. usually rquirs th introduction of an hystrsis function in th rlay block. In this cas, th dscribing function of th rlay is 4 D N ( a) = r (3) π a ε + jε whr ε is th hystrsis width. This function can b rprsntd as a straight lin paralll to th ral axis, in th complx plan. Th contribution of th imaginary part in (3) is usually vry small, so that th systm still oscillats whn th phas of G(jω) is vry clos to -8. Controllr autotuning is usually obtaind by masuring th oscillation priod T u and amplitud a and thn by driving th PID cofficints using Ziglr-Nichols formulas [5]. This basic approach is, howvr, not vry suitabl for dcdc convrtrs sinc Ziglr-Nichols formulas ar quit consrvativ, thy do not us th a-priori information on th dynamic structur of G(s), usually availabl in dc-dc convrtrs, and thus thy do not usually yild to an optimal dynamic rspons. Th Ziglr-Nichols mthod may b usd as a pr-tunr, but thn manual tuning is ndd to obtain dynamic prformancs satisfactory for highprformanc dc-dc convrtrs. y rf ysp y u + - -Dd r Rlay D+ r d u G() s Fig. (a) - Block diagram of rlay fdback T u Fig. (b) Typical wavforms of rlay fdback a d ddr t t y N( a) dscribing function G( jω u ) Im N( a) G( jω ) = - G( jω ) Fig. (c) Nyquist diagram of G(s) and rlay block III. AUTOTUNING OF PID PARAMETERS FOR BUCK CONVERTERS In voltag-mod synchronous buck convrtr, th transfr function btwn th duty-cycl and th output voltag is simply givn by th scond ordr output filtr, i..: whr vo (s) + sτsr G(s) = = Vin (4) δ(s) ξ s + s + ω ω ω o = LC, ξ = ( R dson + Rsl + Rsr ) Zo, Z o = L C (s Fig. ). Th quivalnt sris rsistanc R sr of C is nglctd in th cas of cramic capacitors, whil it plays an important rol in th cas of lctrolytic capacitors. Th cas of non-ngligibl ESR is usually lss critical from th PID autotuning point of viw, sinc th drivativ action on th high-frquncy rang is not ndd and a simplr PI (Proportional-Intgral) controllr structur is sufficint for th voltag loop rgulator. For th purpos of xplanation, th gnral cas of PID control is considrd. In th cas of lctrolytic capacitors, th autotuning tchniqu sts th drivativ gain to a ngligibl valu. Th PID rgulator structur can b xprssd as K PID(z) = z = K I PID + K P o o zroat τ z zroat τ z ( b z z ) ( b 443 z z ) z 4 PD(z) + K D ( z ) = PI(z) whr th PID transfr function has bn dcomposd so as to highlight th intgral trm (-z - ) and two zros, having tim constants τ z and τ z. Th most gnral approach for controllr autotuning may b dividd in thr phass. In th first phas (dnotd Phas A), th systm is forcd to oscillat at th rsonant frquncy ω o and th first zro (τ z ) is st at th rsonant frquncy. In th scond phas (dnotd Phas B), an itrativ procdur is usd to tun th scond zro (τ z ) so as to satisfy th spcification on th dsird phas margin and in th third and last phas (dnotd Phas C) th gain K PID of th PID control is tund so as to impos th dsird bandwidth. A st of simplifications of this gnral R (5)

3 Fig. Basic schm of th proposd autotuning schm procdur is possibl, if a priori knowldg of som convrtr paramtrs is availabl. A. Rsonant frquncy idntification and tuning of τ z In th first phas, th systm is forcd to oscillat at th rsonant frquncy ω o. As shown in Fig., this is simply obtaind by adding an intgral trm in th fdback loop so that transfr function G(s) and th intgrator givs -8 xactly at th rsonanc angular frquncy ω o. Taking into account th possibl calculation dlay of th digital controllr and th Zro-Ordr-Hold (ZOH) sampling of th convrtr transfr functions, th oscillation is usually just bfor th rsonant frquncy. Sinc th systm is xcitd closd to th rsonant angular frquncy ω o, in som applications it may b important to add an activ damping of th LC filtr so as to limit th amplitud of th oscillations on th output voltag. This may b ndd in th cas of lightly dampd LC output filtr. Activ damping is simply obtaind introducing a small drivativ action, as rportd in Fig.. Sinc th goal is only to avoid undsird amplification at th rsonant frquncy, a rough stimation of th damping cofficint k s is sufficint for wid paramtr variations on th LC filtr. Following Fig., th output of phas A is th stimation of LC angular rsonanc frquncy ω o and th masurmnt of th transfr function (4) at th rsonanc frquncy. Basd on this stimation, th zro at τ z has bn st to b at th rsonanc frquncy ω o (i.. τ z =/ ω o ). If th zro du to th output capacitor is known, thn it is possibl to dirctly complt th PID (or PI) tuning. For xampl, in th cas of cramic capacitor it is possibl to st th scond zro τ z at th sam frquncy (i.. τ z =τ z =/ ω o ) and thn tun th gain of th PID according to th spcifid control loop bandwidth ω *. Such simplifications, which may b vry usful in som spcific applications, ar not hr considrd. As a gnral approach, w prfrrd to add a scond phas of tuning (in Fig dnotd Phas B) in ordr to optimiz systm rspons and to propos a tchniqu which is indpndnt of output capacitor bhavior. Morovr, th placmnt of both zros τ z and τ z at /ω o may b consrvativ in th cas th LC rsonant angular frquncy ω o is much lowr than th dsird control loop bandwidth ω * or it may giv small phas margin in th cas ω o is vry clos to ω *. In this lattr cas, which is, howvr, not vry common, th zro τ z should b placd blow ω o so as to nsur th lading action at th dsird bandwidth ω *. B. Itrativ tuning of τ z basd on phas margin spcification During phas B, th zro τ z is itrativly tund so as to giv th spcifid oscillation frquncy ω osc. Sinc th systm oscillats whn th loop gain is -8, an additional low-pass filtr F(z) (s Fig. ) is ndd in ordr to forc th dsird phas margin m Φ at th dsird ω *. In fact, whn th systm oscillats at angular frquncy ω osc du to th rlay fdback, w hav i ω ω arg( ( sw i )) + arg( ( F PD sw )) + i ω ω + arg( ( sw i )) + arg( ( PI G sw d )) = π whr G d (z) is th zro-holdr-hold sampling of G(s). Thus, whn ω osc = ω *, th closd loop systm has th dsird (6)

4 phas margin m Φ sinc (6) can b rarrangd as: arg(pd( iωsw + arg(g ( )) + arg(pi( d iωsw iωsw )) + )) = π + m If ω osc > ω *, th lagging phas of F(z) is gratr that m Φ (i.. iω sw arg( F( )) < mφ ) and th systm phas margin is gratr than th spcifid valu m Φ (i.., th lagging phas of PI(z) is lowr than th corrct valu). Thus, th valu of zro τ z has to b rducd. Convrsly, if ω osc < ω * th lagging phas of F(z) is lowr that m Φ (i.. i ω sw arg( F( )) > mφ ) and th systm phas margin is lowr than th spcifid valu m Φ, and thus, th valu of zro τ z has to b incrasd. This itrativ procdur, using th bisction mthod, is a simpl but ffctiv way to find th corrct solution. W found that just a fw itrations (3-4) ar ndd to obtain a good approximation of th corrct valu. C. Tuning of controllr gain basd on spcifid bandwidth Onc th itration procss is ovr, th gain of th PID (K PID ) is calculatd from th attnuation introducd by th low-pass filtr F(z) and th gain calculatd from th dscribing function of rlay, i..: K PID r ( ) osc ( k ( j ω osc T SW ) Φ (7) 4 D k = F (8) π V ) whr V osc (k) is th amplitud of th oscillations during th last itration, valuatd as: π Vosc( k) = Nsamp N samp h= rf vo( h) vo whr N samp is th numbr of sampls ovr th masurd intrval. IV. SIMULATION RESULTS Th proposd solution has bn vrifid using simulation tools on a synchronous buck dc-dc convrtrs having th following paramtrs: V in =5 V, V o =.5 V, L=3 µh, C=6 µf, f sw = khz. In th simulation modl, th digital control has bn implmntd with a sampling frquncy qual to th switching frquncy and with ngligibl calculation dlay. Th proposd autotuning is prformd during convrtr soft-start. Mor prcisly, th output voltag is kpt blow th nominal valu during th autotuning procdur. For xampl, in this papr w hav st that th autotuning is prformd at th 8% of th nominal voltag. Th first stp is to achiv 8% of output nominal voltag with a spcifid ramp: to nsur systm stability, in this phas th voltag loop is closd with th rlay and intgrator insrtd. Th slop of th output voltag ramp can b adjustd varying th rlay amplitud and th intgral constant. Whn th output voltag rachs th 8% of th nominal valu, thn th (9) autotuning procdur is startd. Dtails of th autotuning mthod ar rportd in Fig. 3, which highlights th phass A and B and th itration procss during phas B. During Phas A, bcaus th loop gain is unknown, th first D r amplitud must b chosn small nough to avoid ovrvoltags and succssivly adjustd according to th following algorithm: V Dr ( k) ( ) () = osc max Dr k Vosc( k ) whr V oscmax is th dsird oscillation amplitud, V osc (k-) is th oscillation amplitud and D r (k-) is rlay amplitud both at instant k-. Vry small oscillations amplituds may compromis th corrctnss of frquncy stimation bcaus nd ordr ffcts and nois disturbancs. Morovr, stabl masurmnt of th oscillation amplitud rquirs an obsrvation intrval qual to svral oscillation priods (typically 4-6), both for transint adjustmnt and nois rjction. At th nd of phas A, τ z is st at /ω o. For ach itration during phas B, th amplitud of D r nds to b adjustd as dscribd in phas A. Instad of starting from a vry small valu, at ach chang of τ z, it is possibl to stimat th initial valu of D r that nsurs th dsird oscillations amplitud as follows: Dr ( k) = D ( k ) r τ z τ z ( k ) f c ( k) f ( k ) osc () This algorithm is basd on th assumption that th PID rgulator has - db/dc at th cross-ovr frquncy and that th systm oscillats nar th cross-ovr frquncy at th nxt stp. Th purpos of this algorithm is to compnsat th chang of loop gain whn th nd zro is moving. Howvr, w found that an altrnativ and much simplr solution is to halv D r amplitud at ach chang of τ z and thn to apply algorithm (). In Fig. 4 it is shown th dtail of bod plot at cross-ovr τ z = 35µs τ z = µs 3 τ z = 67.5µs 4 τ z = 5.µs x -3 Phas A Phas B f rs stimation Itrativ autotuning of st of τ z τ z 3 4 Fig. 3 Convrtr soft-start with th proposd auto-tuning procdur

5 [db] [Dg] Loop Gain O + * x τ z = 35µs τ z = µs τ z = 67.5µs τ z = 5.µs [A] Loop Phas frquncy of th systm loop at ach itration whn τ z is tund (phas B): this figur highlights th chang of oscillating frquncy at vry chang of τ z. Th loop gain plottd is calculatd taking in account th gain introducd by th dscribing function of th rlay. Th autotuning has bn prformd with a dsird crossovr frquncy qual to 6.6 khz and phas margin qual to 45. Fig. 5 and 6 rport th convrtr dynamic bhavior following a load stp chang with th output capacitor qual to µf and 6 µf, rspctivly. Not that, in spit of using th doubl of th output capacitor, th tim rspons to load changs rmains almost th sam and th dynamic bhavior is wll dampd, vrifying th ffctivnss of th proposd solution. Fig. 8 shows th comparison btwn final valus of controllr paramtrs (τ z, τ z and K PID ) for th cas of tantalum capacitors and cramic capacitors. In th cas of tantalum capacitors, du to th prsnc of th zro τ sr within th control bandwidth (placd at khz in our cas), th nd zro of th PID rgulator is placd at high frquncis and, thus, it can b nglctd. Tabl I Autotuning rsults with diffrnt output capacitors f z f z K PID m φ f c Cramic capacitors Tantalum capacitors 3.74 khz 4.6 khz [Hz] Fig. 4 Dtails of gain and phas loop bod plot at oscillating frquncy during Phas B 3.83 khz 9 khz khz 6.6 khz i L Fig. 6 Load stp chang (I o = A 5 A) aftr autotuning with cramic capacitor qual to 6 µf. V. EXPERIMENTAL RESULTS Th proposd autotuning algorithm has bn tstd on a synchronous buck dc-dc convrtr having th following paramtrs: V in =5 V, V o =.5 V, L=3 µh, C=6 µf for cramic capacitors and C=66 3 µf for tantalum capacitors, f sw = khz. Th digital control has bn implmntd in an FPGA (th EPC dvic, a mmbr of Cyclon family by Altra). Du to th ADC convrsion tim, th digital control is charactrizd by a dlay btwn sampling and DPWM updat qual to half-switching priod dlay; thus, th achivabl dynamic prformancs has bn limitd to /5 of th switching frquncy. Fig. 7 shows th output voltag during autotuning phas with cramic capacitors qual to µf imposing a loop bandwidth of f sw /5 and phas margin 3. As a rsults of th autotuning procss, f z =.85 khz and f z =5.6 khz. Th convrtr dynamic bhavior following a stp load currnt is rportd in Fig. 8. In ordr to vrify th ffctivnss of th proposd autotuning procdur, th output capacitor valu has bn dcrasd from µf to 6µF. Th autotuning procss hav st th following control paramtrs: f z =3.7 khz and f z =3.36 khz. As rportd in Fig. 9, th dynamic bhavior is almost unchangd, as thortically forsn. Th voltag drop is, of cours, biggr du to th dcrasd capacitor valu. Not that th incrasd voltag drop is not linarly dpndant on th invrs of th output capacitor du to th control dlay ffct [A] i L Fig. 5 Load stp chang (I o = A 5 A) aftr autotuning with cramic capacitor qual to µf. Fig. 7 Convrtr soft-start with auto-tuning (v O mv/div, tim ms/div)

6 Th sam procdur has bn applid to tantalum capacitors imposing a loop bandwidth of f sw /5 and phas margin 6. For C=3 µf, th autotuning procdur givs f z =.7 khz and f z =3.4 khz. For C=66 µf, th autotuning procdur givs f z =4. khz and f z =3 khz. In this cas, th drivativ contribution of th PID rgulator is usd for th compnsation of control dlay. Th convrtr dynamic bhavior following a load stp up is rportd in Figs. - and thy confirm th ffctivnss of th proposd mthod. 9mV VI. CONCLUSIONS This papr has proposd an autotuning tchniqu for digitally controlld dc-dc synchronous buck convrtrs basd on th rlay fdback. In th proposd solution, mv Fig. 8 Stp load variations with µf cramic capacitors ( mv/div, 5A/div, tim 5µs/div) 8mV Fig. 9 Stp load variations with 6µF cramic capacitors ( mv/div, 5A/div, tim - 5µs/div) 5mV Fig. Stp load variations with 3µF tantalum capacitors ( mv/div, 5A/div, tim - 5µs/div) Fig. Stp load variations with 66µF tantalum capacitors: ( mv/div, 5A/div, tim - 5µs/div) output voltag prturbations hav bn introducd during convrtr soft-start, whil maintaining th closd loop opration of th convrtr. By using an itrativ procdur, th tuning of PID paramtrs is obtaind dirctly by including th controllr in th rlay fdback and by adjusting th controllr paramtrs basd on th spcifid phas margin and control loop bandwidth. Exprimntal rsults hav vrifid th prformanc of th proposd solution. ACKNOWLEDGMENT Th authors would lik to thank Dr. William Scagntti for his support in th xprimntal activitis and prof. M. Zigliotto for his contribution on th proposd itrativ procdur. REFERENCES [] B.J. Patlla, A. Prodic, A. Zirgr, D. Maksimović, High-frquncy Digital Controllr IC for dc/dc Convrtrs, IEEE Trans. on Powr Elctronics, Vol. 8, No., January 3, pp [] J. Xiao, A.V. Ptrchv, S.R. Sandrs, Architctur and IC implmntation of a digital VRM controllr, IEEE Trans. on Powr Elctronics, Vol. 8, No., January 3, pp [3] C. Kranz, Complt Digital Control Mthod for PWM dc-dc Boost Convrtr IEEE Powr Elctronics Confrnc 3 (PESC 3), Acapulco, Mxico, Jun 3. [4] S. Saggini, M. Ghioni, A. Graci, An innovativ digital control architctur for low-voltag, high-currnt dc-dc convrtrs with tight voltag rgulation IEEE Trans. on Powr Elctronics, vol. 9, January 4, pp. -8. [5] K. J. Åström, T.Hagglund, Automatic tuning of PID controllrs, Instrumnt Socity of Amrica, (ISBN ), 988. [6] K. J. Åström and B. Wittnmark. Computr-Controlld Systms. Prntic-Hall(ISBN ), 99. [7] B. Johansson and M. Lnlls, Possibilitis of obtaining small-signal modls of DC-to-DC powr convrtrs by mans of systm idntification, Tlcommunications Enrgy Confrnc, INTELEC,, pp [8] Yang Quan Chn; ChuanHua Hu; Moor, K.L Rlay fdback tuning of robust PID controllrs with iso-damping proprty 4 nd IEEE Confrnc on Dcision and Control, Vol. 3,, 9- Dc. 3, pp [9] A. Lva PID autotuning algorithm basd on rlay fdback IEE Procdings of Control Thory and Applications, Vol. D4, no. 5, Spt. 993, pp [] B. Miao, R. Zan, D. Maksimovic, A Modifid Cross-Corrlation Mthod for Systm Idntification of Powr Convrtrs with Digital Control IEEE Powr Elctronics Spcialist Confrnc (PESC4), Aachn, 4. [] B. Miao, R. Zan, D. Maksimovic. Practical On-Lin Idntification of Powr Convrtr Dynamic Rsponss, IEEE Applid Powr Elctronics (APEC 5), Austin (TX), March 5.