Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002
Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-submicron effects Future trends
The Diode B Al A SiO 2 p n Cross-section of pn-junction in an IC process A p n B One-dimensional representation Al A B diode symbol Mostly occurring as parasitic element in Digital ICs
Depletion Region hole diffusion electron diffusion p n (a) Current flow. hole drift electron drift Charge Density - + x Distance (b) Charge density. Electrical Field x (c) Electric field. Potential V -W 1 W 2 x (d) Electrostatic potential.
Diode Current
Forward Bias p n (W 2 ) p n0 L p n p0 p-region -W 1 0 W 2 n-region x diffusion Typically avoided in Digital ICs
Reverse Bias p n0 n p0 p-region -W 1 0 W 2 n-region x diffusion The Dominant Operation Mode
Models for Manual Analysis V D + I D = I S (e V D/ T 1) V D + + I D V Don (a) Ideal diode model (b) First-order diode model
Junction Capacitance
Diffusion Capacitance
I D (A) Secondary Effects 0.1 0 0.1 25.0 15.0 5.0 0 5.0 V D (V) Avalanche Breakdown
Diode Model R S + V D - I D C D
SPICE Parameters
What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S R on D
The MOS Transistor Polysilicon Aluminum
MOS Transistors - Types and Symbols D D G G S NMOS Enhancement D NMOS S Depletion D G G B PMOS S Enhancement S NMOS with Bulk Contact
Threshold Voltage: Concept S - V GS + G D n+ n+ n-channel p-substrate Depletion Region B
The Threshold Voltage
The Body Effect 0.9 0.85 0.8 0.75 0.7 V T (V) 0.65 0.6 0.55 0.5 0.45 0.4-2.5-2 -1.5-1 -0.5 0 V BS (V)
I D (A) Current-Voltage Relations A good ol transistor -4 x 10 6 VGS= 2.5 V 5 4 Resistive Saturation VGS= 2.0 V 3 2 V DS = V GS - V T VGS= 1.5 V Quadratic Relationship 1 VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V DS (V)
Transistor in Linear S V GS G V DS D I D n + V(x) + n + L x p-substrate B MOS transistor and its bias conditions
Transistor in Saturation V GS G V DS > V GS - V T S D n+ - V GS - V T + n+ Pinch-off
Current-Voltage Relations Long-Channel Device
A model for manual analysis
I D (A) Current-Voltage Relations The Deep-Submicron Era 2.5 x 10-4 2 Early Saturation VGS= 2.5 V 1.5 VGS= 2.0 V 1 VGS= 1.5 V Linear Relationship 0.5 VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V DS (V)
u n (m/s) Velocity Saturation u sat = 10 5 Constant velocity Constant mobility (slope = µ) c = 1.5 (V/µm)
Perspective I D Long-channel device V GS = V DD Short-channel device V DSAT V GS - V T V DS
I D (A) I D (A) I D versus V GS 6 x 10-4 2.5 x 10-4 5 4 quadratic 2 1.5 linear 3 2 1 1 0 0 0.5 1 1.5 2 2.5 V GS (V) Long Channel 0.5 quadratic 0 0 0.5 1 1.5 2 2.5 V GS (V) Short Channel
I D (A) I D (A) I D versus V DS 6 x 10-4 5 4 VGS= 2.5 V Resistive Saturation VGS= 2.0 V 2 1.5-4 2.5 x 10 VGS= 2.5 V VGS= 2.0 V 3 2 V DS = V GS - V T VGS= 1.5 V 1 VGS= 1.5 V 1 VGS= 1.0 V 0.5 VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V DS (V) Long Channel 0 0 0.5 1 1.5 2 2.5 V DS (V) Short Channel
A unified model for manual analysis G S D B
I D (A) Simple Model versus SPICE 2.5 x 10-4 V DS =V DSAT 2 1.5 Velocity Saturated Linear 1 0.5 V DSAT =V GT V DS =V GT Saturated 0 0 0.5 1 1.5 2 2.5 V DS (V)
I D (A) A PMOS Transistor 0 x 10-4 VGS = -1.0V -0.2 VGS = -1.5V -0.4-0.6-0.8 VGS = -2.0V VGS = -2.5V Assume all variables negative! -1-2.5-2 -1.5-1 -0.5 0 V DS (V)
Transistor Model for Manual Analysis
The Transistor as a Switch V GS V T S R on I D D V GS = V DD R mid R 0 V DD /2 V DD V DS
The Transistor as a Switch
The Transistor as a Switch
MOS Capacitances Dynamic Behavior
Dynamic Behavior of MOS Transistor G C GS C GD S D C SB C GB C DB B
The Gate Capacitance Polysilicon gate Source n + x d x d W Drain n + L d Top view Gate-bulk overlap t ox Gate oxide n + L n + Cross section
Gate Capacitance G G G S C GC C GC C GC D S D S D Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off
Gate Capacitance WLC ox C GC WLC ox C GC 2WLC ox WLC ox 2 C GC B C GCS = C GCD WLC ox 2 C GCS C GCD 3 V GS 0 V DS /(V GS -V T ) 1 Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation
Gate Capacitance (F) Measuring the Gate Cap I V GS 10 9 8 7 6 5 4 3 3 10 2 16 2 2 2 2 1.52 1 2 0.5 0 0.5 1 1.5 2 V GS (V)
Diffusion Capacitance Channel-stop implant N A 1 Side wall W Source N D Bottom x j L S Side wall Substrate N A Channel
Junction Capacitance
Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest
Capacitances in 0.25 mm CMOS process
The Sub-Micron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic Resistances
Threshold Variations V T V T Long-channel threshold Low V DS threshold Threshold as a function of the length (for low V DS ) L V DS Drain-induced barrier lowering (for low L)
I D (A) Sub-Threshold Conduction 10-2 10-4 Linear The Slope Factor I D ~ I 0 e qv nkt GS, n 1 C C D ox 10-6 10-8 Quadratic S is DV GS for I D2 /I D1 =10 10-10 Exponential 10-12 V T 0 0.5 1 1.5 2 2.5 V GS (V) Typical values for S: 60.. 100 mv/decade
Sub-Threshold I D vs V GS qvgs nkt I D I0e 1 e qv kt DS V DS from 0 to 0.5V
Sub-Threshold I D vs V DS I D I 0 e qv nkt GS 1 e qv kt DS 1 V DS V GS from 0 to 0.3V
Summary of MOSFET Operating Regions Strong Inversion V GS > V T Linear (Resistive) V DS < V DSAT Saturated (Constant Current) V DS V DSAT Weak Inversion (Sub-Threshold) V GS V T Exponential in V GS with linear V DS dependence
Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S D W R S R D Drain
Latch-up
Future Perspectives 25 nm FINFET MOS transistor