Hex inverter with open-drain outputs

Similar documents
74LVC07A-Q100. Hex buffer with open-drain outputs

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

The 74LVC10A provides three 3-input NAND functions.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

2-input EXCLUSIVE-OR gate

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.

The 74LV08 provides a quad 2-input AND function.

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

Octal bus transceiver; 3-state

Dual buffer/line driver; 3-state

74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

The 74LV32 provides a quad 2-input OR function.

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

The 74LV08 provides a quad 2-input AND function.

74HC30-Q100; 74HCT30-Q100

Dual buffer/line driver; 3-state

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74LVC32A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad 2-input OR gate

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

74HC2G08-Q100; 74HCT2G08-Q100

74LVC541A-Q100. Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

The 74AXP1G04 is a single inverting buffer.

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

74AHC1G00; 74AHCT1G00

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74LVC126A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74HC32-Q100; 74HCT32-Q100

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

74LVC1G125-Q100. Bus buffer/line driver; 3-state

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

74AHC30-Q100; 74AHCT30-Q100

74HC1G32-Q100; 74HCT1G32-Q100

The 74AUP2G34 provides two low-power, low-voltage buffers.

74LVC14A-Q100. Hex inverting Schmitt trigger with 5 V tolerant input

74HC1G02-Q100; 74HCT1G02-Q100

Low-power triple buffer with open-drain output

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

Octal buffer/line driver; 3-state

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC03-Q100; 74HCT03-Q100

The 74LVC00A provides four 2-input NAND gates.

Bus buffer/line driver; 3-state

2-input single supply translating NAND gate

74AHC14-Q100; 74AHCT14-Q100

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

74HC08-Q100; 74HCT08-Q100

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74LVC273-Q100. Octal D-type flip-flop with reset; positive-edge trigger

The 74LVC1G02 provides the single 2-input NOR function.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

The 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

74HC153-Q100; 74HCT153-Q100

74AHC2G241; 74AHCT2G241

74AHC541-Q100; 74AHCT541-Q100

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

Low-power configurable multiple function gate

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

74AHC2G126; 74AHCT2G126

7-stage binary ripple counter

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC541; 74HCT541. Octal buffer/line driver; 3-state

Octal bus transceiver; 3-state

74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.

Low-power configurable multiple function gate

4-bit magnitude comparator

74HC365; 74HCT365. Hex buffer/line driver; 3-state

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

Low-power dual Schmitt trigger inverter

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate

Single supply translating buffer/line driver; 3-state

NXP 74HC_HCT1G00 2-input NAND gate datasheet

Triple inverting Schmitt trigger

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

74HC04; 74HCT General description. 2. Features and benefits. 3. Ordering information. Hex inverter

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate

74LVC823A-Q General description. 2. Features and benefits

74AHC1G125; 74AHCT1G125

Low-power buffer with voltage-level translator

8-bit parallel-in/serial-out shift register

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

Dual buffer/line driver; 3-state

74HC2G125; 74HCT2G125

Transcription:

Rev. 6 0 November 20 Product data sheet. General description The provides six inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or or active-high wired-nd functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits 3. Ordering information 5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic Wide supply voltage range from.2 V to 5.5 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7 (.65 V to.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-4F exceeds 2000 V MM JESD22-5-B exceeds 200 V CDM JESD22-C0E exceeds 000 V Specified from 40 C to +85 C and 40 C to +25 C Table. Ordering information Type number Package Temperature range Name Description Version D 40 C to+25 C SO4 plastic small outline package; 4 leads; SOT08- body width 3.9 mm PW 40 C to+25 C TSSOP4 plastic thin shrink outline package; 4 leads; SOT402- body width 4.4 mm BQ 40 C to+25 C DHVQFN4 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body 2.5 3 0.85 mm SOT762-

4. Functional diagram Y 2 2 Y 3 2 2Y 4 2 3 4 2Y 5 3 3Y 6 3 5 6 3Y 9 4 4Y 8 4 9 8 4Y 5 5Y 0 5 0 5Y Y 3 6 6Y mna525 2 6 3 mna526 2 6Y mna527 GND Fig. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one gate 5. Pinning information 5. Pinning 4 V CC terminal index area VCC Y 2 3 6 Y 4 2 3 6 2 3 2 6Y 2 3 2 6Y 2Y 3 3Y 4 5 6 0 9 5 5Y 4 2Y 3 3Y 4 5 GND () 0 6 9 7 8 5 5Y 4 GND 7 8 4Y GND 4Y 00aae245 00aac96 Transparent top view () This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO4 and TSSOP4 Fig 5. Pin configuration for DHVQFN4 Product data sheet Rev. 6 0 November 20 2 of 4

5.2 Pin description Table 2. Pin description Symbol Pin Description, 2, 3, 4, 5, 6, 3, 5, 9,, 3 data input Y, 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 0, 2 data output GND 7 ground (0 V) V CC 4 supply voltage 6. Functional description Table 3. Function selection [] Input n L H Output ny Z L [] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +6.5 V I IK input clamping current V I <0 50 - m V I input voltage [] 0.5 +6.5 V I OK output clamping current V O <0 50 - m V O output voltage active mode [2] 0.5 +6.5 V high-impedance mode [2] 0.5 +6.5 V I O output current V O =0V tov CC - 50 m I CC supply current - 00 m I GND ground current 00 - m T stg storage temperature 65 +50 C P tot total power dissipation T amb = 40 C to +25 C [3] - 500 mw [] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO4 packages: above 70 C derate linearly with 8 mw/k. For TSSOP4 packages: above 60 C derate linearly with 5.5 mw/k. For DHVQFN4 packages: above 60 C derate linearly with 4.5 mw/k. Product data sheet Rev. 6 0 November 20 3 of 4

8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage.65-5.5 V 9. Static characteristics functional.2 - - V V I input voltage 0-5.5 V V O output voltage active mode 0-5.5 V high-impedance mode 0-5.5 V T amb ambient temperature 40 - +25 C t/ V input transition rise and fall rate V CC =.65 V to 2.7 V 0-20 ns/v V CC = 2.7 V to 5.5 V 0-0 ns/v Table 6. Static characteristics t recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max V IH HIGH-level V CC =.2 V.08 - -.08 - V input voltage V CC =.65 V to.95 V 0.65 V CC - - 0.65 V CC - V V CC = 2.3 V to 2.7 V.7 - -.7 - V V CC = 2.7 V to 3.6 V 2.0 - - 2.0 - V V CC = 4.5 V to 5.5 V 0.7 V CC - - 0.7 V CC - V V IL LOW-level input V CC =.2 V - - 0.2-0.2 V voltage V CC =.65 V to.95 V - - 0.35 V CC - 0.35 V CC V V CC = 2.3 V to 2.7 V - - 0.7-0.7 V V CC = 2.7 V to 3.6 V - - 0.8-0.8 V V CC = 4.5 V to 5.5 V - - 0.30 V CC - 0.30 V CC V V OL LOW-level output voltage V I =V IH or V IL I O = 00 ; - - 0.20-0.3 V V CC =.65 V to 5.5 V I O =4m; V CC =.65 V - - 0.45-0.6 V I O =8m; V CC = 2.3 V - - 0.3-0.75 V I O =2m; V CC = 2.7 V - - 0.4-0.6 V I O =24m; V CC = 3.0 V - - 0.55-0.8 V I O =32m; V CC = 4.5 V - - 0.55-0.8 V I I input leakage current V I =5.5VorGND; V CC =.65 V to 5.5 V - 0. 5-20 I OZ I OFF OFF-state output current power-off leakage current V I =V IH ; V O = 5.5 V or GND; - 0. 0-20 V CC =.65 V to 5.5 V V I or V O = 5.5 V; V CC =0V - 0. 0-20 Product data sheet Rev. 6 0 November 20 4 of 4

Table 6. Static characteristics continued t recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max I CC supply current V I =V CC or GND; I O =0; - 0. 0-40 V CC = 5.5 V I CC additional supply current per input pin; V I =V CC 0.6 V; I O =0; V CC = 2.7 V to 5.5 V - 5 500-5000 C I input capacitance [] ll typical values are measured at V CC = 3.3 V (unless stated otherwise) and T amb =25 C. 0. Dynamic characteristics V CC = 0 V to 5.5 V; - 5.0 - - - pf V I =GNDtoV CC Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter Conditions 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max t PZL OFF-state to LOW n to ny; see Figure 6 propagation delay V CC =.2 V - 9 - - - ns V CC =.65 V to.95 V 0.5 2.8 5.7 0.5 6.7 ns V CC = 2.3 V to 2.7 V 0.5.9 3. 0.5 4.0 ns V CC = 2.7 V 0.5.8 3.9 0.5 5.0 ns V CC = 3.0 V to 3.6 V 0.5.8 3.7 0.5 5.0 ns V CC = 4.5 V to 5.5 V 0.7.5 2.5 0.7 3.5 ns t PLZ LOW to OFF-state n to ny; see Figure 6 propagation delay V CC =.2 V - 0 - - - ns V CC =.65 V to.95 V 0.5 2.6 5.7 0.5 6.7 ns V CC = 2.3 V to 2.7 V 0.5.4 3. 0.5 4.0 ns V CC = 2.7 V 0.5 2.6 3.9 0.5 5.0 ns V CC = 3.0 V to 3.6 V 0.5 2.2 3.7 0.5 5.0 ns V CC = 4.5 V to 5.5 V 0.6.5 2.6 0.6 3.5 ns C PD power dissipation per buffer; V I =GNDtoV CC [2] capacitance V CC =.65 V to.95 V - 6.5 - - - pf V CC = 2.3 V to 2.7 V - 6.9 - - - pf V CC = 3.0 V to 3.6 V - 7.2 - - - pf [] Typical values are measured at T amb =25 C and V CC =.2 V,.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] C PD is used to determine the dynamic power dissipation (P D in W). P D =C PD V CC 2 f i N+ (C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz C L = output load capacitance in pf V CC = supply voltage in Volts N = number of inputs switching (C L V 2 CC f o ) = sum of the outputs Product data sheet Rev. 6 0 November 20 5 of 4

. Waveforms V I n input V M GND t PLZ t PZL V CC ny output V M V OL V X mna529 Fig 6. Measurement points are given in Table 8 Logic level: V OL is a typical output voltage level that occurs with the output load. The input n to output ny propagation delays Table 8. Measurement points Supply voltage Input Output V CC V M V X < 2.7 V 0.5 V CC V OL + 0.5 V 2.7 V to 3.6 V.5 V V OL + 0.3 V 4.5 V to 5.5 V 0.5 V CC V OL + 0.3 V Product data sheet Rev. 6 0 November 20 6 of 4

V I negative pulse 0 V 90 % V M 0 % t W V M t f t r t r t f V I positive pulse 0 V 0 % 90 % V M t W V M V EXT V CC G V I DUT V O RL RT CL RL 00aae33 Fig 7. Test data is given in Table 9. Definitions for test circuit: R L = Load resistance. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to output impedance Z o of the pulse generator. V EXT = External voltage for measuring switching times. Load circuitry for switching times Table 9. Test data Supply voltage Input Load V EXT V I t r, t f C L R L t PLH, t PHL t PLZ, t PZL t PHZ, t PZH.2 V V CC 2 ns 30 pf k open 2 V CC GND.65 V to.95 V V CC 2 ns 30 pf k open 2 V CC GND 2.3 V to 2.7 V V CC 2 ns 30 pf 500 open 2 V CC GND 2.7V 2.7V 2.5 ns 50 pf 500 open 2 V CC GND 3.0Vto3.6V 2.7V 2.5 ns 50 pf 500 open 2 V CC GND 4.5 V to 5.5 V V CC 2.5 ns 50 pf 500 open 2 V CC GND Product data sheet Rev. 6 0 November 20 7 of 4

2. Package outline SO4: plastic small outline package; 4 leads; body width 3.9 mm SOT08- D E X c y H E v M Z 4 8 Q pin index 2 ( ) 3 θ L p 7 L e b p w M detail X 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 0.25.75 0.0 0.069 0.00 0.004 2 3 b p c D () E () e H () E L L p Q v w y Z.45.25 0.057 0.049 0.25 0.0 0.49 0.36 0.09 0.04 0.25 0.9 0.000 0.0075 8.75 8.55 0.35 0.34 4.0 3.8 0.6 0.5.27 6.2 5.8 0.244 0.228 Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included. 0.05.05 0.04.0 0.4 0.039 0.06 0.7 0.6 0.028 0.024 0.25 0.25 0. 0.0 0.0 0.004 θ 0.7 0.3 o 8 o 0.028 0 0.02 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT08-076E06 MS-02 99-2-27 03-02-9 Fig 8. Package outline SOT08- (SO4) Product data sheet Rev. 6 0 November 20 8 of 4

TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402- D E X c y H E v M Z 4 8 pin index 2 Q ( ) 3 θ 7 e b p w M detail X L p L 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm. 0.5 0.05 0.95 0.80 0.25 0.30 0.9 0.2 0. 5. 4.9 4.5 4.3 0.65 6.6 6.2 0.75 0.50 0.4 0.3 0.2 0.3 0. 0.72 0.38 θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402- MO-53 EUROPEN PROJECTION ISSUE DTE 99-2-27 03-02-8 Fig 9. Package outline SOT402- (TSSOP4) Product data sheet Rev. 6 0 November 20 9 of 4

DHVQFN4: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body 2.5 x 3 x 0.85 mm SOT762- D B E c terminal index area detail X terminal index area e e b 2 6 v M w M C C B y C C y L 7 E h e 4 8 3 9 D h X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () Eh e e L v w y y mm 0.05 0.00 0.30 0.8 0.2 3. 2.9.65.35 2.6 2.4.5 0.85 0.5 2 0.5 0.3 0. 0.05 0.05 0. Note. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT762- - - - MO-24 - - - EUROPEN PROJECTION ISSUE DTE 02-0-7 03-0-27 Fig 0. Package outline SOT762- (DHVQFN4) Product data sheet Rev. 6 0 November 20 0 of 4

3. bbreviations Table 0. cronym CDM DUT ESD HBM MM TTL bbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 4. Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes v.6 200 Product data sheet - v.5 Modifications: Table 6: Conditions column, additional supply current V CC range updated v.5 20024 Product data sheet - v.4 Modifications: Table 7: values added for lower voltage ranges v.4 20080 Product data sheet - v.3 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7, and Table 9: values added for lower voltage ranges. v.3 200327 Product specification - v.2 v.2 20030828 Product specification - v. v. 20000307 Product specification - - Product data sheet Rev. 6 0 November 20 of 4

5. Legal information 5. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 5.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 5.3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Product data sheet Rev. 6 0 November 20 2 of 4

Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia s specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia s standard warranty and Nexperia s product specifications. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Product data sheet Rev. 6 0 November 20 3 of 4

7. Contents General description...................... 2 Features and benefits.................... 3 Ordering information..................... 4 Functional diagram...................... 2 5 Pinning information...................... 2 5. Pinning............................... 2 5.2 Pin description......................... 3 6 Functional description................... 3 7 Limiting values.......................... 3 8 Recommended operating conditions........ 4 9 Static characteristics..................... 4 0 Dynamic characteristics.................. 5 Waveforms............................. 6 2 Package outline......................... 8 3 bbreviations.......................... 4 Revision history........................ 5 Legal information....................... 2 5. Data sheet status...................... 2 5.2 Definitions............................ 2 5.3 Disclaimers........................... 2 5.4 Trademarks........................... 3 6 Contact information..................... 3 7 Contents.............................. 4 For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 0 November 20