The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices Zhiping Yu and Jinyu Zhang Institute of Microelectronics Tsinghua University, Beijing, China yuzhip@tsinghua.edu.cn
Outline The major concerns near the end of MOS scaling What is quantum capacitance (QC) and why has it mostly been ignored in FET compact modeling? Modeling and equivalent circuits for QC Carbon-NanoTube FET (CNT-FET), a classical Example for illustrating QC Compact model for Graphene FET (GFET) and its application in design of a distributed amplifier Conclusions June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 2
Driving Force for Further MOS Scaling It s low power, low voltage, and low gate delay (powerdelay product) From planar to FinFET, and from tunneling FET to novel nano-electronic devices (new channel materials) V ds = V dd 22nm planar V = 0 ds Vdd=0.68V Source: Bohr/Mistry slides, May 2011 3
Important Means to Further MOS Scaling New device structures Gate-All-Around Nanowire (GAA-NW) FETs Tunneling FETs (tfets) Junctionless (JL) FETs New channel materials III-V CMOS, e.g., InAs for nmos and GaSb for pmos on GaAs substrate 2D materials, typical graphene, and emerging MoS 2, WSe 2, black phosphorous (BP), etc. 1D materials, mainly carbon nanotube (CNT) June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 4
Critical Device/Material Parameters to Look At Devices Subthreshold swing (SS): break through the 60mV/dec limit I on and I on /I off ratio Off-state leakage (drain controllability over gate) Channel materials Mobility Density of States (DOS) June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 5
Tunneling FETs and Small SS K. Jeon, SEMATECH/UCB, VLSI 10 source side pmos Features: I on /I off : 10 8 n-i-p on 40nm BOX NiSi source structure High field pocket Recessed source-side silicon SS<60 mv/dec for 3-decades of I D June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 6
CNT-FET and Small Gate Delay J. Appenzeller, IBM, PRL 04 pmos, Vds=-0.5V ambipolar Tunneling thru SB band-to-band tunneling June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 7
Why Need to Model Quantum Capacitance (QC) An accurate total (and especially the intrinsic) gate capacitance is important in evaluating the transistor performance (gate delay, say) C V I delay gate dd D Channel materials are assessed for both mobility and density-of-states (DOS), often there is a trade-off (high m implies low DOS) Nano-electronic (and gate-all-around) devices don t have body contact to their channel. June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 8
QC Is Not New: MOS Capacitor Has DOS Capacitance Having bulk contact to channel q s V GB Q inv q n x dx, C inv / V F t n n e N e n i N N e i C V E g C 2k T B Q inv E E / k T F C B S June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 9
Then, Why Quantum (Capacitance)? First coined by S. Luryi of Bell Labs, APL 88 for 2DEG 2DEG C Qi 1e 2 * 2 qm Ei EF kbt 2D DOS e.g., m*=0.98m 0 for Si m l D. Jin, MS thesis, MIT, 2010 June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 10
Impact of Quantum Capacitance B. Yu, UCSD, T-ED, 08 June 27, 2016 11
Effective Mass of DOS for Different Semiconductors G. Jin, MIT, MS Thesis, 10 Si: 1.08 m 0 GaAs: 0.067 m 0 InAs: 0.026 m 0 In 0.53 Ga 0.47 As: 0.04 m 0 June 27, 2016 12
DOS Dependence on Electronic Energy for 1/2/3D D D D 1 2 2 3 3 ck k 1 0 0 3/2 V 2 m* N E E E 2 3D 2 2 0 c in dispersion relation of E E c k k E E E c c E E and p is the power of k, e.g., p 2 for parabolic k E E 0 k p 1D 2D 3D J. Mintmire PRL 98 D. Jin MIT MS Thesis 10 Wiki June 27, 2016 13
DOS for Nanowire B. Yu, UCSD, T-ED 08 Si nanowire of r = 2.5nm June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 14
Quantum Capacitance (QC): Modeling Approach Ballistic transport assumption: provide knowledge of Fermi level in channel nmos Electron Energy channel carrier density -q U SCF q S S ch D A. Raychowdhury, T-ICCAD 04 A. Rahman, T-ED 04 June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 15
Definition of QC: C q June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 16
QC (cont d): Equivalent Circuit Use charge balance principle to find V ch : C V V Q V V Q V V S G ++ ++ ox G ch S ch S D ch D V G large signal model C ox - - - - V ch D Incremental (small signal) capacitance network V S ch G qs qd C June 27, 2016 ox CqS CqD Vch V C qs C qd ch 17 Q S ox S V V, C, C channel mobile charge Q D C Q Q new circuit symbol V D q for quantum D C ox
Application of QC to tfet Z. Yu, Tsinghua, ICSICT 12 Compared to CH S. Fregonese, TED 09 June 27, 2016 18
Quantum Capacitance in III-V FETs D. Jin, MS thesis, MIT, 2010 1 1 1 q Q i q Q i q Q i EF EC EF Ei Ei EC CQi Ccent, i June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 19
Thermal Emission vs. Band-to-Band Tunneling (BtBT): Band-Pass Filtering Now, consider using BtBT to improve SS J. Knoch, IBM, DRC 05 T E 3/2 4 2 m* E g const exp 3q E, g cnt ox t t ox cnt June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 20
SCE: Short-Channel Effect J. Knoch, IBM Zurich Lab, Phys. Stat. Sol. 08 Look for gate control drain control (DIBL) 0 f long channel or SCE: L vs. is influenced by d June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 21
SS of CNT-FET as a Function of t ox : a Measure of Gate Controllability J. Appenzeller, IBM, PRL 02 pmos large small DIBL J. Knoch, IBM Zurich, PSS 08 120nm SiO 2 20nm HfO 2 June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 22
Charge Pile-up in Channel of CNT-FET through BtBT J. Appenzeller, IBM, PRL 04 (both experiment and simulation by NEGF) S. Fregonese, U Bordeaux, T-ED, 09 Double gates J. Knoch, IBM, PSS 08 pmos June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 23
Dual Forces in Controlling Channel Potential: from Gate and Drain Terminals J. Knoch, IBM, PSS 08 C q 2 8 m* h E 0 f d f C C C 0 ox q d f g d Cox Cq Cd Cox Cq Cd C ox C q g 0 f For an electrostatically well-designed device at off-state C C C ox q, QCL: quantum capacitance limited d C ox C q June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 24
Advantage of 1D Transport for CNT-FET J. Knoch, IBM, PSS 08 C BtBT q, BtBT 0 f 4 2 * 3 Q E g 32 m Eg T WKB de D E f E E WKB 0 f S 1 f qt de D E f E E C T and I T q, BtBT WKB D WKB resulting in delay independent upon S 1 f T WKB June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 25
Dilemma of QCL Regime Gate control is good (channel potential closely follow the gate bias), meaning small SS Yet, the total gate capacitance becomes small, which implies small on current There may be some optimization scheme for minimizing the gate delay Similar situation for JL-FETs June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 26
Compact Model for GFET W. Zhu, Tsinghua, SISPAD 12 Features: Back gate effect on the shift Dirac voltage Reducing S/D resistance by using back gate D. Jimenez, TED 11 June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 27
More on GET Model S. Thiele, U. Ilmenau, JAP 10 C q dq dv sh ch 2 2q qv v ch 2 F Not a constant! June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 28
Central Ideal in GFET Modeling To each position x in the channel belongs a certain local potential V(x) I qn xvxw qn V xv V xw D sheet The voltage across the quantum capacitance, C q, is named as V ch. Density of States (DOS) for graphene D E 2 E E v CV 2 June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 29 sheet Taking E 0, E qv CV F F 8, vf 10 cm/s ch
Self-Consistent Solution of V ch and C q J. Thielte June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 30
Four-Stage GFET Distributed Amplifier H Lyu, Tsinghua, Scientific Report 15 June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 31
Conclusions Besides carrier transport, electrostatics (including quantum effects such as quantum confinement) still plays the most central role in device modeling. It is not certain towards the end of the MOS scaling, new (channel) materials and new device structures will emerge as the mainstream IC technology The case study of quantum capacitance prepares the modeling society for the new challenges. June 27, 2016 MOS-AK Shanghai, June 26-28, 2016 32