Static MOS ircuits l onventional (ratio-less) static MOS» overed so far l Ratio-ed logic (depletion load, pseudo nmos) l ass transistor logic ombinational vs. Sequential Logic In Logic ircuit In Logic ircuit State (a) ombinational (b) Sequential put = f(in) put = f(in, revious In) 1
Static MOS ircuit (Review) t every point in time (except during the switching transients) each gate output is connected to either or V ss via a low-resistive path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static MOS (Review) In1 In2 In3 UN MOS Only = G DN NMOS Only UN and DN are Dual Networks 2
roperties of omplementary MOS Gates (Review) High noise margins: V OH and V OL are at and GND, respectively. No static power consumption: There never exists a direct path between and (GND) in steady-state mode. omparable rise and fall times: (under the appropriate scaling conditions) Influence of an-in and an- on Delay D an-: Number of Gates onnected Every fanout (output) adds two gate capacitances (pmos and nmos) D anin: Quadratic Term due to: 1. Resistance Increasing 2. apacitance Increasing (t phl ) t p = a 1 I + a 2 I 2 + a 3 O 3
ast omplex Gate - Design Techniques Transistor Sizing: s long as an-out apacitance dom inates rogressive Sizing: In N MN L M1 > M2 > M3 > MN M3 3 M2 M1 2 1 ast omplex Gate - Design Techniques Trans is tor Ordering critical path critical path M3 L M1 L M2 2 M2 2 M1 1 M3 3 (a) (b) 4
ast omplex Gate - Design Techniques Improved Logic Design Ratioed Logic Resistive Load R L Depletion Load V T < 0 MOS Load DN DN DN (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary MOS areful de sig needed! 5
Ratioed Logic V OH = Resistive Load R L V OL = R DN R L + R DN Desired: R L >> R DN (to keep noise margin low) DN R DN t LH = 0.69R L L roblems: 1) Static power dissipation 2) Difficult to implement a large resistor, eg 40kΩ resistor (typical value) needs 3200 µ2 of n-diff, i.e. 1,000 transistors! ctive Loads Depletion Load V T < 0 MOS Load DN DN depletion load NMOS Depletion-mode transistor has negative threshold On if V GS = 0 ody effect may be a problem! pseudo-nmos 6
seudo-nmos D L No problems due to body effect N-input gate requires only N transistors Each input connects to only a single transistor, presenting smaller load to preceding gate Static power dissipation (when output is zero) symmetric rise and fall times Example: Suppose minimal-sized gate consumes 1 mw of static power. 100, 000 gate-circuit: 50 W of static power (plus dynamic power)! (half the gates are in low-output state) Effective only for small subcircuits where speed is important, eg address decoders in memories seudo-nmos NND Gate GN D 7
ass-transistor Logic Inputs Switch Network Is this transmission gates necessary? Need a low impedance path to ground when = 0 ND gate No static consumption ass-transistor ased Multiplexer = S + S S S S S M 2 M 1 S GN D S S 8
Transmission Gate XOR 6 transistors only! M2 M1 M3/M4 ase 1: = 1, M3/M4 turned off = ase 1: = 0, M3/M4 turned on = always has a path to or Gnd, hence low impedance node If not, node would be dynamic, requiring refresh due to charge leakage Delay in Transmission Gate Networks 5 5 5 5 In V 1 V i-1 V i V i+1 V n-1 V n 0 0 0 0 (a) In R eq R V eq R eq R 1 V i V i+1 V eq n-1 V n m (b) In R eq R eq R eq Req Req R eq (c) Insert buffers after every m switches 9
Delay in Transmission Gate Networks onsider Kirchoff s Law at node V i V i+1 -V i + V i-1 -V i dv i = R eq R eq dt Therefore, dv i = dt V i+1 + V i-1-2v i R eq ropagation delay can be determined using Elmore delay analysis Delay Optimization Delay can be reduced by adding buffers after m stages (t buf = delay of a buffer) 10
Transmission Gate ull dder i i S Sum Generation o arry Generation i i Setup i NMOS Only Logic: Level Restoring Transistor Level Res torer M n M r X M 2 M 1 dvantage: ullswing Disadvantage: More omplex, Larger apacitance Other approaches: reduced threshold NMOS 11
Single Transistor ass Gate with V T =0 0V 5V 0V 5V WT H OUT OR LEK GE URRE NT S omplimentary ass Transistor Logic ass-transistor Network (a) Inverse ass-transistor Network = =+ = Β Y (b) = =+ = Β Y ND/NND OR/NOR EX O R /N EXO R 12
4 Input NND in L 13