EECS 4 F0 Lecture 7 With major inputs/improvements From Mary-Jane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path.» fan-in of N requires 2N devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.» requires on N + 2 transistors
Dynamic Gate In In 2 In 3 B C Two phase operation Precharge ( = 0) Evaluate ( = ) Dynamic Gate off on!((&b) C) In In 2 In 3 Two phase operation Precharge ( = 0) Evaluate ( = ) B off on C 2
Conditions on put Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. put can be in the high impedance state during and after evaluation ( off), state is stored on Properties of Dynamic Gates Logic function is implemented by the only» number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Nonratioed - sizing of the devices is not important for proper functioning Faster switching speeds» reduced load capacitance due to lower input capacitance (C in )» reduced load capacitance due to smaller output loading (Cout)» no I sc, so all the current provided by goes into discharging 3
Properties of Dynamic Gates, con t Overall power dissipation usually significantly higher than static CMOS» no static current path ever exists between V DD and GND (including P sc )» no glitching» higher transition probabilities» extra load on starts to work as soon as the input signals exceed V Tn, so set V M, V IH and V IL equal to V Tn» low noise margin (NM L ) Needs a precharge clock Power Consumption of Dynamic Gate In In 2 In 3 Power only dissipated when previous = 0 4
Dynamic Power Consumption is Data Dependent Dynamic 2-input NOR Gate 0 B 0 ssume signal probabilities P = = /2 P B= = /2 0 0 0 0 0 Then transition probability P 0 = P out=0 x P out= = 3/4 x = 3/4 Switching activity always higher in dynamic gates! P 0 = P out=0 Issues in Dynamic Design : Charge Leakage V Evaluate Precharge Leakage sources Minimum clock rate of a few khz 5
Solution to Charge Leakage Keeper M kp B! Same approach as level restorer for pass transistor logic Issues in Dynamic Design 2: Charge Sharing B=0 C Charge stored originally on is redistributed (shared) over and C leading to static power consumption by downstream gates and possible circuit malfunction. C B 6
Charge Sharing Example! =50fF C a =5fF B!B B!B C b =5fF C c =5fF!C C C d =0fF Charge Sharing V DD case ) if V out < V Tn V DD = V out () t + C a ( V DD V Tn ( V X )) or M a X V out = V out () t V DD = C a -------V ( C DD V Tn ( V X )) L B = 0 M b C a case 2) if V out > V Tn C b C a V out = V DD -------------------- C + C a L 7
Solution to Charge Redistribution M kp B Precharge internal nodes using a clockdriven transistor (at the cost of increased area and power) Issues in Dynamic Design 3: Backgate Coupling =0 = 2 =0 2 In B=0 Dynamic NND Static NND 8
Backgate Coupling Effect 3 Voltage 2 0 In 2-0 2 Time, ns 4 6 Issues in Dynamic Design 4: Clock Feedthrough B Coupling between and input of the precharge device due to the gate to drain capacitance. So voltage of can rise above V DD. The fast rising (and falling edges) of the clock couple to. 9
Voltage Clock Feedthrough 2.5 Clock feedthrough In In 2.5 In 3 In 4 0.5 In & -0.5 0 0.5 Time, ns Clock feedthrough Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) 0
Cascading Dynamic Gates V In 2 In V Tn 2 V t Only 0 transitions allowed at inputs! Domino Logic In In 2 0 0 0 0 In 4 M kp 2 In 3 In 5
Why Domino? In i In j In i In i In i In j In j In j Like falling dominos! In Domino Manchester Carry Chain P 0 P P 2 P 3 C i,0 G 0 G G 2 G 3 C i,4 2
Domino Manchester Carry Chain 3 3 3 3 3 P 0 P P 2 P 3 4 C i,0 5 G 0 4 3 2 C i,4 G 3 G 2 2 G 3 6 5 4 3 2!(G 0 + P 0 C i,0 )!(G + P G 0 + P P 0 C i,0 ) Properties of Domino Logic Only non-inverting logic can be implemented Very high speed» static inverter can be skewed, only L-H transition» Input capacitance reduced smaller logical effort 3
Logical Effort Inverter pair: In Skewed inverter pair: LE = Logical effort LE = 4
Designing with Domino Logic V DD V DD V DD M r 2 In In 2 In 4 In 3 Can be eliminated! Inputs = 0 during precharge Logical Effort LE = 5
Differential (Dual Rail) Domino! =!(B) off on M kp M kp 0 0!!B B = B Solves the problem of non-inverting logic np-cmos In In 2 In 3 0! In 4 In 5! PUN 0 0 0 2 (to ) Only 0 transitions allowed at inputs of Only 0 transitions allowed at inputs of PUN 6
NOR Logic In In 2 In 3 0! In 4 In 5! PUN 0 0 0 2 (to ) to other s to other PUN s WRNING: Very sensitive to noise! np-cmos dder Circuit! 0 x!!b!b!c x!!!!b!c!b! 0 xc 2 x Sum C 0! x!c B 0 x 0 0 0 B 0 C 0 0 0 B 0 B 0 x C 0!!Sum 0 x 0 7
Dynamic CVS Logic clk clk! In!In In 2!In 2 2 and 2 are mutually exclusive How to Choose a Logic Style Must consider area, performance, power, robustness (noise immunity), ease of design, system clocking requirements, fan-out, functionality, ease of testing Style Comp Static CPL* domino DCVSL* # Trans 8 8 6 + 2 0 * Dual Rail 4-input NND Ratioed? no no no yes Delay Power 2 + clk 3 4 2 3 4 8