0/6/06 Homework # Lecture 8, 9: Sizing and Layout of omplex MOS Gates Reading: hapter 4, sections 4.3-4.5 October 3 & 5, 06 hapter, section.5.5 Prof. R. Iris ahar Weste & Harris vailable on course webpage fter today s lecture you should be able to do all the problems. Prof. ahar will be holding office hours Tuesday from 0- noon to make up for missed office hours today ote that HW# is due this Friday by 5pm 06 R.I. ahar Portions of these slides taken from Professors J. Rabaey, J. Irwin, V. arayanan, and S. Reda Today s lecture Review of last lecture Sizing the inverters in a chain Optimal scaling factor Optimal number of inverters Sizing /OR gates ased on topology of gate balance rise/fall delay ew material for today Topology and transistor sizing of complex gates Optimal layout configuration or complex gates Impact of fanout on delay t p = t p0 ( + ext / int ) Extrinsic capacitance, ext, is a function of the gates being driven by the gate under question (i.e. the fanout) larger fanout larger external load. Re-express the intrinsic capacitance ( int ) in terms of input gate capacitance: int = g, where t p = t p0 ( + ext / g ) = t p0 ( + f/ ) f = ext / g is the effective fanout
0/6/06 Inverter chain Goal is to minimize the delay through an inverter chain In g, The delay of the j th inverter stage is t p,j = t p0 ( + g,j+ /( g,j )) = t p0 ( + f j / ) and t p = t p, + t p, +... + t p, so t p = t p,j = t p0 ( + g,j+ /( g,j )) Out If L and g, are given, we have different optimizations How should the inverters be sized to minimize delay? How many stages are needed to minimize the delay? L Sizing the inverters in the chain fter a bit of calculus, we find that for minimum delay: g,j+ / g,j = g,j / g,j- for j= What does this imply? ll gates have the same effective fanout, f Each gate should be scaled up by the same factor w.r.t. its preceding gate What is the effective fanout for a gate given L and g,? With a bit of algebra and inductive reasoning we find that: f L / g, F = L / g,0 is the overall effective fanout What is the minimum delay through the chain? t t ( F / ) p F p0 γ Optimal number of inverters What is the optimal value for given F? (where F = f ) if the number of stages is too large, the intrinsic delay of the stages dominates if the number of stages is too small, the effective fan-out of each stage dominates t t ( F / γ) p p p0 t / γ f e ( γ / f ) F F ln F 0 For = 0 (ignoring self-loading) = ln (F) and the effectivefan out (tapering factor) becomes f = e =.78 For = (the typical case) the optimum effective fan-out can be solved numerically and turns out to be close to 3.6 Optimum effective fanout 5 4.5 4 3.5 3.5 0 0.5.5.5 3 7 6 5 4 3 0.5.5 3 3.5 4 4.5 5 f Too many stages has a substantial negative impact on delay hoosing f slightly larger than optimum has little effect on delay and reduces the number of stages (and area). ommon practice to use f = 4 (for = ) Fanout of 4 (FO4) rule of thumb delay metric is based on this result
0/6/06 Input pattern effects on delay Input pattern effects on delay L int elay is dependent on the pattern of inputs st order approximation of delay: t p 0.69 R eff L R eff depends on the input pattern L int 0 transition on output: possibilities one input goes low: what is R eff? delay is 0.69 L both inputs go low: what is R eff? delay is 0.69 / L since two p-resistors are on in parallel 0 transition on output: possibility both inputs go high delay is 0.69 L t p 0.69 R eff L dding transistors in series (without sizing) slows down the circuit The rest of today s lecture How do we develop design rules for sizing MOS gates in general? The : ratio for an inverter doesn t necessary work best for other types of gates How should we go about planning the layout of these more complex MOS gates? Gates with multiple inputs means more complex routing How to you order inputs and draw out the active area to minimize total area? Transistor sizing How should MOS and PMOS devices be sized relative to an inverter with equal rise/fall times? L int int L 3
0/6/06 Voltage, V elay dependence on input patterns 3.5.5 0.5 == 0 = 0, = =, = 0 0 0 00 00 300 400-0.5 time, psec -input with MOS = 0.5 m/0.5 m PMOS = 0.75 m/0.5 m L = 0 ff Input ata Pattern elay (psec) ==0 69 =, =0 6 = 0, = 50 == 0 35 =, = 0 76 = 0, = 57 Transistor sizing a complex gate 4 8 4 4 8 4 OUT =!( + ( + )) MOS inverter layout G In Symbolic layout imensionless Positioning is most important In Out Out (a) Layout n p-substrate Field n + p + Oxide (b) ross-section along - G Stick diagram of inverter 4
0/6/06 Standard ell Layout Methodology Layout planning for complex gates Routing channel signals G Want layout to be as dense (area efficient) as possible. Try to realize all MOS and PMOS transistors in unbroken row of devices Requires only single strip of diffusion in both wells areful ordering of inputs is important to help achieve this Use a systematic approach identifying Euler paths What logic function is this? OI logic graph stick layouts of!( ( + )) j =!( ( + )) i PU i j G P G G uninterrupted diffusion strip 5
0/6/06 onsistent Euler path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph i OI logic graph PU Euler path: a path through all nodes in the graph such that each edge is visited once and only once. For a single poly strip for every input signal, the Euler paths in the PU and P must be consistent (the same) j G =!((+) (+)) G P OI Layout raw the Euler paths for this function x =!(a + bc + de) x =!(bc + a + de) G Some functions have no consistent Euler path! =!((+) (+)) hosen Euler path: 6
0/6/06 Homework # Should now have all the background to do all the problems for this homework ue Friday, by 5pm Hardcopy due to me or Marc /gpfs/data/engn600 directory needs to contain all relevant files Let me know if you have any issues meeting this deadline Wire delay models Ideal wire same voltage is present at every segment of the wire at every point in time - at equi-potential only holds for very short wires, i.e., interconnects between very nearest neighbor gates Lumped model when only a single parasitic component (, R, or L) is dominant the different fractions are lumped into a single circuit element When the resistive component is small and the switching frequency is low to medium, can consider only ; the wire itself does not introduce any delay; the only impact on performance comes from wire capacitance river V out R river V out c wire lumped capacitance per unit length good for short wires; pessimistic and inaccurate for long wires Wire elay Models, con t Lumped R model total wire resistance is lumped into a single R and total capacitance into a single good for short wires; pessimistic and inaccurate for long wires istributed R model circuit parasitics are distributed along the length, L, of the wire c and r are the capacitance and resistance per unit length V in r L r L r L r L r L elay is determined using the Elmore delay equation: i = c k r ik k= V V in (r,c,l) V hain network Elmore delay V in r r r i- r i r i- i c c c i- c i c typical wire is a chain network with (simplified) Elmore delay of i = c i r ii = c i r j i Where r j = r + r + + r i V 7
0/6/06 hain etwork Elmore elay V in =c r =c r +c (r +r ) r r r i- r i r i- i c c c i- c i c i =c r +c (r +r )+ +c i (r +r + +r i ) i Elmore delay equation = c i r ii = c i r j If all resistors are equal size, i =c r eq +c r eq +3c 3 r eq + + ic i r eq V Fanin considerations 3 L istributed R model (Elmore delay) t phl = 0.69 R eqn ( + +3 3 +4 L ) (assuming all MOS equally sized) Propagation delay deteriorates rapidly as a function of fanin: quadratically in the worst case. t p as a function of fanin t p (psec) 50 000 750 500 t phl t p quadratic function of fanin Gates with a fan-in greater than 4 should be avoided. t plh 50 linear 0 function of 4 6 8 0 4 6 fanin fanin of gate 8