ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS 1
VDD Vout Vin Ideal VTC Logic 0 = 0 V Logic 1 = VDD 0 2
VOH VDD VOL 0 o.c. Cout For DC steady-state Cout is open circuit. VDD 0 VDD VOL VT0n 3
VOH VDD max output voltage when the logic output is 1 VOL 0 min output voltage when the logic output is 0 VIL max input voltage that can be interpreted as a logic 0 VIH min input voltage that can be interpreted as a logic 1 NOTE: VIL VOL and VIH VOH VDD 4
Slope of VTC or inverter gain 5
Steady-State (Static) Output Voltage Behavior Tj = Ta + ΘP P Pstatic, Pdynamic (oc) (oc) Θ -> Thermal Resistance (oc/w) (W) PDC = Pstatic = VDD ID (Vin = VOH or VOL) V DD P static= [ I D.V in =V OL /*I D.V in =V OH /] 2 Minimum area nmos, pmos transistor layouts limited by design rules 6
Minimum Area (Unit) MOS Transistor Layouts Unit pmos Layout 281 61 31 41 41 21 51 21 31 14 1 51 21 2 Area=28 14 1 =392 1 41 21 2 Unit nmos Layout 201 61 81 31 41 21 41 21 2 2 Area=20 8 1 =160 1 21 Unit Dimensions: L nu=l pu=2 1 ; W nu =W pu =4 1 E2 = 2λ 11 Relevant Design Rules 7
VSB kn' kn' = KPn = A/V2 8
Visual Representation of the Resistive-Load Inverter NMOS driver transistor A ID = 0 C < B 9
CALCULTION OF VOH VDD Vin = 0 < VT0,n => nmos Cut-off Vout = VOH = VDD 10
CALCULTION OF VOL implies Vin = VDD 11
CALCULTION OF VIL -1 VIL @ Vin = VIL 12
CALCULTION OF VIH VIH 13
CALCULTION OF VIH CONT. 14
CALCULTION OF Vth 15
VDD 0 VT0n VDD 16
Take Limit as knrl -> -> VT0n -> VT0n V out.v in=v IL /=V DD -> VT0n 1 k n RL -> VDD - 2 V DD -> 0 V out.v in =V IH /= 3 k n RL -> 0 Vout VDD knrl -> semi-ideal VTC 0 VT0n VDD Vin 17
1 V DD P static.average/= [ I D.V in =0/* I D.V in =V DD /] 2 Vin = 0 P(Vin = 0 ) = 0 Vin = VDD Vout = VOL V DD V OL ID(Vin = 1 ) = IL = RL V DD V OL P(Vin = 1 ).=V DD RL Pstatic (average) 18
VDD Multiplying by RL 6 2.V V OL / W 2.5 0.2/ DD 30 x 10 W 2 R = = 0 L 5 0.2= R [2.5 1/0.2.0.2/ ' 2 6 ] 2 L L k n.2.v 2 DD VLT0n/V OL V OL / 30 x 10.2.5 1/0.2.0.2/ / W R L=2.05 x 105 0 L NO UNIQUE W/L, RL 19
W 5 R L =2.05 x 10 0 L Pstatic (average) [mw] V DD V DD V OL P static.average /= 2 RL 20
VOL = 0.147 V or 8.503 V? 21
Preferred Design 22
SATURATED NMOS ENHANCEMENT-LOAD INVERTER VSB,L 0 VSB,d VSB,L 23
SATURATED NMOS ENHANCEMENT-LOAD INVERTER 24
NMOS DEPLETION-LOAD INVERTER ENH& DEP LOADS REPLACED BY CMOS! 25
QUICK REVIEW Visual Representation of the NMOS Resistive-Load Inverter driver transistor A ID = 0 C < B 26
QUICK REVIEW VDD 0 VT0n VDD 27
QUICK REVIEW W 5 R L =2.05 x 10 0 L Pstatic (average) [mw] V DD V DD V OL P static.average /= 2 RL 28
=> VGSp = Vin - VDD => VDSp = Vout - VDD IDn = IDp 29
Visual Representation of the CMOS Inverter A Vout A E V OH =V DD -1 LIN LIN & OFF SAT V in+v T0n Vout = Vin - VT0n E SAT LIN LIN & V in,v DD *V T0p OFF -VT0p V OL=0 -VT0n Vout = Vin - VT0p -1 VT0n V IL V th V DD V IH VDD+VT0p Vin 30
Visual Representation of the CMOS Inverter Vout A E V OH =V DD -1 SAT & SAT -1 V th V IL SAT SAT -VT0p VT0n Vout = Vin - VT0n LIN LIN & SAT V OL=0 -VT0n Vout = Vin - VT0p LIN LIN & SAT V DD V IH VDD+VT0p Vin 31
IDn = IDp Vout = Vin - VT0p -1 Vout = Vin - VT0n V th V T0p V th V th V T0n V out = (iff λ = 0) V in -1 -VT0n V th V IL V IH V DD 32
IDn = IDp = 0 0= IDn = IDp = 0 =0 33
IDn = IDp Eq.(1) 34
(1) Eq.(1) (and set Vin = VIL) ' n ' p (-1) VIL VIL k W k W d V out. / 2.V in V T0n /=. / [2.V out V DD /*2.V in V DD V T0p / ] 2 L n 2 L p d V in d V out (-1) [ 2.V out V DD / ] d V in Eq.(2) SOLVE Eq. (1) and Eq. (2) for Vout and VIL or use simulation. 35
IDn = IDp 36
Eq.(3) Eq.(4) SOLVE Eq. (3) and Eq. (4) for Vout and VIH or use simulation. 37
IDn = IDp 38
Setting for Vin = Vth and solving for Vth Eq.(5) where k 'n.w / L/n 2n.W / L/n k R= ' = k p.w / L/ p 2 p.w / L/ p RECALL THAT 2n,2 p Usually Ln = Lp is set to min L: k 'n.w / L/n 2n W n k R= ' = k p.w / L/ p 2 p W p 39
DESIGN OF CMOS INVERTERS V T0n * V th = - 1.V DD *V T0p / kr - 1 1* kr Solving Eq.(5) for kr If Vth is Eq.(5) Eq.(5) V DD *V T0p V th k R =. / V th V T0n 2 Important design Eq. for CMOS inverter VTC. 1 ideal Vth set to V th =V th.ideal /= 2 V DD 0.5V DD *V T0p 2 2n.W / L/n k R=. /= 0.5 V DD V T0n 2 p.w / L/ p Symmetric CMOS Inverter W p 2n W n. /=. / V VT0n = -V = -VV =>=(k )symmetric =1.k=> / =1 If Vand and V = V If,th(ideal) also T0p T0 R R symetric th(ideal) T0n T0p T0 Lp 2 p Ln 40
Vth vs. 1/kR Vth (volts) 1 2p W p = k R 2n W n V th = where Ln = Lp 1/kR - 1 V T0n *.V DD *V T0p / kr 1* - 1 kr VDD = 5V; VT0n = - VT0p = 1 V 41
Symmetric CMOS inverter Vth(ideal) and VT0n = - VT0p = VT0 =>.k R /symetric =1.W / L/ p 2.52.W / L/n FROM Eq. (1) and Eq. (2) FROM Eq. (3) and Eq. (4) Symmetrical 42
DERIVE: for Symmetric CMOS Inverter Symmetric CMOS inverter: Vth = VDD/2, VT0n = - VT0p = VT0 and kr = 1 Eq.(1) Eq.(2) 1 => V IL =V out 2 V DD Substitute V out =V IL * 1 V DD, V = V and Sym-Inv Cond. into Eq.(1), i.e. in IL 2 V 2IL 2V IL V T0 *V 2T0 1.=2 V 2IL 2V IL V DD *2 V IL V T0 V IL V DD *V 2DD V T0 V DD V 2IL *V IL V DD V 2DD 4 3 2 2 V IL V DD 4 V IL V T0 = V T0 V T0 V DD * V 2DD 4 3 V IL.2 V DD 4V T0 /= V 2DD V T0 V DD V 2T0 V = 1.3V DD *2V T0 /.V DD 2V T0 / QED IL 4 8 V 2V DD T0 43
EXAMPLE: Compute the noise margins for a symmetric CMOS inverter has been designed to achieve Vth = VDD/2, where VDD = 5 V and VT0n = - VT0p = 1 V. V DD 5 2 3 2 NM H =V OH V IH =V DD. V DD V T0 /= V DD * V T0 =2.125V 8 8 8 8 0 3 2 3 2 NM L =V IL V OL=V IL = V DD * V T0 = V DD * V T0 =2.125V 8 8 8 8 RECALL (with VDD = 5 V) 1. NMH, NML > VDD/4 = 1.25 V 2. Ideal NM => NMH = NML = 2.5 V > VDD/2 44
Pstatic Pstatic = 0 45
If the inverter cell is part of a standard cell library, it will adhere to the cell layout protocols. Smaller Area Layout 46
VDD Vout > - VT0p Pstatic > 0 47