PHM21NQ15T. TrenchMOS standard level FET

Similar documents
PHD110NQ03LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1.

µtrenchmos standard level FET Low on-state resistance in a small surface mount package. DC-to-DC primary side switching.

N-channel µtrenchmos ultra low level FET. Top view MBK090 SOT416 (SC-75)

PMV40UN. 1. Product profile. 2. Pinning information. TrenchMOS ultra low level FET. 1.1 Description. 1.2 Features. 1.

PHP/PHB174NQ04LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1.

PHP/PHB/PHD55N03LTA. TrenchMOS Logic Level FET

PHP/PHB/PHD45N03LTA. TrenchMOS logic level FET

PMN40LN. 1. Description. 2. Features. 3. Applications. 4. Pinning information. TrenchMOS logic level FET

PMV56XN. 1. Product profile. 2. Pinning information. µtrenchmos extremely low level FET. 1.1 Description. 1.2 Features. 1.

PHT6N06T. 1. Product profile. 2. Pinning information. TrenchMOS standard level FET. 1.1 Description. 1.2 Features. 1.

TrenchMOS ultra low level FET

N-channel TrenchMOS logic level FET

PHP7NQ60E; PHX7NQ60E

PHP/PHD3055E. TrenchMOS standard level FET. Product availability: PHP3055E in SOT78 (TO-220AB) PHD3055E in SOT428 (D-PAK).

PSMN004-60P/60B. PSMN004-60P in SOT78 (TO-220AB) PSMN004-60B in SOT404 (D 2 -PAK).

PSMN002-25P; PSMN002-25B

PMWD16UN. 1. Product profile. 2. Pinning information. Dual N-channel µtrenchmos ultra low level FET. 1.1 General description. 1.

SI Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 Description. 1.2 Features. 1.

PMV65XP. 1. Product profile. 2. Pinning information. P-channel TrenchMOS extremely low level FET. 1.1 General description. 1.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

IRFR Description. 2. Features. 3. Applications. 4. Pinning information. N-channel enhancement mode field effect transistor

BUK A. 1. Product profile. 2. Pinning information. TrenchMOS standard level FET. 1.1 Description. 1.2 Features. 1.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

TrenchMOS technology Very fast switching Logic level compatible Subminiature surface mount package.

2N7002F. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

BUK71/ AIE. TrenchPLUS standard level FET. BUK AIE in SOT426 (D 2 -PAK) BUK AIE in SOT263B (TO-220AB).

BUK71/ AIE. TrenchPLUS standard level FET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

BUK71/ ATE. TrenchPLUS standard level FET. BUK ATE in SOT426 (D 2 -PAK) BUK ATE in SOT263B (TO-220AB).

BUK9Y53-100B. N-channel TrenchMOS logic level FET. Table 1. Pinning Pin Description Simplified outline Symbol 1, 2, 3 source (S) 4 gate (G)

N-channel TrenchMOS standard level FET. Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance

N-channel TrenchMOS logic level FET

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

PHD/PHP36N03LT. 1. Product profile. 2. Pinning information. N-channel TrenchMOS logic level FET. 1.1 General description. 1.

N-channel TrenchMOS standard level FET. Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance

PSMN013-80YS. N-channel LFPAK 80 V 12.9 mω standard level MOSFET

BUK B. N-channel TrenchMOS standard level FET

DATA SHEET. BSN304 N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 17

PHB108NQ03LT. N-channel TrenchMOS logic level FET

N-channel TrenchMOS ultra low level FET. Higher operating power due to low thermal resistance Interfaces directly with low voltage gate drivers

DATA SHEET. BSN254; BSN254A N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS

PSMN2R6-40YS. N-channel LFPAK 40 V 2.8 mω standard level MOSFET

PSMN8R3-40YS. N-channel LFPAK 40 V 8.6 mω standard level MOSFET

N-channel TrenchMOS logic level FET

PSMN005-75B. N-channel TrenchMOS SiliconMAX standard level FET. High frequency computer motherboard DC-to-DC convertors

PSMN004-60B. N-channel TrenchMOS SiliconMAX standard level FET. High frequency computer motherboard DC-to-DC convertors

PSMN B. N-channel TrenchMOS SiliconMAX standard level FET. High frequency computer motherboard DC-to-DC convertors

DATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20

P-channel enhancement mode MOS transistor

N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package using

N-channel TrenchMOS standard level FET

PHP110NQ08T. N-channel TrenchMOS standard level FET

PSMN4R5-40PS. N-channel 40 V 4.6 mω standard level MOSFET. High efficiency due to low switching and conduction losses

N-channel TrenchMOS logic level FET

PSMN4R3-30PL. N-channel 30 V 4.3 mω logic level MOSFET. High efficiency due to low switching and conduction losses

PSMN006-20K. N-channel TrenchMOS SiliconMAX ultra low level FET

BUK B. N-channel TrenchMOS logic level FET

BUK A. N-channel TrenchMOS standard level FET

FEATURES SYMBOL QUICK REFERENCE DATA

PSMN1R3-30YL. N-channel 30 V 1.3 mω logic level MOSFET in LFPAK

N-channel TrenchMOS transistor

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

N-channel TrenchMOS standard level FET. High noise immunity due to high gate threshold voltage

N-channel 30 V 1.3 mω logic level MOSFET in LFPAK

PHT4NQ10LT. 1. Description. 2. Features. 3. Applications. 4. Pinning information. N-channel enhancement mode field-effect transistor

FEATURES SYMBOL QUICK REFERENCE DATA

BSH Description. 2. Features. 3. Applications. 4. Pinning information. N-channel enhancement mode field-effect transistor

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

BF545A; BF545B; BF545C

60 V, 0.3 A N-channel Trench MOSFET

PINNING - TO220AB PIN CONFIGURATION SYMBOL. tab

PSMN K. 1. Description. 2. Features. 3. Applications. 4. Pinning information. N-channel enhancement mode field-effect transistor

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

DATA SHEET. PH2369 NPN switching transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr Oct 11.

DISCRETE SEMICONDUCTORS DATA SHEET M3D071. BAT74 Schottky barrier double diode. Product specification Supersedes data of 1996 Mar 19.

TO220AB & SOT404 PIN CONFIGURATION SYMBOL

DATA SHEET. BC369 PNP medium power transistor; 20 V, 1 A DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Nov 20.

DATA SHEET. BC368 NPN medium power transistor; 20 V, 1 A DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Dec 01.

DATA SHEET. BCP69 PNP medium power transistor; 20 V, 1 A DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2002 Nov 15.

FEATURES SYMBOL QUICK REFERENCE DATA. V DSS = 55 V Very low on-state resistance Fast switching

DATA SHEET. PBSS4250X 50 V, 2 A NPN low V CEsat (BISS) transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Jun 17

PINNING - SOT223 PIN CONFIGURATION SYMBOL

DISCRETE SEMICONDUCTORS DATA SHEET. book, halfpage M3D302. PBSS4240DPN 40 V low V CEsat NPN/PNP transistor. Product specification 2003 Feb 20

DISCRETE SEMICONDUCTORS DATA SHEET. PMBT3906 PNP switching transistor. Product specification Supersedes data of 1999 Apr 27.

PINNING - SOT404 PIN CONFIGURATION SYMBOL

DATA SHEET. BC856; BC857; BC858 PNP general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2003 Apr 09

DATA SHEET. BC846; BC847; BC848 NPN general purpose transistors DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2002 Feb 04

N-channel TrenchMOS standard level FET. Higher operating power due to low thermal resistance

PINNING - TO220AB PIN CONFIGURATION SYMBOL. tab

PINNING - SOT223 PIN CONFIGURATION SYMBOL

NPN/PNP low V CEsat Breakthrough in Small Signal (BISS) transistor pair in a SOT457 (SC-74) Surface Mounted Device (SMD) plastic package.

DATA SHEET. PBSS4540Z 40 V low V CEsat NPN transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2001 Jul Nov 14.

DATA SHEET. PBSS5350D 50 V low V CEsat PNP transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 2001 Jul Nov 13.

PowerMOS transistor PINNING - SOT428 PIN CONFIGURATION SYMBOL. tab

Transcription:

M3D879 Rev. 2 11 September 23 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. 1.2 Features SOT96 (SO8) footprint compatible Surface mounted package Low thermal resistance Low profile. 1.3 Applications DC-to-DC primary side Portable equipment applications. 1.4 Quick reference data V DS 15 V P tot 62.5 W I D 22.2 A R DSon 55 mω 2. Pinning information Table 1: Pinning - SOT685-1 (QLPAK), simplified outline and symbol Pin Description Simplified outline Symbol 1,2,3 source (s) [1] 4 gate (g) 5,6,7,8 drain (d) mb mounting base connected to drain Bottom view 1 4 mb 8 5 MBL585 SOT685-1(QLPAK) g MBB76 d s [1] Shaded area indicates pin 1 identifier.

3. Ordering information Table 2: Ordering information Type number Package Name Description Version QLPAK Plastic surface mounted package; no leads; 8 terminals SOT685 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 6134). Symbol Parameter Conditions Min Max Unit V DS drain-source voltage (DC) 25 C T j 15 C - 15 V V DGR drain-gate voltage (DC) 25 C T j 15 C; R GS =2kΩ - 15 V V GS gate-source voltage (DC) - ±2 V I D drain current (DC) T mb =25 C; V GS =1V;Figure 2 and 3-22.2 A T mb = 1 C; V GS =1V;Figure 2-14 A I DM peak drain current T mb =25 C; pulsed; t p 1 µs; Figure 3-6 A P tot total power dissipation T mb =25 C; Figure 1-62.5 W T stg storage temperature 55 +15 C T j junction temperature 55 +15 C Source-drain diode I S source (diode forward) current (DC) T mb =25 C - 22.2 A I SM peak source (diode forward) current T mb =25 C; pulsed; t p 1 µs - 6 A Avalanche ruggedness E DS(AL)S E DS(AL)R non-repetitive drain-source avalanche energy repetitive drain-source avalanche energy unclamped inductive load; I D =12A; t p =.21 ms; V DD 15 V; R GS =5Ω; V GS = 1 V; starting T j =25 C unclamped inductive load; I D = 1.2 A; t p =.21 ms; V DD 1 V; R GS =5Ω; V GS =1V - 25 mj [1] Duty cycle limited by maximum junction temperature. [2] Repetitive avalanche failure is not determined simply by thermal effects. Repetitive avalanche transients should only be applied for short bursts, not every switching cycle. [1] [2] - 2.5 mj Product data Rev. 2 11 September 23 2 of 13

12 3aa15 12 3aa23 P der (%) I der (%) 8 8 4 4 5 1 15 2 T mb ( C) 5 1 15 2 T mb ( C) P der P tot I D = ---------------------- 1% I P der = ------------------- 1% I tot ( 25 C ) D25C ( ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 1 2 3al6 ID (A) Limit RDSon = VDS / ID tp = 1 µs 1 µs 1 1 ms DC 1 1 ms 1-1 1 1 1 2 1 3 V DS (V) Fig 3. T mb =25 C; I DM is single pulse; V GS =1V Safe operating area; continuous and peak drain currents as a function of drain-source voltage. Product data Rev. 2 11 September 23 3 of 13

5. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-mb) thermal resistance from junction to mounting base Figure 4 - - 2 K/W 5.1 Transient thermal impedance 1 3al5 Z th(j-mb) (K/W) 1 1-1 δ =.5.2.1.5.2 1-2 single pulse P t p δ = T 1-3 1-5 1-4 1-3 1-2 1-1 1 tp (s) t p T t Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. Product data Rev. 2 11 September 23 4 of 13

6. Characteristics Table 5: Characteristics T j =25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V (BR)DSS drain-source breakdown voltage I D = 25 µa; V GS =V T j =25 C 15 - - V T j = 55 C 134 - - V V GS(th) gate-source threshold voltage I D = 1 ma; V DS =V GS ; Figure 9 T j =25 C 2 3 4 V T j = 15 C 1.2 - - V T j = 55 C - - 4.4 V I DSS drain-source leakage current V DS = 12 V; V GS =V T j =25 C - - 1 µa T j = 15 C - - 1 µa I GSS gate-source leakage current V GS = ±2 V; V DS = V - 1 1 na R DSon drain-source on-state resistance V GS = 1 V; I D =15A;Figure 7 and 8 T j =25 C - 4 55 mω T j = 15 C - 92 127 mω V GS =5V; I D =3A;Figure 7 and 8-42 - mω Dynamic characteristics Q g(tot) total gate charge I D = 2 A; V DD =75V; V GS =1V;Figure 13-36.2 - nc Q gs gate-source charge - 8 - nc Q gd gate-drain (Miller) charge - 11.6 - nc C iss input capacitance V GS =V; V DS = 25 V; f = 1 MHz; Figure 11-28 - pf C oss output capacitance - 285 - pf C rss reverse transfer capacitance - 9 - pf t d(on) turn-on delay time V DD =75V;R L =75Ω; V GS =1V;R G = 5.6 Ω - 16 - ns t r rise time - 12 - ns t d(off) turn-off delay time - 5 - ns t f fall time - 38 - ns Source-drain diode V SD source-drain (diode forward) voltage I S = 1 A; V GS =V;Figure 12 -.83 1.2 V t rr reverse recovery time I S = 1 A; di S /dt = 1 A/µs; V GS = V - 15 - ns Q r recovered charge - 215 - nc Product data Rev. 2 11 September 23 5 of 13

6 I D (A) 4 T j = 25 C 1 V 6 V 3al7 5 V 4.9 V 6 I D (A) 4 V DS > I D x R DSon 3al9 4.7 V 4.5 V 2 4.3 V 2 4.1 V 3.9 V V GS = 3.7 V 1 2 3 4 5 V DS (V) 15 C T j = 25 C 2 4 6 V GS (V) Fig 5. T j =25 C Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. T j =25 C and 15 C; V DS > I D R DSon Transfer characteristics: drain current as a function of gate-source voltage; typical values. 8 3al8 2.5 3al51 RDSon (mω) 6 Tj = 25 C VGS = 4.7 V 4.9 V 5 V 6 V a 2 1 V 1.5 4 1 2.5 2 4 6 ID (A) -6 6 12 18 Tj ( C) T j =25 C R a = DSon ---------------------------- R DSon ( 25 C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. Product data Rev. 2 11 September 23 6 of 13

5 V GS(th) (V) 4 max 3aa32 1-1 I D (A) 1-2 3aa35 3 typ 1-3 min typ max 2 min 1-4 1 1-5 -6 6 12 18 T j ( C) 1-6 2 4 6 V GS (V) Fig 9. I D = 1 ma; V DS =V GS Gate-source threshold voltage as a function of junction temperature. T j =25 C Fig 1. Sub-threshold drain current as a function of gate-source voltage. 1 4 3al11 C (pf) Ciss 1 3 Coss 1 2 Crss 1 1-1 1 1 1 VDS (V) 2 V GS = V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. Product data Rev. 2 11 September 23 7 of 13

6 3al1 1 3al12 I S (A) V GS = V V GS (V) 8 I D = 2 A T j = 25 C V DD = 3 V 75 V 4 6 12 V 4 2 15 C T j = 25 C 2.5 1 1.5 V SD (V) 1 2 3 4 Q G (nc) T j =25 C and 15 C; V GS =V Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. I D = 2 A; V DD = 3 V, 75 V, 12 V Fig 13. Gate-source voltage as a function of gate charge; typical values. Product data Rev. 2 11 September 23 8 of 13

7. Package outline HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 6 x 5 x.85 mm SOT685-1 2.5 5 mm X scale D B A A A 1 c E detail X terminal 1 index area terminal 1 index area L e 1 e b 1 4 v M w M C C A B y 1 C C y E h eh exposed tie bar (4 ) 8 5 D h DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max. 1 A1.5. b.5.3 c.2 D (1) 5.15 4.85 D h 3.95 3.65 E (1) 6.15 5.85 Eh 3.65 3.35 e 1.27 e1 3.81 eh.35 L.75.5 v.1 w.5 y y 1.5.1 Note 1. Plastic or metal protrusions of.75 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA SOT685-1 - - - EUROPEAN PROJECTION ISSUE DATE 2-8-12 2-11-27 Fig 14. SOT685-1 (QLPAK). Product data Rev. 2 11 September 23 9 of 13

8. Soldering handbook, full pagewidth Cu covered with solder resist solder lands 6. 5.9 4.6 3.85.5 (8 ).75 (8 ).75.15.5 solder resist clearance solder paste placement area occupied area 2.25 2.175 2.35 3.45 7.25 7. 1.525 2.3 2.5 1.95 1.4 6.4.4.15 MGX371.5 SP around (4 ).4 2.6 5.4 6.25 1.27.6 (4 ).85 (4 ) Dimensions in mm. Fig 15. Reflow soldering footprint for SOT685-1 (QLPAK). Product data Rev. 2 11 September 23 1 of 13

9. Revision history Table 6: Revision history Rev Date CPCN Description 2 23911 - Product data (9397 75 11844) Modifications: Section 3 Ordering information Addition of ordering information. Section 4 Limiting values Addition of E DS(AL)S. Section 4 Limiting values Addition of E DS(AL)R. Section 8 Soldering Addition of soldering footprint. 1 2313 - Preliminary data (9397 75 1882); initial version. Product data Rev. 2 11 September 23 11 of 13

1. Data sheet status Level Data sheet status [1] Product status [2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 11. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 6134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 12. Disclaimers customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 13. Trademarks TrenchMOS is a trademark of Koninklijke Philips Electronics N.V. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Fax: +31 4 27 24825 9397 75 11844 Koninklijke Philips Electronics N.V. 23. All rights reserved. Product data Rev. 2 11 September 23 12 of 13

Contents 1 Product profile.......................... 1 1.1 Description............................ 1 1.2 Features.............................. 1 1.3 Applications........................... 1 1.4 Quick reference data..................... 1 2 Pinning information...................... 1 3 Ordering information..................... 2 4 Limiting values.......................... 2 5 Thermal characteristics................... 4 5.1 Transient thermal impedance.............. 4 6 Characteristics.......................... 5 7 Package outline......................... 9 8 Soldering............................. 1 9 Revision history........................ 11 1 Data sheet status....................... 12 11 Definitions............................ 12 12 Disclaimers............................ 12 13 Trademarks............................ 12 Koninklijke Philips Electronics N.V. 23. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 11 September 23 Document order number: 9397 75 11844