STANFORD UNIVERSITY Department of Electrical Engineering SAMPLE FINAL EXAMINATION Fall Quarter, 2002 EE214 8 December 2002 CLOSED BOOK; Two std. 8.5 x 11 sheets of notes permitted CAUTION: Useful information may be included at the end of a problem statement, so be sure to read each problem COMPLETELY before beginning to work on it. We will be incredibly unforgiving about failures to read the problems thoroughly. Count the number of pages you have, and make sure it equals the page count shown at the bottom, just in case the copy machine decided to omit a page here or there to trip you up. NOTES: Be sure to summarize your answers in the spaces provided to help us determine correct answers quickly during grading. However, turn in and show all work, as partial credit will be given. BE SURE to put your name on all answer sheets and booklets. Make reasonable approximations, but be sure to state all assumptions. Put your name on each booklet and loose page you intend to turn in (now might be a good time). You may read the following after the exam to save time: Regrade policy: We photocopy a percentage of final exams on a random sampling basis to give the teaching staff a chance to spot systematic grading errors even after we ve handed back exam booklets. Despite our best efforts, though, some mistakes in grading occasionally evade detection by our extensive quality control procedures. If you feel that you have been the victim of a (hopefully rare) grading error, submit a written regrade request, along with your exam, before January 7, 2003. The entire exam will be studied for regrading. We hope to have final exams and final course grades available by noon on Friday, December 12, at the office of EE214 administrative associate Ann Guerra (CIS-207). DO NOT CALL or email. We cannot release exam and final course grades over the phone. To get your exam, please show up in person and present your student ID, or wait for Axess data to become available. SITN students will receive their exams and final grade through regular SITN channels. Happy holidays! Page 1 of 9
PROBLEM 1: Negative feedback has been the dominant paradigm for so long that a prejudice (subtle or not) against positive feedback prevails among many engineers. This problem investigates one possible application of positive feedback in linear circuits, beyond the standard fare of oscillators and flipflops. Since signs are critically important here, little or no partial credit will be awarded for answers that contain sign errors. Suppose that an engineer at that perennially struggling startup, SubOptimal Products, had intended to make a standard non-inverting amplifier, but inadvertently mixed up the two input terminals as follows: FIGURE 1. Tragic mistake or company savior? v IN - + G(s) R 2 v OUT R 1 a) What is the loop transmission of this system? Remember: Watch those signs! Ans: L(s) = b) Provide a block diagram for the circuit: FIGURE 2. Block diagram for Figure 1 (note the minus sign at the summing junction) v IN Σ - v OUT Page 2 of 9
c) What is the closed-loop transfer function, A(s) = v OUT /v IN, for this system? Ans: A(s) = d) Assume that the op-amp used by SubOptimal has the following transfer function: Gs ( ) = G 0 ---------------- ( s + 1), (EQ 1) where G(s) is defined as the output voltage, divided by the differential input voltage. Derive expressions for the crossover frequency and the closed-loop DC gain for the circuit. Again, watch signs! Ans: ω c = Ans: A 0 = e) Implicit in your answer to part d) is the seed of hope. Treat the closed-loop connection (i.e., op-amp plus two resistors) as a single op-amp that will be used to make a standard inverting integrator using an input resistor of 1kilohm, and an integrating capacitor of 1µF. The SubOptimal op-amp has a DC gain, G 0, of only 2001, draws no current through its input terminals, and has zero output resistance. Ignore the op-amp pole, and sketch the unit step response of the integrator if the ratio of resistors, R 2 /R 1, is 2000. If you do not trust your answer to d), you may, with reduced credit, assume that the overall system s closed-loop DC gain magnitude is 10 (but still inverting). FIGURE 3. Unit step response of integrator (notice sign on y-axis label) v OUT t Page 3 of 9
PROBLEM 2: As you can appreciate from having labored on the midterm design, a lowheadroom cascode is an extremely useful circuit to have around. This problem examines a design issues associated with one particular circuit: FIGURE 4. Simple low-voltage cascoded mirror VDD I OUT V BIAS I REF M4 M5 M1 M2 M3 Neglect body effect, assume long-channel (i.e., square-law) behavior, and further assume that, in saturation, the output resistance is infinite (ah, if only it were so...). Additionally, assume that all devices are of equal length. The PMOS mirror is similarly perfect, and has a precise 1:1 current ratio. a) Let W 2 = W 3 = n 2 W 4 = n 2 W 5 = W, with n > 1. Derive a condition for W 1 in terms of W and n such that M2 and M3 are on the edge of saturation. Ans: W 1 = b) An alternative low-voltage cascode circuit is shown in the following figure: Page 4 of 9
FIGURE 5. Alternative low-voltage cascoded mirror I REF I OUT R REF M2 M4 M1 M3 Using the same assumptions as in part a), and additionally assuming that all transistors are the same, derive an expression for R REF such that M1 and M2 are both in saturation. Ans: R REF = Page 5 of 9
PROBLEM 3: The method of open-circuit time constants is, as we all know, an approximate method whose primary value is its ability to identify bandwidth-limiting elements. As long as certain criteria are met, open-circuit time constant estimates are quantitatively reasonable. Consider the following circuit: FIGURE 6. Common-source amplifier with source bypass capacitor VDD R L v OUT v IN C L R E C E a) Neglecting body effect and channel-length modulation, derive an expression for R 1o, the open-circuit resistance facing the load capacitance C L, and R 2o, the corresponding resistance facing the source bypass capacitance C E. Assume that the gate is driven from a zero-impedance source, exactly as shown. Assume that the two capacitances shown are the only ones in the entire circuit. Also assume that the transistor is magically biased into the saturation region. Ans: R 1o = R 2o = b) What is the low-frequency voltage gain of this circuit if R E is much larger than 1/g m of the transistor? Ans: DC gain = c) Open-circuit time constants would suggest that increasing the size of C E would inevitably degrade bandwidth. To evaluate the quality of this prediction, derive a complete Page 6 of 9
expression for the transfer function of this amplifier (include the 1/g m term neglected in part b). It may be helpful to notice that the assumptions given allow you to consider what s happening in the input circuit independently of what s happening in the output circuit. Ans: H(s) = d) Provide an expression for C E that maximizes bandwidth (write zero if that s the right answer). If there appear to be several choices, select the one that maximizes the bandwidth subject to the constraint of a monotonic frequency response: Ans: Optimum C E = Complete the following sentence: The method of open-circuit time constants is/is not (circle one) accurate in this case because Page 7 of 9
PROBLEM 4: No Stanford EE should be permitted to graduate without having studied the oscillator circuit that started HP on its road to success. The following circuit is a simplified version of the Wien (pronounced veen ) bridge that Mr. Hewlett designed for his master s thesis: FIGURE 7. Simplified Wien (not Wein!) bridge oscillator C R G v OUT C R a) Derive an expression for the loop transmission of this system. In this and subsequent parts, you may assume that the quantity G is scalar. Ans: LT(s) = b) For both polarities of G, sketch the collection of all possible closed-loop pole locations below. That is, sketch the locus of poles as the magnitude of G varies: G < 0: G > 0: c) Devise a simple implementation of the gain block in Figure 7, using one ideal op-amp and at most two resistors. Denote as R 2 the resistor that ties to the op-amp output, and Page 8 of 9
name the other one R 1. Note: Strictly speaking, root locus diagrams are not needed to answer this part, but they may be helpful in providing insight. Watch your signs; they count! FIGURE 8. My gain block for the Wien bridge oscillator is shown below: What magnitude should R 2 /R 1 have to make an oscillator? Ans: R 2 /R 1 = d) For the conditions in part c), what is the oscillation frequency if R = 10kΩ and C = 1nF? Be sure to specify units. Ans: Oscillation frequency = e) From your locus, you should discern a practical difficulty with this oscillator (actually, all oscillators), and that is that changes in the gain G can cause the oscillation to grow or decay exponentially. The ingenious solution that Mr. Hewlett employed was to make one of the resistors (we re talking about R 1 and R 2 ) vary with the output amplitude. Specifically, he used a light bulb filament, whose resistance varies with temperature. A change in amplitude changes the temperature, so the light bulb s resistance is a function of amplitude. Arguing from your root locus, should the light bulb form part of R 1 or R 2 if the filament resistance has a positive temperature coefficient? Explain your reasoning. Ans: The light bulb should be part of because, as seen from my locus for G > 0/ G < 0 (circle only one), (insert brilliant insight here) Page 9 of 9