DRAM & SRAM Design Random Access Memory Volatile memory Random access is possible if you know the address DRAM DRAM Dynamic Random Access Memory SRAM Static Random Access Memory SRAM Cell Structure Power for data Refresh Density Access speed (Read/Write) Power(standby) Price 1 Tr. & 1 cap. Required Required High 50ns/50ns ~200μA Low 6 Tr. Required None Low 5ns/5ns 10 μa High Application Main memory Cache
DRAM (Dynamic Random Access Memory) Word line 1cm Transfer gate [access] 1 or 0 Bit line + + + + ---- Storage node capacitor Periphery circuits Cell array (core) 3cm I/O gate, CMOS TR Data sense/amplifier Data read Data refresh Dynamic random access memory Random access : row decoder Select word line column decoder Select bit line Need to refresh the charge loss in the capacitor (refresh circuits)
2 m+n = 2 16 ROW Decoder (n) WL0 WL1 WL2 WL3 WL4 WL5 WL6 WL7 16 BIT DRAM BL /BL BL /BL BL /BL.................. S/A Driver DB Line /DB Line RTO /S.... CD0 CD1 CD7 Column Decoder (m)
1, 6 V BLP N pre /N pre V cc/2 WL DRAM Sensing Operation 2, 5 3 4 Bit line BL C s RTO SA P SA /P SA N SA /N /S DB Gate DB Line /DB Line CDi Column select Bit line /BL DB Gate BL V cc BL Pair V cc /2 /BL 1 2 3 4 5 6 0V
DRAM Sensing Operation BL V cc BL Pair V cc /2 /BL 1 2 3 4 5 6 0V 1) Read operation 1 Turn on N pre & /N pre and pre-charge with V cc /2 level on both BL & /BL. 2 Select (or turn on) WL and BL becomes sensing signal voltage (V S ) (Assumption: data = 1) 3 Amplification. During this process, WL is still on. 4 Select column decoder and send out data 5 After read operation, WL is off and cell data is saved to Vcc again 6 Turn on N pre & /N pre and pre-charge with Vcc/2 level again for next operation.
V 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Stable Two stable point:0,1 Stable point: E=1 V R input V L output V L input V R output B Stable point: 0 0.5 1 1.5 2 2.5 D=0 3 VL Unstable point:a C
Before switch on After switch on Data 1 Charged V BL V H V S C BL C S Data 0 Discharged V BL V L V S
Method for increasing sensing signal voltage V S 1 Reduce parasitic bit line capacitance, C BL PN C S SN Total Parasitic bit line capacitance C N BL C BL, i C BL,BL C BL,SN STI C BL,WL C BL,PN WL C BL,Sub BL where N is the number of cells/bl if there are 256 cell in one bit-line, N=256 Components of parasitic BL capacitance Junction capacitance between BL and Sub = C BL,SUB Interlayer capacitance between BL and WL = C BL,WL Interlayer capacitance between BL and SN = C BL,SN Interlayer capacitance between BL and PN = C BL,PN Interlayer capacitance between BL and BL = C BL,BL
2 Increase memory cell capacitor C s Material є r Material є r C s A d To obtain high C S Increase surface area of capacitor. Reduce thickness of dielectric material Use high-k materials Ta 2 O 5 2.5 TiO 2 80 Al 2 O 3 9.5 SrTiO 3 200 ZrO 2 20 40 (Ba,Sr)TiO 3 800 HfO 2 20 30 PZT 1000
3D View of a DRAM cell
DRAM Cell Configuration Open Folded
DRAM Fabrication Passivation Nitride Passivation HDP oxide Metal-2 Passivation Nitride Passivation HDP oxide Metal-2 TiN Capping Via CVD oxide Barrier metal Metal-1 CVD oxide Metal-1 ILD3 ILD3 ONO W-plug SN Stopper Nitride Plate poly SN DRAM Structure ILD2-B ILD2-A BL HM Nit. ILD1-B ILD1-A STI FOX SPP1 LPP SPP2 BLC1 GATE Cell Pad BL STI FOX BLC2 Cell Peri
Folded Structure Active A A A A BPSG:Borophosphosilicate glass ILD: interlayer dielectric BC: Bit line contact
(using CMP) CMP: chemical mechanical polishing LPP can be seen only in BC1 etch area. The area of cross-section view
HM: hard mask
SN: storage node SPP: Storage node plug poly
SN oxide removal using HF HSG poly Si formation Dielectric formation (ONO) Plate poly formation ONO: oxide nitride oxide HSG: Hemispherical grained
DRAM Cross-section Images (BL direction) (WL direction) M3 (Al) M2(Al) SN SN pad BL cell pad WL STI STI BL(W)
SGT DRAM Fabrication 113 A Capacitor cell A 108 (WL) A Open Structure (4F 2 ) 102 115 116 Capacitor cell Select Transistor A A 101: BOX 102: N+ doped area 120: Nitride 108: Gate 107: Gate oxide 109: Landing plug poly 110: SN poly Si 111: ONO dielectric 112: plate poly 113: Bit line contact 115: Bit line plug poly
SGT DRAM Fabrication 101: BOX 102: N+ doped area 120: Nitride 108: Gate 107: Gate oxide
SGT DRAM Fabrication Tilted implantation 109: Landing plug poly
SGT DRAM Fabrication 110: SN poly Si 111: ONO dielectric 112: plate poly 113: Bit line metal 115: Bit line plug poly
SGT DRAM Fabrication 113 A A Capacitor cell Capacitor cell 108 (WL) A Select Transistor 102 115 116 113 115 Capacitor cell Select Transistor A A 101: BOX 102: N+ doped area 120: Nitride 108: Gate 107: Gate oxide 109: Landing plug poly 110: SN poly Si 111: ONO dielectric 112: plate poly 113: Bit line metal 115: Bit line plug poly
SRAM SRAM : Non-Memory (or Logic) occupies 65% of total semiconductor market Cache memory for non-memory (CPU & GPU) Automobile or display MPU Portable device memory (cell phone), CIS Processor Cache Memory SRAM Main memory DRAM Archive I Magnetic disk / Magnetic tape Archive II Optical disk 24
SRAM The key issue of 6T SRAM is how to distinguish btw read and write. We have one wordline, so it should be high for read and write. Therefore we need to use two bitlines to operate SRAM. N2, N4: Access TR, P1, P2: Pull up PMOS, load N1, N3: Pull down NMOS, driver
SRAM Operation Butterfly curve
SRAM Read Read A _ A BL = 1 BL A BL Hold BL Turn off word Line Time (ps)
SRAM Write
SRAM Design (SNM)
SGT SRAM (reference) 81: BOX 82 & 114: Si 113: nitride mask 128: Si pillar 118: n+ doping 119: nitride spacer 120: salicide (self aligned silicide) 128: Si pillar 130& 134 & 136 : dielectric 131: gate dielectric 132: gate
SGT SRAM (reference)
Announcement 1. Quiz will be held on 11 Oct from 1:00 to 2:00 2. HW #4 (due date: 6 Nov) Run at least two simulation sets (one SGT and one Trigate) that are designed during practice class. Draw transfer curves (Vd=0.1 & 1V) of the above simulations using log files. Obtain Vth, DIBL & SS from transfer curves. 3. HW #5 (due date: 13 Nov) Read Perspective of Giga DRAM and summarize in one A-4 page each. 32