Logarithmic Circuits

Logarithmic Circuits Binary Up Counter Logarithmic Circuits WHAt T Q T C Toggle Flip Flop @(posedge clk) If T=, toggle output Q If T=, hold old Q -bit binary counter TC=T Q T Q T Q T Q T T T T T C C C C CLK Simplest Counter Circuit Uses T Flip-Flops The circles show how the toggle signals are defined by ANDs: T = Q T = Q Q T = Q Q Q TC = Q Q Q Q TC = Teminal Count CLK Q Q Q Q Propagation Delay Notice the ripple carry. This limits the speed of the counter. Dig Cir p. 89 Revised; November 8, Slide 5 Logarithmic Circuits Binary Counters Binary Counters The simplest counters use toggle flip-flops. These are made from D flip-flops as shown. This is why many circuits of counters show an XOR gate and an AND gate for each flip-flop. The AND gates, drawn on top of the waveforms, show how the flip-flops toggle whenever all the preceding flip-flops are one. T D T= Þ D=Q old T= Þ D=~Q old D C Q Counter Speed Note that for long counters the chain of AND gates will get very long and will limit the speed of the counter. For a bit counter, the clock speed must allow propagation through AND gates plus the clock-to-output and setup times of a flip-flop. Digital Circuits p. 9 Revised; November 8, Comment on Slide 5

Logarithmic Circuits Logarithmic Carry in a Binary Counter Ripple Carry Circuit Using T Flip-Flops T8 7 Q7 8-bit binary counter using a ripple carry 6 5 T Q6 T Q5 T Q T Q T Q T Q T Q T T7 T6 T5 T T T T T C C C C C C C C CLK Delay is N- (7), AND gate delays Logarithmic Carry Circuit Using T Flip-Flops 8-bit binary counter using logarithmic carry Delayislog (N) =, AND gate delays but watch the fanout Level number T8 Q7 T T7 Q6 T T6 Q5 T Q T5 C C C T T C Q T Q T Q T T T T T Q T C C C C CLK Dig Cir p. 9 Revised; November 8, Slide 5 Logarithmic Circuits Logarithmic Ripple-Carry Counter Logarithmic Ripple-Carry Counter By placing a buffer as shown, the end-to-end carry need only pass through log (N) gates. Counter Speed In the ripple-carry circuit. The time between a clock edge and a stable outbut from TC is: T CHQV for Q +(T pd for 7 AND gates). Ignoring the flip-flop delay, this is a delay proportional to N-, for N flip-flops. The fanout also effects the delay. Here all fanouts are. In the logarithmic carry circuit. The slowest carry, TC, must go from: a. The clock input to Q b. Q through a st level AND (green with a in side). c. through a nd level AND gate (red with a inside). d. through a rd level AND gate (blue with a inside). For N flip-flops this delay is proportional to log (N). However the fanouts increase the delay. The largest fanout is N/ +, (five for N=8). Digital Circuits p. 9 Revised; November 8, Comment on Slide 5

Logarithmic Circuits Logarithmic Carry for TC for a 6-Bit Counter C C C C C C C C T T T T T T T T C C =T C C C C C C 5 C 5 C 6 6 C 7 C 7 C C C 5 C 6 7 C =T C 7 DEPTH= C C 7 =T 8 C 7 C C C C C C C C T T T T T T T T C 8 8 C 9 C 9 C C C C C C 5 C C C 5 C 9 8 C C C 5 C 8 C 5 C 7 C 8 C 5 =T 6 TC Terminal Count Ripple Counter Showing Depth of Final Carry Depth = log (Number of bits) DEPTH= Dig Cir p. 9 Revised; November 8, Slide 5 Logarithmic Circuits Logarithmic Ripple-Carry Counter More Organized Picture of The Logarithmic Carry This shows how the earlier ANDs are done in parallel so any signal used in calculating TC only has to pass through AND gates. The symbol C m n is used to show what signals are ANDed together to make up a component of the carry. Thus the symbol C 7 means Q 7 Q 6 Q 5 Q. This only shows the gates needed to calculate TC. The next page shows the gates needed to calculate the intermediate carries. The next page also gives a rough approximation of the delay. It only hints at delay optimization from transistor sizing and adding buffers. Both of these will reduce delay at the expense of power and area. Digital Circuits p. 9 Revised; November 8, Comment on Slide 5

Logarithmic Circuits Showing extra hardware for intermediate carrys The depth is still or less. The amount of hardware has doubled (6 gates). 5 6 7 8 9 5 5 7 6 9 8 5 C 5 7 6 98 Gates From Prev. Picture Approximate summary: delay under half, area more than double. 7 8 C 7 7 5 5 8 5 8 5 New Gates For Intermediate Carrys DEPTH= DEPTH= 5 5 5 6 6 6 6 9 8 7 8 DEPTH= 9 8 8 8 9 8 8 8 8 8 8 T T T T 5 T 6 T 7 T 8 T 9 T T T T T T 5 5 T 6 Dig Cir p. 95 Revised; November 8, Slide 5 Logarithmic Circuits Logarithmic Ripple-Carry Counter If the delay of a two-input AND equals its fanout, then the delays are shown in ovals. Gates From New Gates Prev. Picture For Intrm. Carrys 5 6 7 8 9 5 5 7 6 9 8 5 5 7 6 98 7 8 7 7 5 8 58 5 5 5 5 DEPTH= DEPTH= 5 5 5 6 6 6 6 7 8 Without the buffers shown, the total delay, Q to T 6, is ++5+9+ = 9. In general N- + log (N). The buffer requires a more complex calculation but it will decrease the 9 substantially. Compare with the serial carry which is + 5 =. In general N - 9 9 8 DEPTH= 9 8 8 8 9 8 8 8 8 8 8 T T T T 5 T 6 T 7 T 8 T 9 T T T T T T 5 5 T 6 Digital Circuits p. 96 Revised; November 8, Comment on Slide 5

The -Bit Full Adder CARRY Generate C from inputs A,B C = if A=,B= (AB) Propagateprevious C C if A= or B= (A + B)C C = AB + G (A + B)C P Addition Addition A B C C SUM A B C Alternate Definition Σ= if all inputs are, (ABC ) Or if only one of A, B or C is ie any inputs =, but not two ie any inputs =, but no carry out (A+B+C )C A = G + PC Logical C usinggandp G P B C C A B A B Compact Circuit But No Separate P and G Signals +V +V C B A C B B A A (A+B)C+A B = C C C (A+B+C )C + ABC = Σ C C C B A B A C A B Dig Cir p. 97 Revised; November 8, Slide 5 Addition The -Bit Full Adder The -Bit Full Adder It adds bits, A + B +C The Karnaugh maps for the full adder. Maps showing = C (A B) AB C Maps showing carry out, C =A B + C (B + A) C AB AB C C C =A B + B C + C A BC AC =A B + C (B + A) Map for C. Circle map. The CMOS carry circuit Diagonal s on map indicate xor B A C x The map for Σ x=a B Map of C x AB The PMOS part of the circuit does not implement C =(A+B) (B+C ) (A+C ) as good CMOS is supposed(?) to do.. PROBLEM a. Find the expression it does implement. b. Show that it really is C. x C AB A B A B Map of C x with x expanded so one can see A, B AB C A B A B Same map with columns arranged in K-map order, showing C x=c (A B) =(A B) C =(A B)C I +(A B)C Digital Circuits p. 98 Revised; November 8, Comment on Slide 5

Addition The -Bit Adder Ripple-Carry Adder A B A B A B A B C C C C C C C C Σ Σ Σ Σ Ripple Carry Using Propagate and Generate A B B B B C A C A C A C C G G G Σ P Σ P Σ G P P Σ C G and P are independent of C Þ Longest Path Basic Adder Blocks =(A B) C A B C C C = G+PC G P C Generate carry; G Propagate carry; P A B Dig Cir p. 99 Revised; November 8, Slide 55 Addition The -Bit Full Adder. PROBLEM Show that the PMOS part of the full adder on Slide 5, implements the complement of the NMOS part. Hint: plot the PMOS function on a Karnaugh map. Then invert each square on the map to get the complement of The PMOS function, and check that it matches the NMOS map.. PROBLEM Some books define P=A B. Show what this does to the C and functions. What advantage does it have, i.e. smaller, faster, less power. Solution: The alternate P is generated for free because it is needed in the sum, thus saving an OR gate in each block. However the XOR takes more time to calculate, so the Ps will be delayed. Some circuits,. like the carry-bypass adder, demand that P=XOR. Digital Circuits p. Revised; November 8, Comment on Slide 55

Addition Derivation of Carry Look-Ahead Blocks Serial Carry Using P and G (repeated) A B A B A B A B C C C C G G G P Σ G P Σ Σ P P Σ C C =G +P (G +P (G +P (G +P C ))) Convert Serial Carry to Parallel Circuits +V C G P P G P G C P G P G P G P G P G C C =G +P (G +P (G +P C )) C = G +P (G +P C ) +V +V C = G +P C C G P C P P +V G P P G C G P P G P G P G C G G C C P C G P P G G C C Dig Cir p. Revised; November 8, Slide 56 Addition Carry Look-Ahead Adder Carry Look-Ahead Adder Eliminating The Long Path-Delay For The Carry Deep Gates Instead of Long Paths? The long carry chain makes the add slow. One can factor the carry propagation equation to make each C i one complex gate. However for C, this complex gate will have 5 series transistors (one would not go to C5). To compensate for the five channel resistances, the transistors in the C gate would be made.5 times wider than those in the C NAND-OR gate. This greatly increases the adder area and power consumption. The large capacitance seen by C, especially at the wide gates of the left most circuits, causes some delay. However, the propagation time from C to C is still about half that of the serial carry using P and G. PMOS and NMOS are Almost Symmetric The PMOS logic here is not that found by applying DeMorgan directly to the NMOS logic. Neither is it derived directly from the corresponding NMOS equation. For example: C =G +P (G +P (G +P C )) using the methods in Using the Sum of Products (Σ of Π) for the PMOS function on page 8 Remember that G i+ =A i B i,andp i+ =A i +B i, hence one will never get the case G i+,p i+ =,. The outputs for these inputs become don tcares on the map, for the C equation and the equation for the PMOS circuit can be derived.. PROBLEM Derive the equation for the PMOS circuits for C. C will have a similar but longer derivation. G P P G P P G P G P d d d P d d d G d d d d G d d d d C G C G P Digital Circuits p. Revised; November 8, Comment on Slide 56

Addition The -Bit Carry Look-Ahead Adder Carry Lookahead Using P and G G C G C G P Σ P C C G P Σ Σ P Σ C C = G +P C C G G P C Note no carry signal propagates through the Σ blocks. C i is not connected to P i+ or G i+ Look-Ahead Carry Blocks C 7 C 5 C 8 C 5 C C C C C Blocks Connected By Ripple Carry Dig Cir p. Revised; November 8, Slide 57 Addition Carry Look-Ahead Adder Look-Ahead Carry look-ahead depends on single gates, albeit with large fan-in, being faster than a chain of gates. This is true up to or full-adders ( or 5 series transistors in the final carry block). The area used increases significantly with carry look-ahead because the gates are larger, and to maintain speed, the transistors in the series chains of large gates must be larger. Grouping Blocks Since only four adders can be put in a block, larger adders must have chains of blocks. The longest delay is the delay for C to reach C 8 above, or C n for n blocks. If all gates had the same delay τ, the adder delay would be τn for the ripple-carry and τn for the carry lookahead. Unfortunately the large gates provide a large capacitive load to their source gates and slow down the look-ahead carry signal, C n, to roughly τn. This calculation is fairly complex and involves placing buffer inverters after C,C 8... 5. PROBLEM Take the NMOS part of the carry circuit for C on Slide 56. If the G transistor has a width of unit in order to pull down at a certain speed, then the P and C transistors must have a width of units to pull that path down at the same speed. This assumes channel resistance is proportional; to width which is close to true. Show that in the NMOS circuit for C, the G transistor need only have a width of to maintain speed but some other transistors need a width of 5 units. 6. PROBLEM There are five outputs in the compromise adder on Slide 58, Σ, Σ. Σ, Σ and C. Rate each output as being slower, the same, or faster than the -bit carry look-ahead adder. S is about the same, although the load on C will slow its rise time. S,S are slower because their signal goes through the same number of gates, but the P and G inputs are more highly loaded. S is faster because of fast path to the complex gate. Digital Circuits p. Revised; November 8, Comment on Slide 57

Addition Compromise Carry Look-Ahead Adder. G C G C G Σ C G C P P Σ P Σ P C Σ C G G G P C Properties Delay C ->C Area Ripple P&G Full parallel..5 Compromise.5 Description By not using parallel look-ahead on C,C,andC C will have 5% more delay than C, but C is not passed on to later stages. C ->C is slightly faster because of reduced loading on C. Dig Cir p. 5 Revised; November 8, Slide 58 Addition Compromise Carry Look-Ahead Adder Compromise Carry Look-Ahead Adder Formorethan-bits,thisisthefastestaddershownsofar. In a multi-block adder, one might want to make the final block or the last two blocks fully carry look-ahead so that the sum bits would not be delayed more than the final carry. Later we will show how gradually increasing the length of the blocks will reduce the number of blocks. For long adders, the delay will increase with sqrt(n) rather than linearly with n (τn) as it does here. The next carry look-ahead adder will have a delay which increases with log (n). Digital Circuits p. 6 Revised; November 8, Comment on Slide 58n

Addition The Brent-Kung Carry-Lookahead Adder Generalized propagate and generate C Generalized Propagate P m k A propagate through a block of adders If P 7 = then: C can propagate thru adders Σ to Σ 6 and come out as C 7 a b a 6 b 6 5 6 G P G 7 P 7 G 7 P 7 C 7 Propagated Carry Generalized Generate G m k A generate within a block of adders that can also propagate thru the block internaly If G 7 = then: A carry was generated on G,G 5, G 6, and/or G 7 itwasabletopropagatetotheoutput G 7. And come out on C 7 a b a 6 b 6 5 6 C G P G 7 P 7 G 7 P 7 Generated Carry C 7 Dig Cir p. 7 Revised; November 8, Slide 59 Addition Generalized generate and propagate. Compromise Carry Look-Ahead Adder C k- P m k is a propagate between adder m and adder k If P m k = then: C k- can propagate thru the adders that produce G k,g k+... G m and P k,p k+... P m (adders Σ k-,..., Σ m- ) It comes out on C m a k- b k- a m- b m- 5 6 G k P k G m P m G m k P m k C m Propagated Carry G m k is a generate for adders m thru k that reaches m. If G m k = then: a carry was generated inside the block of adders that produce G k,g k+... G m and P k,p k+... P m and propagated inside the block to the output. a k- b k- a m- b m- 5 6 C k- G k P k G m P m G m k P m k Generated Carry C m Digital Circuits p. 8 Revised; November 8, Comment on Slide 59

Addition Generalized generate and propagate P m k composite propagate. For the adder s inputs a m- and b m- P m m =P m =a m- +b m-, P = From other G and P signals P m k =P m P m- k =P m j P j- k Examples: P 5 =P 5 P P P P m =P m P m- P m-...p P 5 =P 5 5 P P 5 =P 5 P G 5 5 P 5 5 a m- b m- G P k k P G m- m- G m P m G 5 P 5 G k m composite generate A carry is generated between m and k, and reaches m. For the adder inputs a m- and b m- G m m =G m =a m- b m-, G =C which is often From other G and P signals G k m =G m +P m G k m- =G j m +P j k m G j- m G m P m m k k P j- G j- G j m j P m k G m k P m G k m P k m Dig Cir p. 9 Revised; November 8, Slide 6 Addition The Brent-Kung Carry-Lookahead Adder The Brent-Kung Carry-Lookahead Adder Brent and Kung introduced a generalized generate and propagate. ThusP m k represents a composite propagate from adder m down to adder k. For the adder s initial inputs a m and b m :- P m m =P m =a m- +b m-, P = After the initial inputs:- P m k =P m P m- k =P m j P j- k Examples: P 5 =P 5 P P P P m =P m P m- P m-...p P 5 =P 5 5 P, P 5 =P 5 P Also G k m represents a composite generate between adders m thru k. For the initial adder inputs a m and b m :- G m m =G m =a m- b m-, G =C which is often After the initial inputs:- G m k =G m +P m G m- k =G m j +P m j G j- k Examples: G m =C m G 5 =G 5 +P 5 G (a) =G 5 +P 5 (G +P G ) (b) =(G 5 +P 5 G )+P 5 P G = G 5 + P 5 G (c) (c) P G G P a m- b m- G 5 5 P 5 5 G 5 P 5 P G P G G P G 5 5 P 5 5 (c) (a) (b) G m P m G 5 P 5 G 5 P 5 G 5 P 5 Digital Circuits p. Revised; November 8, Comment on Slide 6

Addition Generalized generate and propagate. P m k is a propagate between adder m and adder k If P k m = then: C k- can propagate thru the adders that produce G k,g k+... G m and P k,p k+... P m (adders Σ k-,..., Σ m- ) It comes out on C m Example If P 7 = then: a b a 6 b 6 5 6 C G P G 7 P 7 G 7 P 7 C 7 Propagated Carry C can propagate thru adders Σ to Σ 6 and come out as C 7 G m k is a generate for adders m thru k that reaches m. If G k m = then: a carry was generated inside the block of adders that produce G k,g k+... G m and P k,p k+... P m and propagated inside the block to the output. Example If G 7 = then: a carry was generated on G,G 5, G 6, and/or G 7 itwasabletopropagatetotheoutput G 7. and come out on C 7 a b a 6 b 6 5 6 C G P G 7 P 7 G 7 P 7 Generated Carry C 7 Dig Cir p. Revised; November 8, Slide 6 Addition The Brent-Kung Carry-Lookahead Adder Add without an initial carry in C Larger Example G =C =G +P C =G + G =C =G +P C =G +P G G =G +P G G = G + P G =( G +P G )+(P P )(G +P G ) Since C, we do not have to waste an input, and the block can add -bit numbers. a b a b C G P G P G P G P G =G =C since C = G G G =C P P G P =p p p p p P G Here C P is taken as so this adds bit numbers. Digital Circuits p. Revised; November 8, Comment on Slide 6

Addition The Generalized Carry Operator Takes in two adjacent G and P pairs Puts out a merged G and P pair In General k G j- G k k m P j- j k G P m m j P m Example G P G P G =C P What to Remember The General Formula for combining carrys The j- j are absorbed j- k m j m k k G j- k P j- j G m P j m G m k P m k Dig Cir p. Revised; November 8, Slide 6 Addition Digital Circuits p. Revised; November 8, Comment on Slide 6

Addition The Brent-Kung Carry-Lookahead Adder Combining P m k and G m k b 6 a 6 b a b a b a C G m k =G m j +P m j G j- k G 7 =G 7 +P 7 G P m k =P m j P j- k P 7 =P 7 P G 7 P 7 6 5 G 7 P 7 G P G P P m m =P m G m m =G m G m =C m adder inputs C in a G P G G =C P G P G Carry structure inside this block G =C P Carry in, C, uses the first adder position. This block can only add two -bit numbers. b a b a P G P G G P P If C, always, then two -bit numbers can be added. b P Dig Cir p. 5 Revised; November 8, Slide 6 Addition 7. PROBLEM: Assume the implied interconnections to the left of the dividing line. Sketch the circuit with interconnections to calculate carrys C 8 through C 5 Do not increase the depth more than necessary. 8. 5 6 7 8 9 5 7 6 9 8 PROBLEM 5 7 6 7 7 98 8 8 5 5 5 5 5 7 5 8 Following the example of the compromise adder, Slide 58, show how to reduce the size of a few of the intermediate carrys in the Brent-Kung adder without reducing speed.one can only do the ones for the first n/ bits. There is not as much saving here as in the compromise adder. C 8 C 9 C C C C C C 5 Digital Circuits p. 6 Revised; November 8, Comment on Slide 6

Addition G P G P G =C P G P G P G =C P DEPTH= G P G G P G P G 7 G 7 =C 7 P 7 P G P G 5 P 5 G 5 P 5 G 5 P 5 6 G 7 6 P 7 G 7 P 7 P 7 G 6 G 7 6 P 6 G 7 P 7 G 8 P 8 G 9 P 9 G P G P 6 P 7 8 G 9 P 8 9 G P DEPTH= 8 G G =C 9 G 8 P 7 8 8 P 9 G P 8 G P 8 P P Brent-Kung Adder Showing Depth of Final Carry Depth = log (Number of bits) Dig Cir p. 7 Revised; November 8, Slide 6 Addition A Bit Brent-Krung Adder There were of the three-gate blocks when only a fast C was needed. None of this extra circuitry was needed for a ripple-carry adder using P and G. The gates to generate the initial P and G are needed but not shown in the above diagram. To get the other carries one must add another 9 three-gates pairs for a total of. This is shown on the next slide. Digital Circuits p. 8 Revised; November 8, Comment on Slide 6

Addition Brent-Kung Adder Showing extra hardware for intermediate carrys The depth is still or less The amount of hardware has nearly doubled. Gates From Prev. Picture New Gates For Intrnal Carrys DEPTH= DEPTH= C C C C 5 6 7 5 7 6 5 7 6 7 7 7 5 6 5 5 6 6 6 DEPTH= 7 8 8 C 5 C 6 C 7 C 8 8 9 9 8 98 8 9 8 7 9 8 9 8 7 8 C 9 C 7 8 C Dig Cir p. 9 Revised; November 8, Slide 65 Addition Brent-Kung Adder Summary Brent-Kung Adder Summary The depth of the carry chain increases by when the number of bits doubles. A depth of would allow 9 to 6 bit words. Alternately the depth is the ceiling(log (n)) where n is the number of bits. Remember that C takes up one bit position unless it is always zero. The delay goes up more quickly because of the large fanout as n increases. On Slide 6, one generalized gate fans out to 5 gates. An n bit adder will have one gate that fans out to about n/ gates. The number of generalized carry blocks is, for a (n/)log (n), when n is a power of. For bits or more, this adder has the maximum hardware of all the carry-lookahead adders. Its area is proportional to nlog(n). The area of the other carry look-ahead adders is proportional to n. It is a big power-hungry adder, but fast.. The ceiling is the smallest integer larger than a number Digital Circuits p. Revised; November 8, Comment on Slide 65

Addition Summary Of Adders Types (Previously Covered) () Ripple-Carry slow; delay = O(n) small; area = O(n) A B C C Σ A Σ B C A Σ B C A B C Σ () Carry Look-Ahead faster; delay = O(n).5x(ripple delay) large; area = O(n) x(ripple area) C () Brent-Kung fastest O(log (n)) largest O(nlog (n)) G area passes compromise carry look-ahead about n= A B A B C G C G C G P Σ Σ P P Σ Σ P G P G P G 5 G 5 P 5 5 A B 5 5 G C C C C C 5 A B P C C C Dig Cir p. Revised; November 8, Slide 66 Addition Properties of look-ahead adders Properties of look-ahead adders Area Brent-Kung Full look-ahead Compromise look-ahead Ripple with P&G Delay Ripple with P&G Full look-ahead Compromise look-ahead Brent-Kung To the final carry out. Some sum bits take a little longer. 6 6 Number of bits (n) Number of bits (n) O(n) notation The notation delay=o(n), means that the delay increases in proportion to n for large n. Thus delay=n is O(n), but so is delay = 6 + n because the 6 is negligible when n is large More generally if some property = a + bn + cn +dn thepropertyissaidtobeo(n ) because it increases proportional to n for large n. For n= or 8, small details in implementation, like buffer sizing, may make the look-ahead faster than Brent- Kung, but when n>, it is clear that Brent-Kung will beat the pants off the others. Digital Circuits p. Revised; November 8, Comment on Slide 66

Addition Summary Of Adders Types : (About to be covered) Four New Adder Types 5) Carry Skip Speeds up slowest C->C path with little extra area. Does not help other paths. MUX G P A B G P Σ C C C C C G P P P P When P P P P =, does not wait for the ripple carry. A B A B G P Σ G P Σ A Σ B C C 6) Carry Select Doubles area Very fast path C ->C Still delay = O(n) Σ STAGE STAGE Adder for C = Adder for C = A7 A6 A5 A A A A B7 B6 B5 B B B B C8 Adder for C = C Adder for C = Σ Calculate answers for both C = and for C = Select the correct one A B C Dig Cir p. Revised; November 8, Slide 67 Addition Properties of these new adders Properties of these new adders Carry-Bypass (Carry-Skip) This is much like the compromise look-ahead adder.: The logic is a little smaller because the gate to calculate C is smaller. The smaller gate will make the C -> C path slightly faster. The path A i,b i -> C will be slower. Carry-Select Calculate -bit sums with Cin= and Cin=. Use Cin to select the correct one. Double the size of the base adder. The path C ->C ->C 8 is very fast. The delay is mainly in the -bit adder block. For cascade blocks, the adds are all done in parallel. C beats the mux inputs at the C mux, but the data is waiting at the C 8 muxwhenthec control signal gets there. Digital Circuits p. Revised; November 8, Comment on Slide 67

Addition Types of Adders Summary: (About to be covered, cont) (7) Conditional Sum Adder Combination of carry-select carry-skip C out G P G P A B P A B P A B MUX A B Σ Σ Σ Σ G Σ Σ P G Σ Σ G P G P G G C (8) Carry Save Adder Σ Used for multiple adds A B D A B D Adding three -bit numbers C Σ C Σ Final answer C Σ C Σ Σ Σ Σ 7: 7: 7: 7: 7: 7: 7: 7: 7: C Σ C Σ C Σ 8: 7: 8: 7: 8: 7: C Σ C Σ 9: 8: 8: 7: Carry and Sum seperate C Σ : 9: C Σ : : : Adds nine 8-bit numbers Carry not propagated until the last adder. Dig Cir p. 5 Revised; November 8, Slide 68 Addition Properties of these new adders Properties of these new adders Conditional Sum Adder This is much like the compromise look-ahead adder. It calculates both sums and selects the correct one, like the carry-select adder. It calculates C much like the carry-bypass adder. It is probably the fastest adder after the Brent-Kung. Carry-Save Adder An adder for a different purpose. It is good for adding several numbers, such as in multipliers. It uses the carry inputs in its adders to add a third number. Three numbers go in and two (a vector of carry bits and a vector of sum bits) come out. At the end one must add the two vectors together with a normal adder which propagates the carries. However it saves propagating carries during each two-number add. Digital Circuits p. 6 Revised; November 8, Comment on Slide 68

The Carry-Bypass Adder) The Carry-Bypass Adder) Generate and Propagate Revisited Redefine P=A B Then when P=, C OUT =C IN Extend this across bits A B C IN C IN C OUT C OUT G=AB P=A B P +G C IN When P P P P =, C =C The Carry-Bypass Adder A B C A B C A B C A B C G G Σ G G P P Σ P Σ P Σ C C C MUX G P P P P C When P P P P =, do not wait for the ripple carry. Switch the MUX and get C =C directly. C -> C has two paths, one fast and one slow. The red (slow path) cannot actually happen and is called a false path. Dig Cir p. 7 Revised; November 8, Slide 69 The Carry-Bypass Adder) The Carry-Bypass Adder The Carry-Bypass Adder This circuit allows the carry to bypass certain adder sections where the propagate signals are all asserted. It speeds up the longest path where a carry propagates all the way from C to C Digital Circuits p. 8 Revised; November 8, Comment on Slide 69

False Paths False Paths An continuous path through combinational gates that: ) cannot be sensitized, or ) always has a faster sensitized parallel path. () () A= B A= B C= false path B A= fast path false path Sensitized Path sensitized path A path that can be made to propagate a signal change. Dig Cir p. 9 Revised; November 8, Slide 7 False Paths The Carry-Bypass Adder False Paths A false path is a connection through gates from the start to the end of the path which will never propagate a signal change (be sensitized) under proper operation.. False path when the complete path cannot be sensitized. The carry-bypass adder has that type of path. false path C redundant False path due to redundant circuitry. The term AB is redundant. Any signal change through the inverter in the B path, will get to F faster through CB. A B F=CB+CA+AB false path Digital Circuits p. Revised; November 8, Comment on Slide 7

False Paths False Paths Paths that will never propagate a signal change Long unused paths cause two problems, timing and testing Timing problems Static timing verification checks the delay of the longest combinational paths in a circuit. Path delay - input reg to output register - must be under a clock cycle. Here timing verification will say the clock period should be at least 7 ns. Ifthe7nspathisafalsepath, and the next longest real path is ns. The verifier will state the clock period > 8ns. You will likely believe it! Testing Problems Suppose the MUX in the carry-bypass adder was stuck up. The circuit would still work albeit more slowly. One needs a test in which the 8ns path output is definitely wrong for the 6 ns or so. Generating this glitch free test is very difficult. Also testing usually not done at maximum speed. CLK D C D C D C ns 7 ns D C D C D C CLK CLK ns PATH GOOD CIRCUIT 7 ns PATH FALSE PATH ONLY (IDEAL) FALSEPATHONLY(WITHGLITCHES) TESTER CHECKS HERE Dig Cir p. Revised; November 8, Slide 7 False Paths False Paths in the Carry-Bypass Adder False Paths in the Carry-Bypass Adder Timing Problems. Synchronous logic In synchronous logic the input flip-flop outputs change just after the active clock edge. These changes propagate through the combinational logic (gates only, no flip-flops). The outputs of the gates change.they may go up and down several times. Eventually the changes will die out and the logic levels will stabilize. After that a new active clock edge may come and store these stable values in the output flip-flops. One must have: (The clock period) > (longest delay through the combinational logic). False Paths A false path is one which can never propagate a level change to an output. A common reason is the false path has a redundant parallel path. The output gets the correct answer from another path in less time than the propagation delay through the false path. Another reason is that the gates in the false path cannot all turn on at once. Static Timing Verification false path After a circuit is designed and converted to a silicon layout, the delays in each gate can be calculated. A timing verifier is a program which goes through a logic circuit after all the gate delays have been estimated, and calculates that if all signals will be stable before the next clock edge. Unfortunately many of these programs only check the propagation delay along a path. They do not know if the output will be stabilized sooner by another parallel path. They do not know if the all the gates in the path can be turned on at once. Thus they will suggest making the clock slower than is actually needed. Digital Circuits p. Revised; November 8, Comment on Slide 7

False Paths The Redundant Carry-Bypass Adder (Carry-Skip) Case I. The Redundant Path Separate into - MUX up path - MUX down path A B C A B C Map for MUX UP, P P = C = (P P )E P P C E C C G MUX G P Σ G P Σ P P C A B A B E E E E E E E E E E E E E =G +P (G +P C ) =G +P G +P P C Recall we redefined P as P=A B P =A B A B A B P =A B MUX Control = P P E =G +P G +P P C C =(P P )E Map for MUX DOWN, P P = A B A B Variable entered maps: When P P =, map value = E When P P =, map value = C Shaded squares selected by MUX. squares are don't care squares, and never selected. C C C C C =(P P )C Dig Cir p. Revised; November 8, Slide 7 False Paths False Paths in the Carry-Bypass Adder False Paths in the Carry-Bypass Adder (cont.) Testing Problems The tester would: load the flip-flops with a test input, trigger a clock edge, wait for a clock period, and then trigger another clock edge and read the outputs as captured by the flip-flops. If the outputs are stable, it is easy to compare expected and actual signals. If the output is still active when the clock comes it is, difficult to predict what the actual signal will do. One needs to be sure the flip-flop will capture a wrong value if the faster path is defective. Designing such a test is difficult even for a single false path. Such tests cannot be done by normal test generation programs. Most modern tests do not test at the full clock speed. Scan tests, to be discussed later, do not run at full speed. Faster Circuits Do Not Have To Have False Paths False paths are not necessary. It was proven in99 that any redundant path, put in strictly to improve speed, could be replaced by a nonredundant circuit with no speed penalty. False paths are not necessary. K, Keutzer, S. Malik and A. Saldanha, Is Redundancy Necessary to Reduce Delay?, IEEE Trans, on CAD, April 99, pp 7-5. Digital Circuits p. Revised; November 8, Comment on Slide 7

False Paths The Redundant Carry-Bypass Adder (Carry-Skip) Case I. The Redundant Path (cont.) Show E is more complex than needed C = A B A B (P P )E P P C G =A B E C C G MUX G =A B A B C A B C G P Σ G P Σ A B A B Map of G Map of P G E =G +P G +P P C ) don't care squares. P P P G P G False Path, never selected here. Data travels over path selected here. P =A B P =A B C Map of Mux Control=P P A B P =A B A B P P P P P P P P MUX UP, P P = A B A B G G P G G P G G C =(P P )E E =G +P G +P P C Redundant MUX DOWN, P P = A B A B C C C C C C C C C C C C C C C C C =P P C Dig Cir p. 5 Revised; November 8, Slide 7 False Paths The Redundant Carry-Bypass Adder The Redundant Carry-Bypass Adder The Maps for E, the Upper MUX Input Three maps, G,P G and P P, derive the expression for E. The left map encircles the G term. These squares will be s ofe. The centre map encircles the two columns of P and the row of G. The term is P G so the intersection of the circles will be s ofe. The lower centre map shows P P as the four squares at the intersections of the columns, P,andthe rows, P. TheORofthethreemapsisE and is shown in the MUX UP map. The MUX DOWN map shows P P C. The value C is placed in those squares. This avoids making a5-variablemap. Don't Care Conditions Caused By Multiple Equations. The four squares in the MUX UP map are don t care because the mux is always down (P P =) for those four squares. For the function E, those squares contain the value of C, but who cares, they never transfer this value to the output C. The twelve squares in the MUX DOWN map are don t care because the mux is down (P P =) for only four squares. The map is actually filled with the value of C, but only the four useful ones are shown. Digital Circuits p. 6 Revised; November 8, Comment on Slide 7

False Paths The Redundant Carry-Bypass Adder (Carry-Skip) Case II. A Nonredundant Path (cont.) E is reduced to H Redundant path removed C = A B A B (P P )H P P C G =A B H C C G MUX G =A B A B C A B C G P Σ G P Σ A B A B Map of G Map of P G H =G +P G +P P C ) don't care squares. P P P G P G False Path, removed. Data travels over path selected here. P =A B P =A B C Map of Mux Control=P P A B P =A B A B P P P P P P P P MUX UP, P P = A B A B G G P G G P G G C =(P P )H H =G +P G No false path MUX DOWN, P P = A B A B C C C C C C C C C C C C C C C C C =P P C Dig Cir p. 7 Revised; November 8, Slide 7 False Paths A Nonredundant Carry-Bypass Adder A Nonredundant Carry-Bypass Adder The Upper MUX Input In the previous slide E =G +P G +P P C The P P C term was redundant because it was never when the mux was in its upper position. This term is only used in the lower mux position. In this slide we drop P P C from E leaving E =G +P G This removes the false path. C no longer appears to have a path through the upper position in the mux. Digital Circuits p. 8 Revised; November 8, Comment on Slide 7

False Paths Case III. The Simpler Nonredundant Path Faster than the previous one! F =G +P A A B C A B C MUX UP, P P = C = A B A B (P P )F P P C Map of G G =A B F C C G MUX G P Σ G P Σ A P P A B A B P =A B A Map of A P A P A P A P A P C A B A B G G A P G A P G A P A P F =G +P A C =(P P )F MUX DOWN, P P = P =A B Map of Mux Control=P P A B A B P P P P A B A B C C C C C C C C C C C C C C C C P =A B P P P P C =P P C Dig Cir p. 9 Revised; November 8, Slide 75 False Paths The Carry-Bypass Adder, Nonredundant The Carry-Bypass Adder, Nonredundant Circuit Here the P P C term is replaced by A. The new output F is the same as the previous E except for the four don t care Compare E and F equations and maps. E =G +P G +P P C ) F =G +P A The P P C term only appeared in the don t care squares. It was removed. squares. The P G only appeared in two squares. It was replaced by a P A that made those two squares correct but changed the don t care squares. Summary The don t care terms were caused by partitioning the logic into several functions. The don t care terms were utilized to remove redundant logic and false a path. Now both the static-timing verifier and the test engineer are happy. 9. PROBLEM Recall that here P =A B. The term P A is on the time-critical path, and can be replaced by a slightly faster term. However it will cost a few extra transistors because one will not be able to utilize the adders XOR gate. Find this revised circuit. Digital Circuits p. Revised; November 8, Comment on Slide 75

Adders The Carry Select Adder Trade silicon for speed. Uses Two Adders. Do parallel adds One based on C =. The other for C =. Use C to select the correct answer. Time Saving Onestagesaveslittletime. Best with many stages. The add blocks are all done in parallel. The carries ripple through the stages with one MUX delay per stage. Σ Σ Σ Σ C G Adders MUX G MUX Σ Σ Σ Σ YOUR FAVORITE -BIT ADDER -stage time delay = time for -bit add + *(delay thru MUX) C C C = A A A A B B B B YOUR FAVORITE -BIT ADDER Σ Σ Σ Σ C = C Σ STAGE Σ STAGE Σ STAGE A8 A C A B A B A9 B9 B8 C8 A7 B7 A6 B6 A5 B5 B C A B A B A B A B C Dig Cir p. Revised; November 8, Slide 76 Adders The Carry-Select Adder The Carry-Select Adder A Fast, But Large, Adder This adder consists of two normal adders in parallel. They might be ripple-carry or carry look-ahead, or any other type. They would usually be -bits adders or more. One adder adds as if C =, the other as if C =. The real C selects the correct answer with a MUX. Speed The -bit single MUX carry-select adder saves only one or two gate delays in the right-hand section. Probably about the same as the extra delay added by the MUX. The carry-select adder is best for long word lengths broken into sections. For example bits made of 8 sections of bits each. All the adds are done at the same time, so there is an initial delay for them to finish. Then the sums and carry outputs are available, but no one knows which to use. Then the carry must propagate serially through the chain of MUXs, each carry switching a MUX which selects a carry, which in turn is used as the control for the next MUX. This delay increases linearly with the number of MUXs. However it is faster than most other systems which increase linearly with the number of full adders.. PROBLEM Does the carry-select adder contain redundant paths? HINTS Are there two apparent paths for the carry? Check the paths, is one ever turned off so a change cannot propagate through it, while the other is turned on? Alternately do two paths give the same answer but one path clearly always faster than the other. Digital Circuits p. Revised; November 8, Comment on Slide 76

Adders The Carry-Select Adder (Cont.) The two adders can share some circuitry C = Σ = P C PREV C Σ Σ Σ Σ C PREV Σ Σ Σ Σ MUX G C MUX G G P G A P G A P G A P A P G P G P G P G B B B B C C = G P G P G P G P Σ Σ Σ Σ C C G P common The common blocks contain G=AB; P= A B. The distinct (striped) block contain S=P C PREV ; C=G+PC OLD for each bit About 6% more area than a single adder. Dig Cir p. Revised; November 8, Slide 77 Adders The Carry-Select Adder (Cont.) The Carry-Select Adder (Cont.) Sharing Circuitry The propagate and generate circuits are common to the upper and lower adders because they do not use the carry. The other circuits involve carries and must be separate.. PROBLEM Since the c input is known to be or, redesign the first full-adders in each -bit chain to utilize this fact. Digital Circuits p. Revised; November 8, Comment on Slide 77

Conditional Sum Adder Conditional Sum Adder A B B A B A A B Σ Σ Σ Σ Σ Σ Σ Σ G P G P G G P P G G G P =P P C P =P P P =P P C out MUX G Σ Σ Σ Σ Dig Cir p. 5 Revised; November 8, Slide 78 Conditional Sum Adder The Conditional-Sum Adder The Conditional-Sum Adder At one time considered to be the fastest adder theoretically. It combines features of the carry look-ahead, the carry-select, and the carry-bypass adders. Each adder block calculates: P = carry out if there is a carry in, Cout(C =). G= carry out if it is independent of a carry in, Cout(C =). Σ = sum out if carry in is, Σ(C in =). Σ = sum out if carry in is, Σ(C in =). Select the right carry and the right sum outside the adder block Outside the adder block the previous P and G lines along with C are used to select the proper sum. The proper carry out is G if C= and P if C= However the proper one is not selected immediately. Both are passed on to the next adder block. The next block upgrades P and G and passes them on. The carry out from a block of (usually four) adders is selected from the previous P and G by C. Digital Circuits p. 6 Revised; November 8, Comment on Slide 78

Conditional Sum Adder Calculate both sum and carry values Σ if C Sum Σ k = k = Carry out C k = Σ if C k = Select the correct sum to send out Select the right carry to send on. G k if C k- = P k if C k- = Calculate in the adder box Σ k- =A k- B k- Σ k- =A k- B k- G k =A k- B k- P k =A k- +B k- A B G k+ = carry out from the kth adder G k+ = carry out from the kth adder ignoring C. (C =) G k+ = carry out from the kth adder ignoring G,P,andC. (G ==C ) G P Σ Σ G =G +P G P n =P n P n- P P If (P n ==), then G =G +P G P =P P abitcan propagate C Þ C out G n =G n +P n G n- P n =P n P n- P =P P C C out =G n = P n P n- P P Σ Dig Cir p. 7 Revised; November 8, Slide 79 Conditional Sum Adder The Conditional-Sum Adder Carry Calculations The initial carry C bypasses all intermediate carry calculations Two carries are calculated: OneGisvalueofthecarryifC = The other P is the value if C =. C is not used to tell which carry is correct until the final output carry. Notice that the propagation delay for P is exactly that of the carry-bypass adder, the delay of ANDs and ORs. Also note that the next block takes in C and sends out C 8. The signals P and G are calculated in parallel with those in the first block, so C 8 does not have to wait extra time for its P and G. The delay for C 8 is that of 5 ANDs and Ors Calculated in parallel Σ Σ Σ Σ Σ Σ Σ Σ Σ Σ Σ Σ Σ Σ Σ Σ C C C 8. A. Bellaouar and M Elmasary, Low-powered Digital VLSI Design Circuits and Systems, Kluwer 995, p. has a good summary of the csa.. Digital Circuits p. 8 Revised; November 8, Comment on Slide 79

Conditional Sum Adder Conditional Sum Adder Carry Calculations G = carry out from the th adder = C out G = carry out from the th adder with C = P =P P P P If (P =) if a carry would propagate through all adders i.e C = Þ C out = A B A B A B A B G Σ Σ G Σ Σ Σ Σ Σ Σ G G C if C is ignored P P G =G +P G P P C if C is ignored C if C is ignored G = G +P G G =G +P G P =P P C P =P P C out =G P =P P Σ Σ Σ Σ Dig Cir p. 9 Revised; November 8, Slide 8 Conditional Sum Adder The Conditional-Sum Adder Carry Calculations The G chain This is the same as the carry chain in the P and G ripple adder except it does not contain C. It calculates C, C, C and C, ignoring C. The P chain This is the same as the P chain in the carry-bypass adder, except, as shown on the next page, it has taps to select the correct sum for individual full adders. Comparison with other schemes Combination of carry-select and carry-bypass adders Like the carry-select adder, it calculates both Σ(C =) and Σ(C =). It sends C -> Cout directly if all propagate signals are true, like the carry-bypass adder. Thus the propagate time, if C goes to Cout is almost the same as for the carry-bypass adder. The extra P line loading will slow it a little. Note also this carry bypass is done for all the adders, for example Σ is controlled by P P P C. This means the individual sum terms will be faster than in the carry look ahead adder which uses G +P (G +P (G +P C ))) to propagate C into adder. It uses the generalized generate signal G k n which signals if a carry comes from circuitry between adders n and k. This is like the Brent-Kung adder, except here it uses only G n It does not use the logarithmic carry propagation so, for long word lengths, it will be slower than Brent-Kung. There is an alternate implementation of the carry-select adder which uses transmission gates.. See Jan M. Rabaey, Digital Integrated Circuits, Prentice Hall, 996, Chapt. 7, Prob. 8, pp. 9-. Digital Circuits p. 5 Revised; November 8, Comment on Slide 8

Conditional Sum Adder Conditional Sum Adder Selecting the sum terms Σ Σ Sum if carry in is Sum if carry in is carry in = G k =G k +P k C G k P k C B A A B A B A B Σ Σ Σ Σ Σ Σ Σ Σ C GP Σ Σ Σ Σ Σ Σ Σ Σ G G G P G G P P P G G P =P P C P =P P P =P P C out MUX G Σ Σ Σ Σ Dig Cir p. 5 Revised; November 8, Slide 8 Conditional Sum Adder Conditional Sum Adder Conditional Sum Adder Digital Circuits p. 5 Revised; November 8, Comment on Slide 8

Conditional Sum Adder Reducing Delay By Gradually Increasing Stage Length The stages calculate in parallel Their outputs reach the carry muxs at the same time (with equal lengths). Path delay increases by a mux delay at each stage. If (mux delay) (G P delay), can do one more add in each successive stage. Carry-Select C 9 STAGE path STAGE STAGE Inputs 5 to 8 bits path C 5 Inputs to bits C Inputs to bits C Delay now increases as sqrt(n), O( n), instead of linearly with n, O(n). Carry-Bypass STAGE path STAGE STAGE path Inputs 5 to 8 Inputs to Inputs to S bits S bits S bits C C 9 C 5 C path Dig Cir p. 5 Revised; November 8, Slide 8 Conditional Sum Adder Increasing Stage Length Increasing Stage Length Renumber the carrys by stage by making the output carry of stage k be S k. In the picture, S =C,S =C,... Balance delays so path and path k are equal. Path k is the longest path from some stage k input to S k. τ k is its path delay. Path is shown. In the first stage, signal C will reach S beforethesignalonpath,sothedelaytos is τ. After that, as long as path k can reach mux k before the signal along path, then (delayalongpathuptocarrys k )=τ k = τ +k*τmux The increase in delay between τ k and τ (k+) is one mux delay as long as path k+ can reach the mux k before the signal along path. Thus we can increase the delay along each path k by one mux delay for each stage. Thus τ m, the total carry-out delay for m stages, is τ +m*τ mux The number of full adders, n = +++5+...+ m = m(m+)/ -. Solve the quadratic equation to find m = -.5 + (.5 + n) For n>>.5 τ m τ mux n (Sum of arithmetic series) Balancing the whole sum Carry-Bypass The circuits above have the delay to the final carry faster than to some of the high order bits of the sum. Then one of the critical paths is shown on the right. Here the stage length is decreased symmetrically on both ends to equalize the delay to the final sum bit in each stage. Carry-Select Here the final sum is selected in parallel by the carry. Shortening the most-significant end is not necessary. Digital Circuits p. 5 Revised; November 8, Comment on Slide 8

Conditional Sum Adder Comparison of Adders Delay Ripple Look Ahead Bypass Select Area Lookahead Bypass Skip Ripple 8 Number of bits (n) Number of bits (n) Adapted from Rabaey. The carry select adder area and speed depends on the stage your favourite adder type. Details will change relative properties, particularly for low n.. Jan M. Rabaey, Digital Integrated Circuits, Prentice Hall, 995. pp. 99,,. Dig Cir p. 55 Revised; November 8, Slide 8 Conditional Sum Adder Summary of Adders Summary of Adders Ripple-carry adder is the smallest and the lowest power consumption, and for short words it may be fastest. The bit-serial version is very small and very slow. It takes in and gives out bit streams. See Lealand Jackson, Digital Filters and Signal Processing, Kluwer 989, pp -5. The Brent-Kung adder is by far the fastest, but it gets very large. The conditional-sum adder is the second choice for speed, and has much less area. Experience with Small Adders For small adders, O(n) approximations may be misleading. For to 7 bit adds, using library Designware, a Carleton graduate student, Youxing Zhao found: The conditional sum adder (csa) was the fastest. The ripple carry adder (rpl) was second and significantly slower. The fast carry look-ahead (clf) was third. The Brent-Kung (bk) and the carry look-ahead adder (cla) were last and about the same. Digital Circuits p. 56 Revised; November 8, Comment on Slide 8

Ripple-Carry Adder Verilog Adders Verilog Adders module ripple_add8(cout,s,a,b,cin); input [7:] a, b, input cin; output [7:] s; reg [7:] s; output cout; reg cout; integer i; wire cy; always @(a or b or cin) begin cy=cin for (i=; i<=7; i=i+) begin {cy, s[i]) = a[i] + b[i] + cy; end cout=cy; end endmodule // ripple_add8 cout a[7] b[7] FA7 c a[] b[] FA c a[] b[] FA c a[] b[] FA c a[] b[] FA cin s[7] s[] s[] s[] s[] Dig Cir p. 57 Revised; November 8, Slide 8 Verilog Adders Verilog Adders Verilog Adders Ripple-Carry Adder Connections The input and output ports, a, b, cin, cout and s, do not have to be declared again. The internal connection, c, c,..., normally would be declared. However: Wires do not have to be declared explicitly if they serve as wiring between arguments of module instantiations. For example c, c,... Module Definitions We define a module ripple_add8 and a module fulladder. Ripple_add8 calls fulladder eight times. The definition of a module must be completely outside the definition of any other module. Note the endmodule statement for ripple_add8 came before module fulladder started Behavioural Model for Adder The full adder was defined by logic equations rather than gates. This allows a logic synthesizer to choose how the gates are to be put together. For example it might factor the carry into: a(b + c) + bc. Normally the synthesizer will do a much better job than the designer. Two exceptions are:. when custom cells available that are not in the synthesizer library.. When the logic is too much for the minimizer. Carry-select adders are probably too much. Digital Circuits p. 58 Revised; November 8, Comment on Slide 8

Verilog Adders Carry Lookahead Adder module lookahead_add8(cout,s,a,b,cin); input [7:] a, b; input cin; output [7:] s; output cout; wire ca; cout ca cin LA_b LA_a lookahead_ LA_a(ca, s[:],a[:],b[:],cin], LA_b(cout, s[7:],a[7:],b[7:],ca]; endmodule //lookahead_add8 module lookahead_(cout,s,a,b,cin); input [:] a, b, cin; output [:] s; output cout; wires [:] c, p, g; // Connect the carry, cin, and carry lookahead c[i]. assign c[] = cin, c[] = g[] p[]&c[], c[] = g[] p[]&g[] p[]&p[]&c[], c[] = g[] p[]&g[] p[]&p[]&g[] p[]&p[]&p[]&c[], cout = g[] p[]&g[] p[]&p[]&g[] p[]&p[]&p[]&g[] p[]&p[]&p[]&p[]&c[]; // Connect propagate and generate signals; connect the sum. assign p = a^b, g = a&b, s = p^c; end module // lookahead_ Dig Cir p. 59 Revised; November 8, Slide 85 Verilog Adders Carry Lookahead Adder Carry Lookahead Adder Connections The input and output ports, a, b, cin, cout and s, do not have to be declared again. The internal connection, ca, was declared. However in this case it was optional (see below). Wires do not have to be declared explicitly if they serve as wiring between arguments of module instantiations. For example declaration of ca in LA_a and LA_b, is optional. Nonprocedural Verilog Is a Circuit Note again that Verilog statements, except in procedures, are definitions of connections. The order of the statements does not matter any more than it matters which gate is put at the top of a wiring diagram. The two -bit sections are coupled by a ripple carry The Carry Lookahead Code the equations were written to follow my guess at the fastest implementation. A good synthesizer may change the gate connections considerably. Digital Circuits p. 6 Revised; November 8, Comment on Slide 85