-SAGE ASYHONOUS BINAY COUNES AND OSCILLAOS SCLSB DECEMBE 82 EVISED MAY Allow Design of Either C or Crystal Oscillator Circuits Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description he HC00 consist of an oscillator section and ripple-carry binary counter stages. he oscillator configuration allows design of either C or crystal-oscillator circuits. A high-to-low transition on the clock () input increments the counter. A high level at the clear (CL) input disables the oscillator ( goes high and goes low) and resets the counter to zero (all Q outputs low). he SNHC00 is characterized for operation over the full military temperature range of C to 2 C. he SNHC00 is characterized for operation from 0 C to 8 C. logic symbol CL 2 + C=0 C C & Z 2 0 QD QE QF QG QH QI QJ QL QM QN SNHC00... J O W PACKAGE SNHC00...D O N PACKAGE (OP VIEW) Q L Q M Q N Q F Q E Q G Q D GND 2 8 2 0 SNHC00... FK PACKAGE (OP VIEW) Q N Q F Q E Q G Q M Q L V CC Q 2 20 8 8 02 Q D GND No internal connection V CC Q J Q H Q I CL J Q H Q I CL his symbol is in accordance with ANSI/IEEE Std -8 and IEC Publication -2. Pin numbers shown are for the D, J, N, and W packages. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of exas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PODUCION DAA information is current as of publication date. Products conform to specifications per the terms of exas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, exas Instruments Incorporated POS OFFICE BOX 0 DALLAS, EXAS 2
-SAGE ASYHONOUS BINAY COUNES AND OSCILLAOS SCLSB DECEMBE 82 EVISED MAY logic diagram (positive logic) QF 2 QI QL QM QN QG QH QJ CL 2 0 Pin numbers shown are for the D, J, N, and W packages. QD QE absolute maximum ratings over operating free-air temperature range Supply voltage range, V CC.......................................................... 0. V to V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note ).................................... ±20 ma Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note )................................ ±20 ma Continuous output current, I O (V O = 0 to V CC ).............................................. ±2 ma Continuous current through V CC or GND................................................... ±0 ma Package thermal impedance, θ JA (see Note 2): D package.................................. C/W N package................................... 8 C/W Storage temperature range, stg................................................... C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. hese are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOES:. he input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. he package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a trace length of zero. 2 POS OFFICE BOX 0 DALLAS, EXAS 2
-SAGE ASYHONOUS BINAY COUNES AND OSCILLAOS recommended operating conditions SCLSB DECEMBE 82 EVISED MAY SNHC00 SNHC00 UNI MIN NOM MAX MIN NOM MAX Supply voltage 2 2 V = 2 V.. VIH High-level input voltage =. V.. V = V.2.2 = 2 V 0 0. 0 0. VIL Low-level input voltage =. V 0. 0. V = V 0.8 0.8 VI Input voltage 0 0 V VO Output voltage 0 0 V = 2 V 0 000 0 000 tt Input transition (rise and fall) time =. V 0 00 0 00 ns = V 0 00 0 00 A Operating free-air temperature 2 0 8 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMEE ES CONDIIONS A = 2 C SNHC00 SNHC00 MIN YP MAX MIN MAX MIN MAX 2 V..8.. All outputs VI = VIH or VIL IOH = 20 µa. V.... VOH V.... V Q outputs VI =VIH or VIL IOH = ma. V.8...8 IOH =.2 ma V.8.8.2. 2 V 0.002 0. 0. 0. All outputs VI = VIH or VIL IOL = 20 µa. V 0.00 0. 0. 0. VOL V 0.00 0. 0. 0. V Q outputs VI =VIH or VIL IOL = ma. V 0. 0.2 0. 0. IOL =.2 ma V 0. 0.2 0. 0. II VI = or 0 V ±0. ±00 ±000 ±000 na ICC VI = or 0, IO = 0 V 8 0 80 µa Ci 2 V to V 0 0 0 pf UNI POS OFFICE BOX 0 DALLAS, EXAS 2
-SAGE ASYHONOUS BINAY COUNES AND OSCILLAOS SCLSB DECEMBE 82 EVISED MAY timing requirements over recommended operating free-air temperature range (unless otherwise noted) A = 2 C SNHC00 SNHC00 MIN MAX MIN MAX MIN MAX 2 V 0. 0. 0. fclock Clock frequency. V 0 28 0 0 22 MHz tw Pulse duration V 0 0 22 0 2 2 V 0 high or low. V 8 2 2 V 2 20 2 V 0 CL high. V 8 2 2 V 2 20 2 V 0 20 200 tsu Setup time, CL inactive before. V 2 8 0 ns V 2 UNI ns switching characteristics over recommended operating free-air temperature range, C L = 0 pf (unless otherwise noted) (see Figure ) PAAMEE FOM (INPU) O (OUPU) A = 2 C SNHC00 SNHC00 MIN YP MAX MIN MAX MIN MAX 2 V. 0.. fmax. V 28 22 MHz V 22 2 2 V 20 0 tpd QD. V 8 8 2 ns V 2 8 2 0 2 V 0 20 tphl CL Any Q. V 8 28 2 ns V 2 0 2 V 28 0 tt Any. V 8 22 ns V 0 UNI operating characteristics, A = 2 C PAAMEE ES CONDIIONS YP UNI Cpd Power dissipation capacitance No load 88 pf POS OFFICE BOX 0 DALLAS, EXAS 2
-SAGE ASYHONOUS BINAY COUNES AND OSCILLAOS PAAMEE MEASUEMEN INFOMAION SCLSB DECEMBE 82 EVISED MAY Input From Output Under est tplh est Point LOAD CICUI CL = 0 pf (see Note A) tphl eference Input Data Input 0% tsu 0% 0% tr VOLAGE WAVEFOMS SEUP AND INPU ISE AND FALL IMES 0% tf In-Phase Output Out-of-Phase Output 0% tphl 0% 0% 0% tr 0% 0% tf tplh VOH 0% VOL tf VOH 0% VOL tr High-Level Pulse Low-Level Pulse tw VOLAGE WAVEFOMS POPAGAION DELAY AND OUPU ANSIION IMES VOLAGE WAVEFOMS PULSE DUAIONS NOES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: P MHz, ZO = 0 Ω, tr = ns, tf = ns. C. For clock inputs, fmax is measured when the input duty cycle is. D. he outputs are measured one at a time with one input transition per measurement. E. tplh and tphl are the same as tpd. Figure. Load Circuit and Voltage Waveforms POS OFFICE BOX 0 DALLAS, EXAS 2
-SAGE ASYHONOUS BINAY COUNES AND OSCILLAOS SCLSB DECEMBE 82 EVISED MAY CONNECING AN C OSCILLAO CICUI O HE HC00 he HC00 consist of an oscillator section and ripple-carry binary counter stages. he oscillator configuration allows design of either C or crystal-oscillator circuits. When an C oscillator circuit is implemented, two resistors and a capacitor are required. he components are attached to the terminals as shown below: 2 8 2 0 2 C o determine the values of capacitance and resistance necessary to obtain a specific oscillator frequency (f), use this formula: f 0.0 2 2()(C). 0.. 2 If 2 > > (i.e., 2 = 0), the above formula simplifies to: f 0. C POS OFFICE BOX 0 DALLAS, EXAS 2
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