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INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic Package Outlines Octal D-type flip-flop; positive edge-trigger; File under Integrated Circuits, IC06 December 1990
Octal D-type flip-flop; positive edge-trigger; FEATURES non-inverting outputs for bus oriented applications 8-bit positive, edge-triggered register Common output enable input Independent register and buffer operation Output capability: bus driver I CC category: MSI GENERA DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the OW-to-IG CP transition. When OE is OW, the contents of the 8 flip-flops are available at the outputs. When OE is IG, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 374 is functionally identical to the 34, but has non-inverting outputs. QUICK REFERENCE DATA GND = 0 V; T amb =2 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS C CT UNIT t P / t P propagation delay CP to Q n C = 1 pf; V CC = V 1 13 ns f max maximum clock frequency 77 48 Mz C I input capacitance 3. 3. pf C PD power dissipation capacitance per flip-flop notes 1 and 2 17 17 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1. V ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December 1990 2
PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1 OE output enable input (active OW) 2,, 6, 9, 12, 1, 16, 19 Q 0 to Q 7 flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 D 0 to D 7 data inputs 10 GND ground (0 V) 11 CP clock input (OW-to-IG, edge-triggered) 20 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December 1990 3
FUNCTION TABE OPERATING MODES load and read register load register and disable outputs INPUTS INTERNA OUTPUTS OE CP D n FIP-FOPS Q 0 to Q 7 l h l h Z Z Notes 1. = IG voltage level h = IG voltage level one set-up time prior to the OW-to-IG CP transition = OW voltage level I = OW voltage level one set-up time prior to the OW-to-IG CP transition Z = high impedance OFF-state = OW-to-IG CP transition Fig.4 Functional diagram. Fig. ogic diagram. December 1990 4
DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI AC CARACTERISTICS FOR 74C GND = 0 V; t r =t f = 6 ns; C =0pF SYMBO t P / t P t PZ / t PZ t PZ / t PZ PARAMETER propagation delay 0 CP to Q n 18 14 output enable time OE to Q n 41 1 12 output disable time 0 OE to Q n 18 14 t T / t T output transition time 14 4 t W t su t h f max clock pulse width IG or OW set-up time D n to CP hold time D n to CP maximum clock pulse frequency T amb ( C) 74C +2 40 to +8 40 to +12 min. typ. max. min. max. min. max. 80 16 14 60 12 10 30 3 19 7 6 14 4 6 2 2 23 70 83 16 33 28 10 30 26 10 30 26 60 12 10 100 20 17 7 1 13 4.8 24 28 20 41 3 190 38 33 190 38 33 7 1 13 120 24 20 90 18 1 4.0 20 24 20 0 43 22 4 38 22 4 38 90 18 1 UNIT TEST CONDITIONS V CC (V) 4. 4. 4. 4. 4. 4. 4. Mz 2.0 4. WAVEFORMS Fig.7 Fig.7 Fig.8 Fig.8 December 1990
DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE CP D n UNIT OAD COEFFICIENT 1.2 0.90 0.3 AC CARACTERISTICS FOR 74CT GND = 0 V; t r =t f = 6 ns; C =0pF T amb ( C) TEST CONDITIONS 16 32 40 48 ns 4. 16 30 38 4 ns 4. Fig.7 18 28 3 42 ns 4. Fig.7 74CT SYMBO PARAMETER UNIT V WAVEFORMS +2 40 to +8 40 to +12 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay CP to Q n t PZ / t PZ output enable time OE to Q n t PZ / t PZ output disable time OE to Q n t T / t T output transition time 12 1 18 ns 4. t W t su t h f max clock pulse width IG or OW set-up time D n to CP hold time D n to CP maximum clock pulse frequency 19 11 24 29 ns 4. 12 7 1 18 ns 4. Fig.8 3 ns 4. Fig.8 26 44 21 17 Mz 4. December 1990 6
AC WAVEFORMS (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Waveforms showing the clock (CP) to output (Q n ) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the enable and disable times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 0%; V I = GND to V CC. CT : V M = 1.3 V; V I = GND to 3 V. Fig.8 Waveforms showing the data set-up and hold times for D n input. December 1990 7
PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December 1990 8