The MC06 contains six high speed, master slave type D flip flops. Clocking is common to all six flip flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive going Clock transition. Thus, outputs may change only on a positive going Clock transition. A change in the information present at the data (D) input will not affect the output information any other time due to the master slave construction of this device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT. RESET ONLY FUNCTIONS WHEN CLOCK IS LOW. P D = 460 mw typ/pkg (No Load) f toggle = 0 MHz (typ) t r, t f =.0 ns typ (0% 0%) LOGIC DIAGRAM CDIP L SUFFIX CASE 60 PDIP P SUFFIX CASE 64 MARKING DIAGRAMS MC06L AWLYYWW MC06P AWLYYWW PLCC 0 FN SUFFIX CASE 77 06 AWLYYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week DIP PIN ASSIGNMENT CLOCKED TRUTH TABLE R C D Qn + L L X Q n L H* L L L H* H H H L X L *A clock H is a clock transition from a low to a high state. Pin assignment is for Dual in Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page of the ON Semiconductor MECL Data Book (DL/D). ORDERING INFORMATION Device Package Shipping MC06L CDIP Units / Rail MC06P PDIP Units / Rail MC06FN PLCC 0 46 Units / Rail Semiconductor Components Industries, LLC, 00 January, 00 Rev. 7 Publication Order Number: MC06/D
MC06 ELECTRICAL CHARACTERISTICS Characteristic Symbol Test Limits Pin Under 30 C + C + C Test Min Max Min Typ Max Min Max Unit Power Supply Drain Current I E 0 madc Input Current I inh 9 Output Voltage Logic V OH Output Voltage Logic 0 V OL Threshold Voltage Logic V OHA Threshold Voltage Logic 0 V OLA Switching Times (0Ω Load) Propagation Delay t +3 t +4 t 9++ t 9+ 30 49 90 0 30 7 0 30 7 µadc I inl 0. 0. 0.3 µadc 3 4.060.060.90.90.00.00 0.90 0.90 7 7 0.960 0.960.0.0 0.90 0.90 0.0 0.0 0 0 30 30 0.90 0.90.. 0.90 0.90 Rise Time (0 to 0%) t +.0 4... 4.0. 4.4 Fall Time (0 to 0%) t.0 4... 4.0. 4.4 0.700 0.700.9.9 Setup Time t setup.... ns Hold Time t hold.... ns Toggle Frequency (Max) f tog 0 MHz 4.6 4.6 4.6 4.6.. 3. 3. 4. 4. 4. 4..0.0.0.0 Vdc Vdc Vdc Vdc ns Output level to be measured after clock pulse. appears at clock input (Pin 9).
MC06 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic @ Test Temperature V IHmax V ILmin V IHAmin V ILAmax V EE Symbol 30 C 0.90.90.0.00. + C 0.0.0.0.47. + C 0.700..03.440. Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW Under (V CC ) Test V IHmax V ILmin V IHAmin V ILAmax V EE Gnd Power Supply Drain Current I E Input Current I inh 9 Output Voltage Logic V OH Output Voltage Logic 0 V OL Threshold Voltage Logic V OHA Threshold Voltage Logic 0 V OLA 9 I inl Switching Times (0Ω Load) +.Vdc +0.3V Pulse In Pulse Out 3. V +.0 V Propagation Delay t +3 t +4 t 9++ t 9+ 3 4 Rise Time (0 to 0%) t +, 9 Fall Time (0 to 0%) t, 9 Setup Time t setup, 9 Hold Time t hold, 9 Toggle Frequency (Max) f tog 6 7, 9, 9, 9, 9 3 4 Output level to be measured after clock pulse. appears at clock input (Pin 9). Each MECL 0,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 00 linear fpm is maintained. Outputs are terminated through a 0 ohm resistor to.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. 3
MC06 PACKAGE DIMENSIONS PLCC 0 FN SUFFIX PLASTIC PLCC PACKAGE CASE 77 0 ISSUE C B N Y BRK U D L M Z W D X G V VIEW D D Z A R K H C G G E J T VIEW S VIEW S K F 4
MC06 PACKAGE DIMENSIONS T F A E G D PL B C N CDIP L SUFFIX CERAMIC DIP PACKAGE CASE 60 0 ISSUE T K L M J PL H A G B F C S K D PL T PDIP P SUFFIX PLASTIC DIP PACKAGE CASE 64 0 ISSUE R J L M
MC06 Notes 6
MC06 Notes 7
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