EE 330 Lecture 39 Digital ircuits Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)
Review from last lecture Other MOS Logic Families Enhancement Load NMOS Enhancement Load Pseudo-NMOS Depletion Load NMOS
Review from last lecture Static Power Dissipation in Static MOS Family When is Low, I D1 =0 When is High, I D2 =0 Thus, P STATI =0 This is a key property of the static MOS Logic Family and is the major reason Static MOS Logic is so dominant PUN PDN It can be shown that this zero static power dissipation property can be preserved if the PUN is comprised of p-channel devices, the PDN is comprised of n-channel devices and they are never both driven into the conducting states at the same time ompound Gate in MOS Process
Review from last lecture Propagation Delay in Static MOS Family Defn: The Propagation Delay of a gate is defined to be the sum of t HL and t LH, that is, t PROP =t HL +t LH t t +t R R PROP HL LH L PU PD Propagation delay represents a fundamental limit on the speed a gate can be clocked For basic two-inverter cascade in static MOS logic X Y In typical process with minimum-sized and : t t +t 20 psec PROP HL LH
Review from last lecture Propagation Delay in Static MOS Family A F Propagation through k levels of logic t t + t + t + + t HL HLk LH(k-1) HL k-2 XY1 t t + t + t + + t LH LHk HL(k-1) LH k-2 YX1 where x=h and Y=L if k odd and X=L and Y=h if k even t PROP k i1 t PROPk Will return to propagation delay after we discuss device sizing
Digital ircuit Design Hierarchical Design Basic Logic Gates Properties of Logic Families haracterization of MOS Inverter Static MOS Logic Gates Ratio Logic Propagation Delay Simple analytical models Elmore Delay Sizing of Gates Propagation Delay with Multiple Levels of Logic Optimal driving of Large apacitive Loads Power Dissipation in Logic ircuits Other Logic Styles Array Logic Ring Oscillators done partial
Question:????? Why is V Tp V Tn /5 in many processes?????
Device Sizing A k k A 1 A 2 A k 1 2 k A 2 2 A k k A 1 1 A 2 k M A 11 1 A 2 2 A k k A 1 k Strategies? Degrees of Freedom? Will consider the inverter first
Device Sizing L Degrees of Freedom? Strategies?
Device Sizing Since not ratio logic, V H and V L are independent of device sizes for this inverter With L 1 =L 2 =L min, there are 2 degrees of freedom (W 1 and W 2 ) Sizing Strategies Minimum Size L Fixed V TRIP Equal rise-fall times (equal worst-case rise and fall times) Minimum power dissipation Minimum time required to drive a given load Minimum input capacitance
Device Sizing Assume V Tn =0.2, V Tp =-0.2, μ n /μ p =3, L 1 =L 2 =L min Sizing Strategy: minimum sized W n =?, W p =?, V trip =?,t HL =?,t LH =? L R PD μ n OX L1 W V 1 DD V Tn R PU μ p OX L2 W V 2 DD V Tp IN OX WL W L 1 1 2 2
Device Sizing Assume V Tn =0.2, V Tp =-0.2, μ n /μ p =3, L 1 =L 2 =L min Sizing Strategy: minimum sized W n =?, W p =?, V trip =?,t HL =?,t LH =? W 1 =W 2 =W MIN also provides minimum input capacitance t HL =R PD L L t LH =3 R PD L t LH is longer than t HL t PROP =4R PD L V TRIP V Tn V +V DD Tp 1 μ W L μ W L p 2 1 n 1 2 μ W L μ W L p 2 1 n 1 2 1 0.2V V -0.2V DD DD DD V 3. 42V TRIP 1 1 3 DD
Device Sizing Assume V Tn =0.2, V Tp =-0.2, μ n /μ p =3, L 1 =L 2 =L min Sizing strategy: Equal (worst case) rise and fall times W n =?, W p =?, V trip =?,t HL =?,t LH =? L R R PD PU Lmin μ W 0.8V n OX 1 DD Lmin 3μ W 0.8V n OX 2 DD
Device Sizing Assume V Tn =0.2, V Tp =-0.2, μ n /μ p =3, L 1 =L 2 =L min Sizing strategy: Equal (worst case) rise and fall times t R t R LH PU IN = R PU=RPD HL PD IN L Thus L1 L2 u W V -V u W V +V W W n OX 1 DD Tn p OX 2 DD Tp with L 1 =L 2 and V Tp =-V Tn we must have 2 1 n 3 p What about the second degree of freedom? W 1 =W MIN V TRIP =?
Device Sizing Assume V Tn =0.2, V Tp =-0.2, μ n /μ p =3, L 1 =L 2 =L min Sizing strategy: Equal (worst-case) rise and fall times W n =W MIN,W p =3W MIN, V trip =?,t HL =?,t LH =? L μp W L 2 1 V Tn V +V DD Tp μ W L 0.2V +0.8V V V = TRIP μ 2 2 p W L 2 1 1 μ W L n 1 2 L t = t = R n 1 2 DD DD DD min HL LH pd L L μnoxwmin 0.8VDD t PROP = 2 RpdL For a fixed L, how does t prop compare for the minimum-sizing compared to equal rise/fall sizing?
Device Sizing Assume V Tn =0.2, V Tp =-0.2, μ n /μ p =3, L 1 =L 2 =L min Sizing strategy: Fixed V TRIP = /2 W n =?, W p =?, V trip =?,t HL =?,t LH =? L
Device Sizing Assume V Tn =0.2, V Tp =-0.2, μ n /μ p =3, L 1 =L 2 =L min Sizing strategy: Fixed V TRIP = /2 W n =?, W p =?, V trip =?,t HL =?,t LH =? Set V TRIP = /2 L μp W L 2 1.2V V -.2V DD DD DD μ W L V V = TRIP μp W L 2 1 2 1 μ W L n 1 2 n 1 2 DD Solving, obtain W W 2 1 n p W n =W MIN, W p =3W MIN This is the same sizing as was obtained for equal worst-case rise and fall times so t HL =t LH =R pd L This is no coincidence!!! Why? These properties guide the definition of the process parameters provided by the foundry
Device Sizing Assume V Tn =0.2, V Tp =-0.2, μ n /μ p =3, L 1 =L 2 =L min Sizing Strategies Minimum Size Fixed V TRIP L Equal rise-fall times (equal worst-case rise and fall times) Minimum power dissipation Minimum time required to drive a given load Minimum input capacitance
Device Sizing Assume V Tn =0.2, V Tp =-0.2, μ n /μ p =3, L 1 =L 2 =L min Sizing Strategy Summary Minimum Size V TRIP = /2 Equal Rise/Fall Size W n =W p =W min L p =L n =L min W n =W min W p= 3W min W n =W min W p= 3W min L p =L n =L min L p =L n =L min t HL R pd L R pd L R pd L L t LH 3R pd L R pd L R pd L t PROP 4R pd L 2R pd L 2R pd L V trip V TRIP =0.42 V TRIP =0.5 V TRIP =0.5 For a fixed load L, the minimum-sized structure has a higher t PROP but if the load is another inverter, L will also change so the speed improvements become less apparent This will be investigated later
Have sized the reference inverter with W p /W n =μ n /μ p In standard processes, provides V TRIP /2 and t HL t LH Any other sizing strategy could have been used for the reference inverter but this is most convenient Reference Inverter The reference inverter Assume μ n /μ p =3 L n =L p =L MIN W n =W MIN, W p =3W n = IN = 4OXWMIN LMIN def R PD V Tn =.2V L DD MIN LMIN μ W V -V μ W 0.8V n OX MIN DD Tn n OX MIN DD L R PU L MIN μ 3W V +V p OX MIN DD Tp V Tp = -.2V DD R PD
Reference Inverter The reference inverter pair Assume μ n /μ p =3 L n =L p =L MIN W n =W MIN, W p =3W n V OUT L L1 L1= =4 OXWMIN LMIN t = t PROP = t HL +t LH =2RPD def
Reference Inverter The reference inverter pair Assume μ n /μ p =3 L n =L p =L MIN W n =W MIN, W p =3W n V OUT L L L1 Summary: parameters defined from reference inverter: = 4 W L OX MIN MIN MIN R PD = μ n OX W MIN V DD -V Tn t =2R L PD =4 OXWMIN LMIN
The Reference Inverter Reference Inverter R =R PD PU = IN= 4OX WMIN LMIN L VTn.2VDD MIN MIN R PD= μ n OX W MIN V DD -V Tn μ n OX W MIN 0.8V DD t HL = t LH = RPD L Assume μ n /μ p =3 t = t HL + t LH = 2RPD W n =W MIN, W p =3W MIN L n =L p =L MIN In 0.5u proc t =20ps, =4fF, R PD =R PU =2.5K (Note: This OX is somewhat larger than that in the 0.5u ON process)
Propagation Delay How does the propagation delay compare for a minimum-sized strategy to that of an equal rise/fall sizing strategy? V OUT V OUT L L L1 L1 Minimum Sized W 2 =W 1 =W MIN Reference Inverter W 2 =(µ n /µ p )W 1, W 1 =W MIN t PROP = t
Device Sizing The minimum-sized inverter pair Assume μ n /μ p =3 L n =L p =L MIN W n =W MIN, W p =W n = 4OX WMIN LMIN V OUT L1= 0.5 =2 OXWMIN LMIN L L1 R PD VTn.2V L DD MIN LMIN W V V W V 0.8 n OX MIN DD Tn n OX MIN DD 2 t =t +t =R 0.5 3R 0.5 R PROP HL LH PD PD PD t P R O P = t R E F F
Propagation Delay How does the propagation delay compare for a minimum-sized strategy to that of an equal rise/fall sizing strategy? V OUT V OUT L L L1 L1 Minimum Sized W 2 =W 1 =W MIN t PROP = t They are the same! Reference Inverter W 2 =(µ n /µ p )W 1, W 1 =W MIN t PROP = t By how much did t HL improve? Why was there no net change in t PROP? Even though the t LH rise time has been reduced with the equal rise/fall sizing strategy, this was done at the expense of an increase in the total load capacitance that resulted in no net change in propagation delay!
Device Sizing A k k A 1 A 2 A k 1 2 k A 2 2 A k k A 1 1 A 2 k M A 11 1 A 2 2 A k k A 1 k Will consider now the multiple-input gates Will consider both minimum sizing and equal worst-case rise/fall Will assume L (not shown)= Will initially size so gate drive capability is same as that of ref inverter Note: worst-case has been added since fall time in NOR gates or rise time in NAND gates depends upon how many transistors are conducting
Fan In The Fan In (FI) to an input of a gate device, circuit or interconnect that is capacitive is the input capacitance Often this is normalized to some capacitance (typically of ref inverter). FI = alternately FI IN IN
Sizing of Multiple-Input Gates Analysis strategy : Express delays in terms of those of reference inverter Reference Inverter IN= = 4OX WMIN LMIN IN FI = alternately FI =1 R PD LMIN RPU μ W 0.8V n OX MIN DD Assume μ n /μ p =3 W n =W MIN, W p =3W MIN t HL = t LH =RPD t = t HL + t LH = 2RPD L n =L p =L MIN In 0.5u proc t =20ps, =4fF,R PD =2.5K
Multiple Input Gates: 2-input NOR VDD Device Sizing 2-input NAND k-input NOR k-input NAND VDD VDD VDD Ak M2k A1 A2 Ak M21 M22 M2k VOUT A A B A2 A1 M22 M21 Ak M1k B VOUT M11 M12 M1k A1 A2 Ak A2 M2k A1 M1k Equal Worst ase Rise/Fall (and equal to that of ref inverter when driving ) W n =? W p =? Fastest response (t HL or t LH ) =? Worst case response (t PROP, usually of most interest)? Input capacitance (FI) =? Minimum Sized (assume driving a load of ) W n =W min W p =W min Fastest response (t HL or t LH ) =? Slowest response (t HL or t LH ) =? Worst case response (t PROP, usually of most interest)? Input capacitance (FI) =?
Multiple Input Gates: 2-input NOR W n =? W p =? Device Sizing Equal Worst ase Rise/Fall (and equal to that of ref inverter when driving ) (n-channel devices sized same, p-channel devices sized the same) Assume L n =L p =Lmin and driving a load of Input capacitance =? FI=? t PROP =? (worst case) DERIVATIONS A B W n =W MIN W p =6W MIN 7 7 INA = INB=OX WMIN L MIN+6OX WMINL MIN=7OX WMINL MIN= 4OXWMIN L MIN= 4 4 7 FI= 7 or FI= 4 4 t PROP = t (worst case)
Multiple Input Gates: 2-input NOR W n =? W p =? Device Sizing Equal Worst ase Rise/Fall (and equal to that of ref inverter when driving ) (n-channel devices sized same, p-channel devices sized the same) Assume L n =L p =Lmin and driving a load of Input capacitance =? FI=? DERIVATIONS A B t PROP =? (worst case) One degree of freedom was used to satisfy the constraint indicated W n =W MIN W p =6W MIN 7 7 INA = INB=OX WMIN L MIN+6OX WMINL MIN=7OX WMINL MIN= 4OXWMIN L MIN= 4 4 7 FI= 7 or FI= 4 4 Other degree of freedom was used to achieve equal rise and fall times t PROP = t (worst case)
Device Sizing Equal Worst ase Rise/Fall (and equal to that of ref inverter when driving ) Multiple Input Gates: k-input NOR Wn=? DERIVATIONS A k k Wp=? Input capacitance =? A 2 2 FI=? A 1 1 t PROP =? M A 11 1 A 2 2 A k k W n =W MIN W p =3kW MIN 3k+1 3k+1 INx=OXWMIN L MIN+3kOXWMIN L MIN= 3k+1 OXWMIN L MIN= 4OXWMIN L MIN= 4 4 3k+1 FI= 3k+1 or FI= 4 4 t PROP = t
Device Sizing Equal Worst ase Rise/Fall (and equal to that of ref inverter when driving ) Multiple Input Gates: 2-input NAND Wn=? DERIVATIONS Wp=? Input capacitance =? FI=? t PROP =? A B W n =2W MIN W p =3W MIN 5 5 INA= INB=2OXWMINL MIN+3OXWMIN L MIN= 5OXWMINL MIN= 4OXWMINL MIN= 4 4 5 FI= 5 or FI= 4 4 t PROP = t
Device Sizing Equal Worst ase Rise/Fall (and equal to that of ref inverter when driving ) Multiple Input Gates: k-input NAND Wn=? DERIVATIONS A 1 A 2 A k 1 2 k Wp=? A k k Input capacitance =? FI=? A 2 k t PROP =? A 1 k W n =kw MIN W p =3W MIN 3+k 3+k INx=kOXWMINL MIN+3OXW MINL MIN= 3+k OXWMINL MIN= 4OXWMINL MIN= 4 4 3+k FI= 3+k or FI= 4 4 t PROP = t
Device Sizing omparison of NAND and NOR Gates A k k A 1 A 2 A k 1 2 k A 2 2 A k k A 1 1 A 2 k M A 11 1 A 2 2 A k k A 1 k W n =W MIN W n =kw MIN W p =3kW MIN 3k+1 INx= 4 3k+1 FI= 3k+1 or FI= 4 4 t PROP = t W p =3W MIN 3+k INx= 4 3+k FI= 3+k or FI= 4 4 t PROP = t
Assume μ n /μ p =3 L n =L p =L MIN Device Sizing Equal Worse-ase Rise/Fall Device Sizing Strategy -- (same as V TRIP = /2 for worst case delay in typical process considered in example) A k k A 1 A 2 A k 1 2 k A 2 2 A k k A 1 1 A 2 k M A 11 1 A 2 2 A k k A 1 k INV W n =W MIN, W p =3W MIN = IN FI=1 k-input NOR W n =W MIN, W p =3kW MIN 3k+1 IN= 4 3k+1 FI= 4 k-input NAND W n =kw MIN, W p =3W MIN 3+k IN= 4 3+k FI= 4
Multiple Input Gates: 2-input NOR VDD Device Sizing 2-input NAND k-input NOR k-input NAND VDD VDD VDD Ak M2k A1 A2 Ak M21 M22 M2k VOUT A A B A2 A1 M22 M21 Ak M1k B VOUT M11 M12 M1k A1 A2 Ak A2 M2k A1 M1k Equal Worst ase Rise/Fall (and equal to that of ref inverter when driving ) Wn=? Wp=? Fastest response (t HL or t LH ) =? Worst case response (t PROP, usually of most interest)? Input capacitance (FI) =? Minimum Sized (assume driving a load of ) Wn=Wmin Wp=Wmin Fastest response (t HL or t LH ) =? Slowest response (t HL or t LH ) =? Worst case response (t PROP, usually of most interest)? Input capacitance (FI) =?
Device Sizing A k k VDD A 1 A 2 A k 1 2 k A B A 2 A 1 2 1 A B A k k A 2 k M A 11 1 A 2 2 A k k A 1 k Minimum Sized (assume driving a load of ) W n =W min W p =W min Input capacitance (FI) =? IN = OXWn L n+oxwp L p = OXWminL min + OXWminL min = 2ox WminL min= 2 1 FI = 2 Fastest response (t HL or t HL ) =? Slowest response (t HL or t HL ) =? Worst case response (t PROP, usually of most interest)?
Device Sizing minimum size driving A k k A 1 A 2 A k 1 2 k A 2 2 A k k A 1 1 A 2 k M A 11 1 A 2 2 A k k A 1 k INV t PROP? t 0.5t PROP tprop FI = R R R 2t 2 3 t 2 PU PD PD R PROP k-input NOR t PROP? t 0.5t PD t PROP R 3k t 2 3k 1 t 2 FI = PD 2 R PU 3kR PD k-input NAND t t PROP? PROP t 3 k t t 2 2 PROP FI = 3 k t 2 2 R 3R R 3R PD PD PU PD
End of Lecture 39