Power Distribution Network Design for High-Speed Printed Circuit Boards Jun Fan NCR Corporation 1
Outline Overview of PDN design in multi-layer PCBs Interconnect Inductance Individual Capacitor Values Capacitor ocation Power/Ground Plane Pair Summary 2
PDN in a Multi-ayer PCB DC/DC converter (Power source) SMT capacitors GND GND GND IC load electrolytic capacitor GND IC driver GND GND switch V DC P-MOS N-MOS IC driver R S PCB trace Z 0, v p IC load C GND 3
Device Switching Current drawn from power charge IC load IC driver R S Z 0, v p shoot-through current GND logic 0 1 discharge IC load Shootthrough current only Shoot-through + load charging current IC driver R S Z 0, v p 0 V shoot-through current GND logic 1 0 J. Knighten, B. Archambeault, J. Fan, et. al., PDN Design Strategies: IV. Sources of PDN Noise, IEEE EMC Society Newsletter, Winter 2007, Issue No. 212, pp. 66-76. 4
Current Supply and Power Bus Noise I am Mr. Charge! IC 2 IC driver EMI GND GND V noise V N d I/O line or cable EMI 5
PDN Design Objectives 1. Ensure charge supply for logic transitions Enough capacitance to store charge Enough charge readily available for short transitions 2. Minimize noise voltage distribution on the /GND plane pair ow power bus impedance over frequency Noise decoupling GND Noise isolation EMI shoot-through current IC 2 GND V noise IC driver GND V N IC driver d R S charge Z 0, v p logic 0 1 IC load EMI I/O line or cable 6
PDN Design Issues in PCB Capacitor interconnects; Individual capacitor values and packaging forms; Number of capacitors needed; Capacitor placement; PCB stack-up; Power/ground plane pair geometry; Segmentation and isolation 7
PDN Charging/Discharging Hierarchy Speed of charge delivery Connectors and wiring Capacitor leads Interconnect Pin interconnect V DC bulk C bulk via C SMT C plane s BGA packaged IC pins VRM (DC/DC converter) SMT capacitors Ultimate Charge Source 100 s uf 0.01-100 s uf Electrolytic capacitors pf s-100 nf /GND plane Amount of charge available for delivery The planes can be regarded as a C only @ low frequencies 8
PDN Impedance Profile 20 ocal decoupling 10 0Bulk cap Z 21 [dbω] -10-20 -30-40 Global decoupling Power plane distributed behavior -50 10-4 10-2 10 0 Frequency [GHz] 9
Outline Interconnect Inductance - shall be minimized in any situation 10
Effect of Inductance Inductance impedes the flow of current (charge) to the load that will charge it to achieve a logic 1 GND decoupling capacitor C IC load Inductance associated with the capacitor: package parasitics, bonding pads, board traces, and vias R C Z = R f res + = jω 2π 1 + C 1 jω C C R v(0)=v S t=0 i(t) i( t 0) = V S C sin( t C ) 11
Minimizing Interconnect Inductance SMT Decoupling Capacitor ES oop 2 above oop 1 via SMT Capacitor Via The Good Capacitor Pads The Better The Best Really Ugly The Ugly The Bad 12
Outline Individual Capacitor Values - multiple values or maximum value? May not matter f res = 2π 1 C 13
Two Common SMT Decoupling Strategies Use an array of capacitor values: This may be the best known approach and is very popular in the signal integrity design community (SI-IST). Rationale: to maintain a flat impedance profile below a target impedance over a wide frequency range Typically a logarithmically spaced (10, 22, 47, 100, 220, 470nF, etc.) array of 3 values per decade. Use the largest capacitor value in the package size This is less well-known, but a popular approach in the EMI design community Rationale: to keep impedance as low as possible, less emphasis on a target impedance and a flat profile 14
Different Approaches : Comparison Approach A : values of decoupling capacitors logarithmically spaced, i.e. 3 values per decade : 10, 22, 47, 100, etc. Approach B : largest values of decoupling available in two package sizes, i.e., 0603 and 0402 Approach B1 : largest values of decoupling available in one package size, i.e., 0402. Target Impedance decoupling capacitors -20 db/dec +20 db/dec distributed behavior Both approaches can meet the design specs relative to the target impedance 15
Outline Capacitor ocation - could be important due to PCB geometry 16
Background decoupling caps GND 1.5V 3.3V Does capacitor location matter? How close is close? What if capacitors can t be placed close enough to the IC pwr/gnd pins? Is it worth sacrificing routing or using costly new technology in order to get capacitors closer? Need a way to facilitate engineering judgment 17
ocation Affects Interconnect Inductance S G P CAP i(t) above CAP below IC above Interconnect inductance is reduced when the cap is moved closer to the IC The capacitor becomes more effective S R R t=0 C C v(0)=v S i(t) Z = R f res + = jω 2π + 1 1 jω C C i( t 0) = V S C sin( t C ) 18
Equivalent Circuit Model D k C 2 I 1 Parallel Plate + + Geometry 1 = + ES 3 3 V 1 Port 1 Port 2 V 2 I N C dec B A J. Fan, et. al., ``Quantifying SMT decoupling capacitor placement in DC power bus design for multi-layer PCBs, IEEE Transactions on Electromagnetic Compatibility, Vol. 43, No. 4, pp. 588-599, November 2001. 19
ocal Decoupling Effect Frequency-Domain Equivalent circuit at high frequencies D C M 1 1 k M I N B A 2 + M 2 3 3 = 3 + ES 1 0 C ωc dec dec dec I 1 I 1 Parallel Plate + + Geometry V 1 Port 1 Port 2 V 2 Z Z Z 21 = = V I V ' 2 21 I1 = V 2 N ' 1 11 I1 Z21 I1 jω( = = Z I jω( 21 2 + + 3 M ) ) + Z (1 k) + N 2 3 11 1+ 3 2 3 2 20
ocal Decoupling Effect Frequency-Domain IC GND GND Δf c ΔZ ΔZ ΔZ Increasing series resonant frequency of decoupling capacitor Reducing impedance uniformly in a frequency-independent manner (approximately) for frequencies higher than the series resonant frequency 21
ocal Decoupling Effect Time-Domain Equivalent circuit at early time (t 0) 1 -M M i 1 (t) i 2 (t) 2 + 3 -M i N (t) M di t) dt di ( t) ) dt ( 1 2 ( 2 + 3 M 1 M I N 2 + 3 M C dec M I 1 Parallel Plate + + Geometry V 1 Port 1 Port 2 V 2 2 + 3 M i1 ( t) = in ( t) + 2 (1 k) + 1+ 3 2 3 3 2 i N ( t) 22
ocal Decoupling Effect Time Domain IC GND GND Port 2 voltage (mv) Reducing initial noise voltage generated in the power bus due to logic transitions. Time (ns) 23
ocal Decoupling Effect Charge Delivery 3.4 3.4 3.2 3.2 3 3 Vplane [V] 2.8 2.6 2.4 2.2 50 mils 400 mils 5000 mils No decap Vplane [V] 2.8 2.6 2.4 2.2 50 mils 400 mils 5000 mils No decap 2 0 1 2 3 4 5 6 time [ns] 2 0 1 2 3 4 5 6 time [ns] 35 mil thick 10 mil thick 24
Estimating ocal Decoupling Effect Closed-form expressions derived from the radial transmission-line theory : Δ Z 21 ( db) 20log 10 (1 k) + 3 1+ 2 3 2 μ0d R equiv 2 = ln 0.75 2π r R equiv ln 0.75 s + r k R equiv ln 0.75 r For a rectangular power bus, accounting for fringing effect H d PWR/GND plane pair spacing r via radius Requiv equivalent radius of power bus s spacing between two vias R equiv a+ b 4 assumption: vias are located close to the center of the planes J. Fan, et. al., Estimating the noise mitigation effect of local decoupling in printed circuit boards, IEEE Transactions on Advanced Packaging, Vol. 25, No. 2, pp. 154-165, May 2002. 25
Estimating ocal Decoupling Effect cap via 2( ) 3 = via + trace where = M and trace = t Mt via ps ps 2 2 μ 0 hs hs l l 2 2 2 2 2 2 2 M ps = hs ln + 1+ + 1 + 2π l l hs h ( w 2 p + l ) w + p + l s 3 2 2 2 Validated 2 2 l+ w + p + l 2 2 μ 0 hs h + l( w p ) ln s r r with ps = hs ln + 1+ + 1 + + l w + p + l 2π r r hs hs CEMPIE 2 2 2 2 2 + ( w 2 p ) w + p 3 2 2 2 2 2 l+ w + l 2 w+ w + l 7 2 2 2 7 10 2 w w p l 2 10 3wlln + 3l wln + + + Mt = + l wln t = w l 2 2 w 2 2 2 3w w+ w + p + l 2 2 3/2 3 3 ( w l ) l w + + + 1 wl 4wpl tan 2 2 2 p w + p + l 2 2 2 2 2 + ( l 2 p ) l + p 3 2 2 3 2 l+ l + p 4 p + plln + 2 2 + l l + p 3 l: separation between two via; h s : height of the capacitor from the nearest power or ground plane ; w: width of the trace connecting two vias, or width of the capacitor package if no trace ; r: radius of the via ; and p = 2h s. trace pad 2 2 2 C. Wang, et. al., An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances, IEEE Transactions on Advanced Packaging, Vol. 29, No. 2, pp. 320-334, May 2006. 26
Design Implications Dos Don ts CAP IC GND PWR IC GND PWR CAP J. Knighten, B. Archambeault, J. Fan, et. al., PDN Design Strategies: II. Ceramic SMT Decoupling Capacitors Does ocation Matter?, IEEE EMC Society Newsletter, Issue No. 207, Winter 2006, pp. 56-67. 27
Design Implications The ratio of 3 / 2 A good indicator of the ability of a power bus to support local decoupling The lower, the better Can be greatly increased by even very short trace length from via to pad PWR/GND pair thickness 3 ' (nh) 3 / 2 with no trace 3 / 2 w/extra 100 mil trace length 3 / 2 w/extra 200 mil trace length 3 / 2 w/extra 300 mil trace length 10 mils 1.66 6.75 9.13 11.50 13.88 35 mils 0.92 1.29 1.98 2.67 3.36 Tabulated values for Centered power bus in a 62-mil PCB stack-up 10 mil via diameter 0603 SMT capacitor package trace cap pad via 28
Design Implications The placement of de-cap (obverse or reverse), can be highly dependent on the position of power bus in PCB stack-up. Always EAST above-plane inductance! SMT de-cap Placement 3 ' (nh) 3 / 2 Obverse 0.45 2.96875 Reverse 2.56 9.5625 29
Outline Power/Ground Plane Pair - thin is always better 30
Impedance of the Power/Ground Plane Pair Based on the cavity method: P i P j ow frequency capacitive term ocation Port Dimensions Z ij ( ω) = 1 jωc plane + jωμd M N m= 0n= 0 n m 2 2 ( k k ) nm 2 2 ε ε f ab m= n 0 ( x, x, y, y ) p(,,, ) i j i j xi xj yi yj + jω HM ij Resonant frequency contributions Higher order mode exists only when i = j Z ij (ω) d C. Wang, et. al., An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances, IEEE Transactions on Advanced Packaging, Vol. 29, No. 2, pp. 320-334, May 2006. 31
Power Bus Thickness Effects on Decoupling b = 10 in Port 2(7 in, 4 in) Port 1 (3 in, 2 in) d 40 30 20 d = 1 mil d = 5 mils d = 10 mils d = 40 mils a = 12 in 40 20 d = 1 mil d = 5 mils d = 10 mils d = 40 mils 10 0 Z 11 (dbω) 0-10 Z 21 (dbω) -20-20 -40-30 -40-60 -50 1 10 100 1000 5000 Frequency (MHz) -80 1 10 100 1000 5000 Frequency (MHz) 32 Frequency domain: impedance
Power Bus Thickness Effects on Decoupling port 1 current Current (A) 1 0.8 0.6 0.4 0.2 b = 10 in Port 2(7 in, 4 in) Port 1 (3 in, 2 in) d 0 0 0.2 0.4 0.6 0.8 1 Time (ns) a = 12 in Port 1 voltage (mv) 4000 3000 2000 1000 0-1000 -2000-3000 d = 1 mil d = 5 mils d = 10 mils d = 40 mils Port 2 voltage (mv) 500 400 300 200 100 0 d = 1 mil d = 5 mils d = 10 mils d = 40 mils -4000 0 0.5 1 1.5 2 2.5 3 Time (ns) Time domain: port voltages -100 0 0.5 1 1.5 2 2.5 3 Time (ns) 33
Power Bus Thickness Effects on Decoupling 3.4 3.2 3 3.4 3.2 3 Vplane [V] 2.8 2.6 3 0.5nH 2.4 3 1nH 3 2nH 2.2 3 3nH No decap 2 0 1 2 3 4 5 6 time [ns] Vplane [V] 2.8 2.6 2.4 2.2 3 0.5nH 3 1nH 3 2nH 3 3nH No decap 2 0 1 2 3 4 5 6 time [ns] 35 mil thick 10 mil thick 34
Effect of Typical aminates on Decoupling Dk oss Tangent Thickness, d 4.4 0.02 4, 10, 35 mils Comment better quality fiberglass/ epoxy resin material 4 0.02 2 mils patented thin FR4 core, widely used. 16 0.006 16 microns (0.63 mils) ultra-thin material commercially available 20 0.015 0.2 mils ultra-thin material from [7, 8]. Z 11 (dbω) 40 30 20 10 0-10 -20-30 -40-50 ε r = 4.4, tanδ = 0.02, d = 4 mils ε r = 4.4, tanδ = 0.02, d = 10 mils ε r = 4.4, tanδ = 0.02, d = 35 mils ε r = 4, tanδ = 0.018, d = 2 mils ε r = 16, tanδ = 0.006, d = 0.63 mils ε r = 20, tanδ = 0.015, d = 0.2 mils -60 10 100 1000 5000 Frequency (MHz) Embedded capacitance (thin laminate) has superior electrical performance 35
Summary Interconnect inductance shall be minimized in any situation: inductance limits the effectiveness of decoupling Individual capacitor values may not matter: using an array of capacitor values or the largest value in a package size meets design specifications Capacitor location could be important due to PCB geometry: thin power bus structures (< 10 mils) usually result in a larger 3 / 2 value; thus capacitor location is relatively unimportant. Thick power bus structures usually result in a smaller ( 3 / 2 ) value, and capacitor placement can be an important design factor Thin power/ground plane pair is always better: low impedance and high charge availability 36