: CMOS Process and Device Simulation Virtual Device Simulation Virtual Process Integration Dr Zhou Xing Office: S1-B1c-95 Phone: 6790-4532 Email: exzhou@ntu.edu.sg Web: http://www.ntu.edu.sg/home/exzhou/teaching// X. ZHOU 1 2018
Technology Scaling Gordon Moore (2003): No exponential is forever. But we can delay forever. X. ZHOU 2 2018
Moore s Law: Essence of Technology Scaling 2002 1018 $200B I estimate that the number of printed characters produced every year is between 10 to the 17th and 10 to the 18th. That s all the newspapers, books, magazines, Xerox copies, computer print outs that you throw away, everything. That s the same order of magnitude as the number of transistors that the industry sells. (Of course we print a lot of them we don t sell). Those are where those little red dots are when we get $2 10 7 = 20 through sorting them. G. E. Moore, ISSCC, Feb. 2003 What really dictates technology scaling is the Economics (as governed by Moore s law), and the essence of which is yield, which is mainly determined by variability/reliability. X. ZHOU 3 2018
CMOS Technology Generations X. ZHOU 4 2018
Overall Picture: Chip Design and Wafer Fabrication Design Manufacturing Characterization Simulation Verification Specification EDA Design System Design ECAD Verification Logic synthesis CM SPICE Logic Design Netlist extraction Verification Characterization Parameter extraction Frontend Circuit Design Layout extraction SPICE I-V, C-V Backend Layout Design CM RWF Manufacturing Mask VWF = + Characterization Wafer Recipe Parameter extraction Calibration SIMS, SRP Simulation Process Simulation TCAD LPE DRC I-V C-V Verification Structure Doping profile I-V, C-V Device Simulation Virtual wafer X. ZHOU 5 2018
Multi-Level Representation Level Representation Function Graphical y System Functional y = f(x) x Logic Boolean x y 0 1 1 0 Circuit Transistor [I] = [Y][V] Device Analytical Ids = f(vgs, Vds, Vbs, W, L, T) Id Vg Vd 2 = / Technology Device d + J dt = G U J = qµ n + qd n X. ZHOU 6 2018
Layout + Process = Chip X. ZHOU 7 2018
TCAD Physical Simulation X. ZHOU 8 2018
Target Variable Relationship Level Variables Targets Circuit Spice: Model parameters,... Geometrical: Channel length, width,... Electrical: Supply voltage, substrate bias,... Digital: Analog: Delay, rise/fall time, drivability, off-state current, noise margin,... Voltage gain, cutoff frequency, slew rate, gain-bandwidth,... Device Structural: Oxide thickness, junction depth, sheet resistance,... Doping: Peak/surface concentration,... Electrical: Threshold, transconductance, subthreshold swing, saturation current, punchthrough current, junction capacitance, lifetime,... Electrical: Supply voltage, substrate bias,... Physical: Potential, field, charge, current, carriers, velocity,... Process Oxidation: Temperature, time, ambient,... Layer: Oxide thickness, junction depth, sheet resistance,... Implantation: Dose, energy, tilt, damage,... Diffusion: Defect, stress, OED, TED,... Profile: Peak/surface concentration, projected range/straggle,... X. ZHOU 9 2018
Three Ways of Obtaining Device Characteristics X. ZHOU 10 2018
Basic Ingredients in Device Simulation X. ZHOU 11 2018
Discretization and Solution Methods X. ZHOU 12 2018
What Is a Model, and Modeling? John von Neumann The sciences do not try to explain, they hardly even try to interpret, they mainly make models. By a model is meant a mathematical construct which, with the addition of certain verbal interpretations, describes observed phenomena. The justification of such a mathematical construct is solely and precisely that it is expected to work. A model is a mental image of reality X. ZHOU 13 2018
Ideal vs Real MOSFET X. ZHOU 14 2018
Long-Channel or Short-Channel? Short-channel effect (SCE) technology dependent (depends on where the device sits on the V t L curve, not the actual dimension) Challenge in modeling geometry dependence in the SCE regime Threshold Voltage, V t SCE SCE long short L 1 > L 2 0.15 0.2 0.25 m 0.13 m L 1 L L 2 Gate Length, L X. ZHOU 15 2018
Ideal MOS Capacitor and Operation Ideal MOS: No work function difference between metal and Si, and no charges in SiO 2 ; thus, all bands are flat (V ox =0, s = 0) at zero gate-bulk bias (V gb = 0). In an MOS capacitor, since there s no (DC) current, the system is always at thermal equilibrium, even with bias. Three regions of operation Accumulation (V gb < 0; s < 0) Depletion (0 < V gb < V t ; 0 < s < 2 F ) Strong-inversion (V gb > V t ; s > 2 F ) Basic governing equations Voltage balance (KVL): V gb = V ox + s Charge balance (neutrality): Q g = Q sc Gauss law: ox ox = Q g ; Si s = Q sc q( pn N N ) flatband / q NA D A accumulation / q ps / q ns NA depletion V ox Vb 0 0, 0 s V ox (0) s B ( ) E qv 0 i b (a) Ideal MOS (p-bulk) at zero bias (flatband); (b) accumulation at V gb ; (c) depletion at +V gb ; (d) strong-inversion at large +V gb. inversion X. ZHOU 16 2018
Real MOS: Gate Bulk Work Function Difference In real MOS, metal work function and Si work function (depends on doping) won t be the same, given by MS M S ( EFm EF ) q After connecting the metal gate to the Si bulk with a wire (V gb = 0), the two Fermi levels will line up. Band bending occurs such that the total potential drop in MOS will balance the initial Fermi level difference: Vox s 0 MS or Vox s MS Vgb This is similar to pn junction built-in voltage (V bi ) except MOS is always at equilibrium, so np=n i2 everywhere; while for pn junction, npn i2 in the depletion region (drift = diffusion). Before contact: After contact: at thermal equilibrium (V gb = 0) Note: Work function, affinity, and band gap are all material properties (function of temperature) and do not change with applied bias. X. ZHOU 17 2018
Real MOS: Mobile/Fixed/Trapped Charges in the Oxide In real MOS, there are various charges distributed in the oxide during wafer processing, including: mobile ions (Q m ), fixed oxide charge (Q f ), and oxide trapped charge (Q ot ), as well as interface trapped charge (Q it ). To simplify analysis, we assume all these charges can be represented by an equivalent sheet charge Q ox (per unit area) at the SiO 2 /Si interface (ignoring Q it ): Qox Qm Qf Qot From charge balance, we have Qg Qox Qsc From potential balance, we have Vgb Vox s MS From Gauss law, we have ox ox Qg, with ox Vox Tox and C Define Flatband voltage: V Q C Q Q Q C X. ZHOU 18 2018 0 Q g Q ox Q sc Qox Qm Qf Qot ox ox ox FB MS ox ox MS m f ot ox ox ox Vgb Qox Qsc Cox s MS VFB Qsc Cox s Qox Qsc Cox So, non-idealities due to work function difference and oxide charge can be absorbed into flatband, if we define Vgf Vgb VFB Vox s. When Vgf 0( Vgb VFB ), we havevox 0, s 0, i.e., bands are flat. This is similar to ideal MOS (V FB = 0): when V 0, we have V 0, 0. gb T V T Q ox ox ox T Q ox g ox ox g C ox s
Field and Potential Distribution in Depletion Region Full-depletion approximation In depletion region, both electrons and holes can be ignored compared to N A, so space charge (per unit area) is: Q qn X Poisson equation is given by 2 2 2 d d x d dx qn 2 x 2 2 x x 0 xd x 0 2 2 Si A Si d qn A d dx So, surface field: From Gauss law (at Si surface): Si sc A d dx 0 2qN x 2 d x A Si Q s x A s Si qn Si s sc 2qN Q qn X s A s Si sc Si A d Si Potential distribution x From 2 nd integral of Poisson: 0 1 d 2qN dx x X d A Si d dx 1 d 2qNA Sidx So, depletion width (function of V gb ): X xqn 2 X x 2 A Si d 2 qn d Si s A 2 qn 2 X s A Si d x 0 Area = s Q sc o V g Q b ov b = 0 Si s X. ZHOU 19 2018
Charge-Sheet Approximation and Threshold Voltage Charge-sheet approximation (CSA) in strong inversion In strong inversion, electrons (n) are comparable to N A, so the space charge (per unit area) Q sc includes both inversion charge Q i = qn*x i (in a layer of x i ) and depletion charge Q b = qn A *X d, and they are in principle not separable. In the charge-sheet approximation, we assume Q i is a sheet of charge with negligible thickness (x i 0); and under full-depletion approximation, in the depletion region of thickness X d, there is no free carriers. Then: Qsc Qi Qb Threshold voltage definition and maximum depletion width We define the threshold voltage (V t ) to be the gate-to-bulk voltage (V gb ) at which surface potential is equal to twice of the bulk Fermi potential (2 F ). For V gb > V t, we assume surface potential is pinned to 2 F, and depletion layer reaches its maximum value X dm. This is due to sufficient electrons to screen the gate electric field after the onset of strong inversion. Recall potential balance: Vgf Vgb VFB Vox s Qsc Cox s and 2 V V V Q 2 C 2 V 2 2 t gb 2 FB b F ox F FB F F s F Q sc = + X. ZHOU 20 2018 CSA Q i o Q Q qn X q N sc b A d Si A s where q N C is the body factor. 2 Si A ox V g Q b ov b = 0 For V gb V t, maximum depletion width: X dm 4 Si F qn A
MOSFET Structure and Naming Four terminals Gate: control current flow in an inversion channel Source: supply carriers Drain: collect carriers Bulk: silicon body Intrinsic device parameters W/L: channel width/length T ox : oxide thickness N A : substrate (bulk/body) doping 2D problem two 1D solutions Electrostatics by vertical field (~V gb /T ox ) Current transport by lateral field (~V ds /L) Key: Inversion-carrier imref split V cb (y) = [E Fn (y) E F ]/q (E Fp = E F ) Cross-section of an NMOS with p- type Si substrate. MOSFET source and drain are identical and distinguished by applied bias. I ds = f(v gs, V ds, V bs ) X. ZHOU 21 2018
MOSFET in Equilibrium and Regions of Operation G B S G D MOSFET & equilibrium energy band. y V gs : Vertical field controls the conductance (carriers) V ds : Lateral field controls current transport (flow) Cut-off: V gs < V t (no free carriers no current*) Turn-on: V gs V t (V ds = 0: I ds = 0; V ds > 0: I ds > 0) Linear: V gs V t & V gd V t (full inversion channel) Saturation: V gs V t & V gd <V t (drain pinched-off ) (*There is still small diffusion current, like a thick-base [long-channel] BJT.) V dsat = V gs V t (a) Linear (triode), (b) pinch-off, (c) saturation. X. ZHOU 22 2018
MOSFET Operation: Due to Inversion Carrier Imref-Split MOSFET at equilibrium (V ds = 0): no current flow even if channel is created at V gs = V t ( s = 2 F ) When V sb 0 (V sb > 0 in NMOS), electron imref will split from hole imref with qv sb = E Fn E Fp, so s = 2 F + V sb. V cb y = 0 y = L E Fp = E F When V ds 0 (V ds > 0 in NMOS), holes are still at quasi-equilibrium (since no source nor drain ), so we can assume E Fp = E F. However, electron imref will change from V sb at source end to V db = V sb + V ds at drain end relative to E F, and varying along the channel as V cb (y) [ c stands for channel ]. It is the gradient of V cb (y) that drives electrons drifting/diffusing from source to drain along y. X. ZHOU 23 2018 = qv db Key to understanding MOSFET operation: Band diagram in the x direction along a cutline at (b) source-end (y = 0) and (c) drain-end (y = L).
Regions of Operation: Output Characteristics Cross-sectional view of a long-channel NMOS in strong inversion. Compare with BJT (CE): BJT: MOS: E C S D Saturation Linear Active Saturation I c I b I d V gs V t Three regions of operation (excluding break-down): Cut-off: V gs < V t ; Linear V gd > V t (or V ds < V gs V t ); Saturation: V gd < V t (or V ds > V gs V t = V dsat ). (Note: V dsat = V gs V t ; V gd = V gs V ds ) X. ZHOU 24 2018
Regions of Operation: Transfer Characteristics Quadratic V t Exponential V t Linear log Low gate source bias (V gs < V t ): No inversion layer; diffusion dominant. MOS behaves like a wide-base (long-channel) BJT with I ds exp[(v gs V t )/v th ]. High drain source bias (V ds > V dsat ): Drain side pinched-off. MOS behaves like a current source. Low drain source bias (V ds < V dsat ): Full channel. MOS behaves like a voltage-controlled resistor. X. ZHOU 25 2018
MOSFET Source-Referenced Threshold Voltage MOSFET threshold voltage definition (source-referenced) We define the threshold voltage (V t ) to be the gate-to-source voltage (V gs ) at which source-end surface potential is equal to twice of the bulk Fermi potential (2 F ) with reference to source bulk voltage V sb. Potential balance Gauss law V V V V V V V Q C Q C Q C gs sb FB gb FB gf ox s g ox s sc ox s b ox s Vgs VFB VsbQb Cox s 2 2 V V V V Q C V V Q V C V t gs 2 V FB sb b s ox s 2 V FB sb b s F sb ox F sb s F sb s F sb V V V 2 V 2 t gs 2 V FB F sb F s F sb 0 2 F sb 2 F Charge balance 2 qn X C q N C A d ox s Si A s ox s Full-depletion approximation Body effect Threshold-voltage shift due to non-zero V sb V V V t sb t V where q N C is the body factor. 2 Si A ox Charge-sheet approximation Vt0 Vt V 2 2 0 FB F F V sb X 2 qn d Si s A For NMOS, V sb > 0 so that source/drainto bulk diodes always reverse biased. X. ZHOU 26 2018
Current Voltage in Linear (Triode) Region MOSFET analysis major assumptions (NMOS as example) GCA Gradual Channel Approximation: de y /dy << de x /dx Unipolar hole current can be neglected (E Fp E F ) in normal region (excluding breakdown) Built-in voltages for the source/drain diodes can be ignored (long channel) No recombination/generation and constant mobility Current flows in the y direction only First-order equation derivation Charge-sheet approximation (CSA) Pinned surface potential at strong inversion (2 F ) Constant bulk charge along channel Drift-current only in linear region y 0 V y 2 V V y s s cb F sb V V Q C V V Q i ox gb FB C V V ox gb FB C ox Vgs Vt V, s ds 0 n, drift 0 n s y 0 ds V V V Q C Q Q C gb FB ox s g ox s b i ox s I y W J y dx W qn x y d dy dx WnQiydV dy Qi y qnx, ydx 0 W V ds I ds n Q 0 i y dv L W 1 I C V V V V L 2 b 2 F Vs b V y 2F Vs b ds n ox gs t ds ds V V 2 V 2 t Q C 2 V FB F sb F L L V V dy s db ds ~ d dv dv 0 0 s V cb 0 s b ox F sb Linear law (I ds is a linear function of V gs ) [ Sah equation ]: sb V V, V V gs t gd t X. ZHOU 27 2018
Current Voltage in Saturation (Pinch-off) Region The peak of the linear current is reached when di dv C W L V V V 0 ds ds n ox gs t ds For Vds Vgs Vt Vdsat, GCA is not valid. Also, QiV Vdsat0, channel is said to be pinched-off. V dsat is called saturation or pinch-off voltage, and the corresponding current is the saturation current: Square law (I ds is a quadratic function of V gs ): 1 W I C V V 2 I 2 L ds n ox gs t dsat V V gs gd Vt, V t The pinch-off picture (Q i = 0 assumption) is not physically correct since it requires the field to be infinite Eyy J ds y nqiy at pinch-off and carriers travel with infinite drift velocity. A more correct picture is that Q i at pinch-off is very small but finite, with carriers drift under the large field in the pinch-off region at a saturated velocity. V t =1V Linear (Triode) Saturation Cut-off MOSFET first-order piece-wise linear/square-law model. X. ZHOU 28 2018
Velocity Saturation and Saturation Current Velocity field relation piecewise model ne E E v 1 EEsat vsat E E Saturation field E 2v vsat Esat 1 E E Lateral-field mobility sat sat n sat sat ds n 1 I y WQ y i E EE 1 dv dv Ids y1 WQi yn Esat dy dy Q C V V 2 V V Q i ox gb FB F sb b v sat v Saturation current n E sat Bulk-Si property ~10 7 cm/s sat sat n Idsat WvsatQsat WvsatCox Vgs Vt AV b dsat Q b Cox 2F Vsb V n eff EsatLeff Vgs Vt 1 1 Vds EsatL A 1 eff (1)(V dsat ) = (2): Vdsat b 2 2 F Vsb Vgs Vt AbEsatLeff sat (Amplitude) E (2) W 1 I C V V AV V L 2 ds eff ox gs t b ds ds (1) V 2 gs Vt Idsat WvsatCox V gs V t A b E sat L eff L 0 V gs V Linear! t X. ZHOU 29 2018
Charge-Sharing Model: V t Roll-Off Charge-sharing model Without charge-sharing V V Q C 2 t FB bm ox F With charge-charing V V Q C 2 ' ' t FB ox F bm ' Vt Vt Vt 1 C Q C L bm qn AX dm X dm 4SiF Tox T L L 2X V t ' Q Q Q X bm bm bm dm ox ox eff ox ox eff ox g j V t C L L 2 X eff g j ox ox Tox Qbm qnaxdm X 2 2 V qn dm Si F sb A Short-channel effect (SCE): V t roll-off (L eff ) L g T ox 0 X j n + X. ZHOU 30 2018 ~ 0.7 V s o Total bulk charge: X d Bulk charge per unit area: W o L g Q' b Q b o V g V b L eff Simple Triangle Model n + V d Charge shared by the gate/drain o Q qn W L X X ' 2 B A eff d d Q qn W L X B A eff d ' ' Qb QB X 1 Q Q L b B eff d N sd
DIBL: Drain-Induced Barrier Lowering V s o T ox 0 X j n + X d W o L g Q b Q' b V g L eff V d0 V dd o n + N sd log(i DS ) V DS = V dd V DS = V d0 I crit V t o V b 2 2 X V V qn dm cb Si F cb A V t0 V DIBL V t0 V t0 (L g = ) V t0 (L g ) V DIBL V t0 (L g ) V ts (L g ) s L g V ts V t0 V GS s (V) L = 0.18 m 0.4 m 0.7 m Surface Potential 2 m (V gs = 0.5 V, V bs = 0) Solid lines: V ds = 0.05 V Dotted lines: V ds = 2.5 V E (ev) X. ZHOU 31 2018
Summary of Important Equations Threshold voltage Long-channel (1D theoretical model) V V V 2 V 2 t gs 2 V FB F sb F Short-channel (triangle charge-sharing model) 4 SiF Tox Vt 0Lg Vt 0_ long Vt 0 Vt 0_ long L 2X Drain current Linear W 1 I 0C V V AV V L 2 ds ox gs t b ds ds Saturation s F sb V 2 gs Vt Idsat WvsatCox V gs V t A b E sat L eff ox g j kt N A F ln q ni 2qSiNA Cox V Q C E 2 Q C FB MS ox ox M g F ox ox Subthreshold 2 W Ids 0Cdvth e 1 e L V gs V t nv th ds th V v C Short-channel DIBL T ox ox ox 0 V L V L V L DIBL g t g ts g 2 Vgs Vt Leff ; long-channel: quadratic Vgs Vt Leff 0; short-channel: linear n1cd Cox Cd Si Xdm Cox 2 2 V F sb X. ZHOU 32 2018
Gate-Controlled Drift ( ON ) and Diffusion ( OFF ) E i = qv c (y) (ev) 0.0-0.5-1.0 n + n + S Diffusion Drift (V gs = 0.2 V) V g V gs = 0.4 V 0 V 1 V 2 V "Pinch-off" D -1.5 V s V s ' V s ' V d ' V d ' V d x = 0 x = L 0 20 40 60 80 100 X. ZHOU 33 2018
Threshold Voltage Definition (I crit @V t0 ) Drain Current, I ds (A) 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 L = 0.2 m W = 20 m I crit I offs I off0 S ts I ds V ts S t0 V t0 Solid: V ds = 0.1 V (V bs = 0) Dotted: V ds = 2.5 V (V bs = 0) Dashed: V ds = 0.1 V (V bs = 2.7 V) V t0 (V bb ) 0.0 0.5 1.0 1.5 2.0 2.5 I ds g m Gate Voltage, V gs (V) Drain Current, I ds (ma) I on I crit g ms 1.5 1.0 0.5 0.0 Transconductance, g m (ms) X. ZHOU 34 2018