EE141- Spring 2004 Digital Integrated Circuits Lecture 30 PERSPECTIVES 1 Administrative Stuff Homework 10 posted just for practice. No need to turn in (hw 9 due today). Normal office hours next week. HKN review today. Your feedback is important! Final covers all material covered in class. Precise overview to be posted on web-site. Review session the day before the final (TBA) 2 1
Project 2 some exciting results Most projects focused on non-restoring combined with mostly pass-transistor based implementation Some great alternatives Look-up tables Carry-select combined with concurrency Exploit the specs Grades: Mean:16.88 Median: 16.75 Stddev: 2.01 Max: 20 3 Memory 4 2
Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM 5 6-transistor CMOS SRAM Cell WL V DD M 2 M 4 Q M Q M 5 6 M 1 M 3 BL BL 6 3
Resistance-load SRAM Cell V DD WL R L R L M 3 Q Q M 4 BL M 1 M 2 BL Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem 7 3-Transistor DRAM Cell BL1 BL2 WWL RWL WWL M 3 RWL M 1 X M 2 X V DD 2 V T C S BL 1 V DD BL 2 V DD 2 V T DV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn 8 4
3T-DRAM Layout BL2 BL1 GND RWL M3 M2 WWL M1 9 1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance C S V = VBL V PRE = V BIT V PRE ------------ C S + C BL Voltage swing is small; typically around 250 mv. 10 5
DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD 11 Sense Amp Operation V BL V(1) V PRE DV(1) Sense amp activated Word line activated V(0) t 12 6
1-T T DRAM Cell Capacitor Metal word line Poly n + n + Inversion layer Poly induced by plate bias Cross-section SiO 2 Field Oxide Diffused bit line Polysilicon gate Layout Polysilicon plate M 1 word line Uses Polysilicon-Diffusion Capacitance Expensive in Area 13 SEM of poly-diffusion capacitor 1T-DRAM 14 7
Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Isolation Storage electrode Storage Node Poly 2nd Field Oxide Si Substrate Trench Cell Stacked-capacitor Cell 15 EE 141 Summary Digital CMOS design is kicking and well Some major challenges down the road: Cost Power consumption Robustness Complexity Some new circuit solutions and design methodologies are bound to emerge 16 8
18nm FinFET Double-gate structure + raised source/drain Gate Silicon Fin Source BOX Gate X. Huang, et al, 1999 IEDM, p.67~70 Drain Si fin - Body! I d [ua/um] 400 350-1.50 V 300-1.25 V 250-1.00 V 200 150-0.75 V 100-0.50 V 50-0.25 V 0-1.5-1.0-0.5 0.0 V d [V] 17 And after that the nano-age??? age??? Organic (polymer) NEMS Nanotube Nano-optics optics Molecular Nanowire Quantum Dots 18 9
With ever more Exotic Behaviors Scaled MOS Nanometer MOS Beyond MOS 2000 2005 2010 Courtesy R. Rutenbar, CMU 19 Cost Mask cost in 90nm technology is over $1M In 130nm is slowly dropping from 700k Bugs are very expensive Design effort increases in DSM Cost of new tools Non-recurring costs dominate the price effectiveness of low-volume ASICs Need to have a product that can fit multiple applications, customers (flexibility) 20 10
Power will be a problem Power (Watts) 100000 10000 1000 100 10 1 0.1 8085 8086286 386 486 4004 80088080 Pentium proc 18KW 5KW 1.5KW 500W 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive S. Borkar 21 The Productivity Gap Logic Transistors per Chip (K) 10,000,000.10µ 1,000,000.35µ 2.5µ 100,000 10,000 1,000 100 10 1 Logic Transistors/Chip Transistor/Staff Month 58%/Yr. compound Complexity growth rate x x x x x x x 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 21%/Yr. compound Productivity growth rate 2001 2003 2005 2007 2009 100,000,000 10,000,000 1,000,000 100,000 10,000 1,000 100 10 Productivity Trans./Staff - Month Source: SEMATECH 22 11
From ASIC Design (Standard Cells). Cell-structure hidden under interconnect layers 23 To Flexible Solutions: RAM-based FPGA Xilinx XC4025 24 12
Xilinx Vertex-II 18 embedded multipliers PowerPC 3.1 Gbs Serial Interface 25 Flexibility and Efficiency Prog Mem Flexibility MAC Unit µp Addr Gen Embedded DSP Processor (e.g. TI 320CXX ) Direct Mapped Hardware Embedded FPGA Reconfigurable Processor Inefficiency (Power, Area) 26 13
The Challenge of the Next Decade The Deep Sub-Micron (DSM) Effect ( 0.25µ) DSM Microscopic Problems Wiring Load Management Noise, Crosstalk Reliability, Manufacturability Complexity: LRC, ERC Accurate Power Prediction Accurate Delay Prediction etc. Everything Looks a Little Different? 1/DSM Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! 27 That s all Folks Thanks for the fun semester. And good luck in your future endeavors! 28 14