COMINTIONL LOGIC
Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos
Combinational vs. Sequential Logic In Logic Circuit Out In Logic Circuit Out State (a) Combinational (b) Sequential Output = f(in) Output = f(in, Previous In)
Static CMOS Circuit t every point in time (except during the switching transients) each gate output is connected to either or V ss via a low-resistive path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
Static CMOS In1 In2 In3 PUN PMOS Only F = G In 1 In 2 In 3 PDN NMOS Only V SS PUN and PDN are Dual Networks
NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high X Y Y = X if and X Y Y = X if OR NMOS Transistors pass a strong 0 but a weak 1
PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low X Y Y = X if ND = + X Y Y = X if OR = PMOS Transistors pass a strong 1 but a weak 0
Complementary CMOS Logic Style Construction (cont.)
Example Gate: NND
Example Gate: NOR
Example Gate: COMPLEX CMOS GTE C D D C OUT = D + (+C)
4-input NND Gate Vdd In 1 In 2 In 3 In 4 In 1 Out In 2 Out In 3 In 4 GND In1 In2 In3 In4
Properties of Complementary CMOS Gates High noise margins: V OH and V OL are at and GND, respectively. No static power consumption: There never exists a direct path between and V SS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)
Transistor Sizing for symmetrical response (dc, ac) for performance D 6 C 6 12 12 Input Dependent Focus on worst-case D 1 2 2 C 2 F
Propagation Delay nalysis - The Switch Model = R ON V DD R R p R p R p p F F R n C L R n C L R n R n R n R p F C L (a) Inverter (b) 2-input NND (c) 2-input NOR t p = 0.69 R on C L (assuming that C L dominates!)
What is the Value of R on?
nalysis of Propagation Delay R n R n R p R p F C L 1. ssume R n =R p = resistance of minimum sized NMOS inverter 2. Determine Worst Case Input transition (Delay depends on input values) 3. Example: t plh for 2input NND - Worst case when only ONE PMOS Pulls up the output node - For 2 PMOS devices in parallel, the resistance is lower t plh = 0.69R p C L 2-input NND 4. Example: t phl for 2input NND - Worst case : TWO NMOS in series t phl = 0.69(2R n )C L
Design for Worst Case 2 1 1 2 F C L D 2 C D 2 1 2 4 4 2 C 2 F Here it is assumed that R p = R n
Influence of Fan-In and Fan-Out on Delay C D Fan-Out: Number of Gates Connected 2 Gate Capacitances per Fan-Out C D FanIn: Quadratic Term due to: 1. Resistance Increasing 2. Capacitance Increasing (t phl ) t p = a 1 FI+ a 2 FI 2 + a 3 FO
t p as a function of Fan-In 4.0 3.0 t phl t p (nsec) 2.0 quadratic t p 1.0 linear t plh 0.0 1 3 5 7 9 fan-in VOID LRGE FN-IN GTES! (Typically not more than FI < 4)
Fast Complex Gate - Design Techniques Transistor Sizing: s long as Fan-out Capacitance dominates Progressive Sizing: In N MN Out C L M1 > M2 > M3 > MN In 3 M3 C 3 Distributed RC-line In 2 M2 C 2 In 1 M1 C 1 Can Reduce Delay with more than 30%!
Fast Complex Gate - Design Techniques Transistor Ordering (2) critical path critical path In 3 M3 C L In 1 M1 C L In 2 M2 C 2 In 2 M2 C 2 In 1 M1 C 1 In 3 M3 C 3 (a) (b)
Ratioed Logic Resistive Load R L Depletion Load V T < 0 PMOS Load F F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary CMOS
Ratioed Logic Resistive Load R L N transistors + Load V OH = F V OL = R PN R PN + R L In 1 In 2 In 3 PDN ssymetrical response Static power consumption V SS t pl = 0.69 R L C L
ctive Loads PMOS Load V SS F In 1 In 2 In 3 PDN V SS pseudo-nmos
Load Lines of Ratioed Gates 1 Current source I L (Normalized) 0.75 0.5 Pseudo-NMOS 0.25 Resistive load 0 0.0 1.0 2.0 3.0 4.0 5.0 V out (V)
Pass-Transistor Logic Inputs Switch Network Out Out N transistors No static consumption
NMOS-only switch C = 5 V C = 5 V = 5 V = 5 V M 2 M n C L M 1 V does not pull up to 5V, but 5V - V TN Threshold voltage loss causes static power consumption
Solution 1: Transmission Gate C C C C C = 5 V = 5 V C L C = 0 V
Resistance of Transmission Gate 30000.0 R n (W/L) p =(W/L) n = 20000.0 1.8/1.2 R (Ohm) R p 10000.0 R eq 0.0 0.0 1.0 2.0 3.0 4.0 5.0 Vout
NMOS Only Logic: Level Restoring Transistor Level Restorer M r M 2 M n X Out M 1 dvantage: Full Swing Disadvantage: More Complex, Larger Capacitance Other approaches: reduced threshold NMOS
Level Restoring Transistor V out (V) 5.0 3.0 without with V X 5.0 3.0 with without 1.0 V 1.0-1.00 2 4 6 t (nsec) (a) Output node -1.00 2 4 t (nsec) (b) Intermediate node X 6
Single Transistor Pass Gate with V T =0 0V 5V 0V Out 5V WTCH OUT FOR LEKGE CURRENTS
Complimentary Pass Transistor Logic Pass-Transistor Network F (a) Inverse Pass-Transistor Network F F= F=+ F= ΒÝ (b) F= F=+ F= ΒÝ ND/NND OR/NOR EXOR/NEXOR
4 Input NND in CPL
Dynamic Logic M p Out M e In 1 In 2 In 3 PDN C L In 1 In 2 In 3 PUN Out M e M p C L n network p network 2 phase operation: Precharge Evaluation
Example M p Out N + 1 Transistors Ratioless No Static Power Consumption C Noise Margins small (NM L ) Requires Clock M e
Dynamic 4 Input NND Gate Out In 1 In 2 In 3 In 4 GND
Reliability Problems Charge Leakage M p Out (1) (2) C L V out precharge evaluate t M e (a) Leakage sources (b) Effect on waveforms t Minimum Clock Frequency: > 1 MHz
Charge Sharing (redistribution) case 1) if V out < V Tn M p Out C L = C V t L out ( ) + C V V a ( Tn ( X )) or M a X C L V out = V out ( t) = C a -------V ( C DD V Tn ( V X )) L = 0 M b C a case 2) if V out > V Tn M e C b C a V out V -------------------- = DD C + C a L
Charge Redistribution - Solutions M p M bl Out M p M bl Out M a M a M b M b M e M e (a) Static bleeder (b) Precharge of internal nodes
Clock Feedthrough M p Out could potentially forward bias the diode M a X C L 5V M b C a overshoot M e C b out
Domino Logic M p Out1 M p M r Out2 In 1 In 2 PDN In 4 PDN Static Inverter with Level Restorer In 3 M e M e
Domino Logic - Characteristics Only non-inverting logic Very fast - Only 1->0 transitions at input of inverter move V M upwards by increasing PMOS dding level restorer reduces leakage and charge redistribution problems Optimize inverter for fan-out
NP-CMOS M p Out1 M e In 1 In 2 In 3 PDN In 4 PUN Out2 M e M p Only 1 0 transitions allowed at inputs of PUN
NP CMOS dder S 1 1 1 1 1 C i1 1 1 C i2 1 C i1 1 0 0 0 0 C i1 0 0 C i0 0 0 C i0 S 0 C i0 Carry Path
CMOS Circuit Styles - Summary