Lecture 4: Implementing Logic in CMOS Mark Mcermott Electrical and Computer Engineering The University of Texas at ustin
Review of emorgan s Theorem Recall that: () = + and = ( + ) (+) = and + = ( ) () + ( + ) (+) + () Page 2
ubble Pushing Start with network of N / OR gates Convert to NN / NOR + inverters Push bubbles around to simplify logic (a) (b) (c) (d) Page 3
Static CMOS Circuits N and P channel networks implement logic functions Each network connected between Output and V or VSS Parallel network: "OR" function Series network: "N" function Page 4
uality in CMOS Circuits N and P networks must implement complementary functions uality is sufficient for correct operation P What are the values of, and C which will produce a connection between P and Q C + * C Q Page 5
Constructing Complex Gates Example: F = ( * ) + (C * ) Take un-inverted function F = ( + C) and derive N-network Identify N, OR components; F is OR of,c Make connections of transistors N, Series connection, OR, Parallel F C Page 6
Construction of Complex Gates, Cont d Construct P-network by taking complement of N-expression ( +C), which gives the expression, ( + ) * (C + ) Combine P and N circuits V C F C C Page 7
Layout of Complex Gate V N-OR-INVERT (OI) gate Metal 2 V dd C C F Metal 1 F C Layout GN Page 8
Example of Compound Gate V F = ( + + C) * C F C Page 9
Example of More Complex Gate +V E C F G H OUT OUT = (+)*(C+)*(E+F+GH) C E F G H Page 10
Exclusive-NOR Gate in CMOS IN1 IN2 OUTPUT V P P P N N OUTPUT = + OUT P N IN1 () IN2 () N Page 11
Pseudo nmos Logic V Generally a weak device Z C E Page 12
uality is not Necessary Functions realized by N and P networks must be complementary, and one of them must conduct for every input combination V a b c d F = ab + a b + a c + cd + c d a b c a b c d d F The N and P networks are NOT duals, but the switching functions they implement are complementary a b "Hybrid" CMOS Circuit a b a c c d c d GN Page 13
Example of ual Rail Complex CMOS Gate V F = G z z F G = x x x x y y Page 14
Signal Strength Strength of signal How close it approximates ideal voltage source V and GN rails are strongest 1 and 0 nmos pass strong 0 ut degraded or weak 1 pmos pass strong 1 ut degraded or weak 0 Thus nmos are best for pull-down network Page 15
Pass Transistors Transistors can be used as switches s g d s s g = 0 g = 1 d d Input g = 1 Output 0 strong 0 g = 1 1 degraded 1 s g d s s g = 0 g = 1 d d Input g = 0 Output 0 degraded 0 g = 0 strong 1 Page 16
Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well a g gb b g = 0, gb = 1 a b g = 1, gb = 0 a b Input Output g = 1, gb = 0 0 strong 0 g = 1, gb = 0 1 strong 1 a g b a g b a g b gb gb gb Page 17
Pass Transistor Logic What is the difference between the two circuits? P 1 C, C F(,,C) P 2 F(,) P 3 P 4 Page 18
Pass Transistor Logic -- etter Layout Group similar transistors, so they can be in the same well P 4 F(,) P 3 P 2 P 1 Page 19
Pass Transistor Logic Pull-Up Version How do voltage levels at the output of this gate differ from that of the pass-transistor multiplexer in the previous foil? F(,) Page 20
Tristates Tristate buffer produces Z when not enabled EN 0 0 EN 0 1 1 0 EN 1 1 EN Page 21
Non-restoring Tri-state Transmission gate acts as Tri-state buffer Only two transistors ut nonrestoring Noise on is passed on to EN EN Page 22
Tri-state Inverter Tri-state inverter produces restored output Violates conduction complement rule ecause we want a Z output EN EN EN = 0 = 'Z' EN = 1 = Page 23
Multiplexers (mux) 2:1 multiplexer chooses between two inputs S 1 0 0 X 0 0 0 X 1 1 0 1 0 1 S 1 0 X 0 1 1 X 1 Page 24
Gate-Level Mux esign How many transistors are needed? = S + S 1 0 (too many transistors) 20 1 S 0 1 S 0 2 4 4 2 2 4 2 Page 25
Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors if both of the select signals are available If not then it takes 6 transistors S 0 1 S S Page 26
Inverting Mux Inverting multiplexer Use compound OI22 Or pair of tristate inverters Essentially the same thing Non-inverting multiplexer requires adding an inverter 0 S S S 1 S 0 S S 1 S S 0 1 0 1 S Page 27
4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates Requires pre-decoded signals S1S0 S1S0 S1S0 S1S0 0 S0 S1 0 1 2 0 1 0 0 1 1 2 3 1 3 Page 28
Latch** When = 1, latch is transparent flows through to Q like a buffer When = 0, the latch is opaque Q holds its old value independent of Latch Q Q ** transparent latch or level-sensitive latch Page 29
Latch esign Multiplexer chooses or old Q 1 0 Q Q Q Q Page 30
Flip-flop esign uilt from master and slave latches QM Q Latch QM Latch Q Page 31
Questions? Page 32