.7.4: Direct frequency dmain circuit analysis Revisin: August 9, 00 5 E Main Suite D Pullman, WA 9963 (509) 334 6306 ice and Fax Overview n chapter.7., we determined the steadystate respnse f electrical circuits t sinusidal signals using phasr representatins f the signals invlved, and timedmain representatins f the circuit element vltagecurrent relatins. Applying KL and KCL in this manner resulted in gverning equatins in which the time dependence had been remved, which cnverted the gverning equatins frm differential equatins t algebraic equatins. Unknwns in the resulting algebraic equatins were the phasr representatins f the signals. These equatins culd then be slved t determine the desired signals in phasr frm; these results culd then be used t determine the timedmain representatins f the signals. n chapter.7.3, we replaced the timedmain vltagecurrent relatins fr passive electrical circuit elements with impedances, which prvide vltagecurrent relatins fr the circuit elements directly in the frequency dmain. At the end f chapter.7.3, we used these impedances t schematically represent a circuit directly in the frequency dmain. n this sectin, we will use this frequencydmain circuit representatin t perfrm circuit analysis directly in the frequency dmain using phasr representatins f the signals and impedance representatins f the circuit elements. This will allw us t write the algebraic equatins gverning the phasr representatin f the circuit directly, withut any reference t the time dmain behavir f the circuit. As in chapter.7., these equatins can be slved t determine the behavir f the circuit in terms f phasrs, and the results transfrmed t the time dmain. Perfrming the circuit analysis directly in the frequency dmain using impedances t represent the circuit elements results can result in a significant simplificatin f the analysis. n additin, many circuit analysis techniques which were previusly applied t resistive circuits (e.g. circuit reductin, ndal analysis, mesh analysis, superpsitin, Thevenin s and rtn s Therems) are directly applicable in the frequency dmain. Since these analysis techniques have been presented earlier fr resistive circuits, in this sectin we will simply:. prvide examples f applying these analysis methds t frequencydmain circuits, and. nte any generalizatins relative t using phasrs in these analysis methds. Thrughut this sectin, the student shuld firmly keep in mind that we are dealing nly with the steadystate respnses f circuits t sinusidal frcing functins. Dc: XXXYYY page f 8
.7.4: Direct frequency dmain circuit analysis Befre beginning this mdule, yu shuld be able t: Use phasrs t represent sinusidal signals (chapter.7.) Perfrm cmplex arithmetic Calculate impedances fr resistrs, capacitrs, and inductrs (chapter.7.3) After cmpleting this mdule, yu shuld be able t: State, frm memry, KL and KCL in phasr frm State, frm memry, vltage and current divider frmulae in phasr frm Determine equivalent impedances f parallel and series impedance cmbinatins Apply circuit reductin techniques t frequency dmain circuits Analyze frequency dmain circuits using ndal and mesh analysis Use superpsitin t analyze circuits in which multiple frequencies are present State Thevenin s and rtn s therems fr frequency dmain circuits Determine the lad impedance necessary t deliver maximum pwer t a lad This mdule requires: /A www.digilentinc.cm page f 8
.7.4: Direct frequency dmain circuit analysis Kirchff s ltage Law: Kirchff s ltage Law states that the sum f the vltage differences arund any clsed lp is zer. Therefre, if v ( t ),v( t ),...,v ( t ) are the vltages arund sme clsed lp, KL prvides: k = v k ( t) = 0 () Substituting the phasr representatin f the vltages results in: k e k= jωt = 0 () Dividing equatin () by j t e ω results in: k k= = 0 (3) S that KL states that the sum f the phasr vltages arund any clsed lp is zer. Kirchff s Current Law: Kirchff s Current Law states that the sum f the currrents entering any nde is zer. Therefre, if i ( t ),i( t ),...,i ( t ) are the currents entering a nde, KCL prvides: i k= k ( t ) = 0 (4) Substituting the phasr representatin f the currents results in: k= j t k e ω = 0 (5) Dividing equatin () by j t e ω results in: k= k = 0 (6) S that KL states that the sum f the phasr currents entering (r leaving) a nde is zer. mprtant result: KL and KCL apply directly in the frequency dmain. www.digilentinc.cm page 3 f 8
.7.4: Direct frequency dmain circuit analysis Example: RC circuit steadystate sinusidal respnse n this example, we will revisit example frm chapter.7.. n that example, we determined the capacitr vltage in the circuit t the left belw, using phasr analysis techniques applied t the circuit s timedmain gverning equatin. n this example, we will represent the circuit itself directly in the frequency dmain, using impedance representatins f the circuit element. The frequencydmain representatin f the circuit is shwn t the right belw. p cs( t) R C y(t) P 0 R jωc Y By the definitin f impedance, we can determine the current thrugh the capacitr t be: = Y C = Y jωc = jωcy The vltage acrss the resistr can nw, by the definitin f impedance, be written as = R = R( jωcy ). We nw apply KL fr phasrs t the circuit t the right abve, which R leads t: P 0 = R( jωcy ) Y Slving fr Y in this equatin prvides Y P 0 = jωrc By the rules f cmplex arithmetic, we can determine the magnitude and phase angle f Y t be: Y = Y = tan P ( ωrc) ( ωrc) And the timedmain slutin fr y(t) is thus y( t ) = P ( ωrc) cs [ ωt tan ( ωrc) ] www.digilentinc.cm page 4 f 8
.7.4: Direct frequency dmain circuit analysis Parallel and Series mpedances & Circuit Reductin Cnsider the case f impedances cnnected in series, as shwn in Figure. Since the elements are in series, and since we have seen that KCL applies t phasrs, the phasr current flws thrugh each f the impedances. Applying KL fr phasrs arund the single lp, and incrprating the definitin f impedance, we btain: = ( ) 0 (7) = Figure. Series cmbinatin f impedances. f we define eq as the equivalent impedance f the series cmbinatin, we have eq =, where (8) eq = s that impedances in series sum directly. Thus, impedances in series can be cmbined in the same way as resistances in series. By extensin f the abve result, we can develp a vltage divider frmula fr phasrs. Withut derivatin, we state that the phasr vltage acrss the k th impedance in a series cmbinatin f impedances as shwn in Figure can be determined as: k = k (9) s that ur vltage divisin relatinships fr resistrs in series apply directly in the frequency dmain fr impedances in series. We nw cnsider the case f impedances cnnected in parallel, as shwn in Figure. Since the elements are in parallel, and KL applied t each lp shws that all circuit elements share the same phasr vltage difference. Applying KCL fr phasrs at the upper nde, and incrprating the definitin f admittance, we btain: = (Y Y Y ) 0 (0) = www.digilentinc.cm page 5 f 8
.7.4: Direct frequency dmain circuit analysis Figure. Parallel cmbinatin f impedances. f we define Y eq as the equivalent impedance f the series cmbinatin, we have: = () Y eq where Y eq = Y Y Y () s that admittances in series sum directly. Cnverting ur admittances t impedances indicates that the equivalent impedance f a parallel cmbinatin f impedances as shwn in Figure is: eq = L (3) Thus, impedances in parallel can be cmbined in the same way as resistances in parallel. By extensin f the abve result, we can develp a current divider frmula fr phasrs. Withut derivatin, we state that the phasr current acrss the k th impedance in a series cmbinatin f impedances as shwn in Figure can be determined as: k = k L (4) s that ur current divisin relatinships fr resistrs in parallel apply directly in the frequency dmain fr impedances in parallel. mprtant result: All circuit reductin techniques fr resistances apply directly t the frequency dmain fr impedances. Likewise, vltage and current divider relatinships apply t phasr circuits in the frequency dmain exactly as they apply t resistive circuits in the time dmain. www.digilentinc.cm page 6 f 8
.7.4: Direct frequency dmain circuit analysis Example : Use circuit reductin techniques t determine the current phasr leaving the surce in the circuit belw. (te: the circuit belw is the frequency dmain circuit we btained in example f chapter.7.3.) 0 30 Since impedances in series add directly, the inductr and resistr can be cmbined int a single equivalent impedance f (j)ω, as shwn in the figure t the left belw. The capacitr is then in parallel with this equivalent impedance. Since impedances in parallel add in the same way as resistrs in parallel, the equivalent impedance f this parallel cmbinatin can be calculated by ( j3 )( j) 3 j6 dividing the prduct f the impedances by their sum, s eq = Ω = Ω. ( j3 ) ( j ) j Cnverting this impedance t plar frm results in shwn in the figure t the right belw. eq =.37 8 Ω ; the final reduced circuit is 0 30 0 30.37 8 Ω Using the reduced circuit t the right abve and the definitin f impedance, we can see that: 0 30 0 = = [ 30 ( 8 )]A. 37 8 Ω. 37 s that = 8. 44 48 A www.digilentinc.cm page 7 f 8
.7.4: Direct frequency dmain circuit analysis Example 3: Use circuit reductin techniques t determine the current, i(t) thrugh the inductr in the circuit belw. With ω= rad/sec, the frequency dmain representatin f the circuit is as shwn in the figure t the left belw; in that figure, we have als defined the current phasr leaving the surce. S S 5 0 We nw emply circuit reductin techniques t determine the phasr. T d this, we first determine the circuit impedance seen by the surce; this impedance allws us t determine the surce current. The current can be determined frm a current divider relatin and. S The impedances f the series cmbinatin f the capacitr and the 4Ω resistr is readily btained by adding their individual impedances, as shwn in the figure t the left belw. This equivalent impedance is then in parallel with the inductr s impedance; the equivalent impedance f this parallel cmbinatin is as shwn in the circuit t the right belw. S S S 5 0 (4j4) j4 5 0 (4j4) The surce current is then, by the definitin f impedance, 5 0 = = 0. 69 33. 7 ( 4 j4 ) Ω Ω. S The circuit t the left abve, alng with ur vltage divider frmula, prvides: ( 4 j4 ) Ω = S = ( j ) Ω 0. 69 33. 7 = 0. 98 78. 7 ( 4 j4 ) Ω j4ω And the current i ( t ) = 0. 98cs( t 78. 7 ) dal and Mesh Analysis: www.digilentinc.cm page 8 f 8
.7.4: Direct frequency dmain circuit analysis dal analysis and mesh analysis techniques have been previusly applied t resistive circuits in the time dmain. n ndal analysis, we applied KCL at independent ndes and used Ohm s Law t write the resulting equatins in terms f the nde vltages. n mesh analysis, we applied KL and used Ohm s Law t write the resulting equatins in terms f the mesh currents. n the frequency dmain, as we have seen in previus subsectins, KL and KCL apply directly t the phasr representatins f vltages and currents. Als, in the frequency dmain, impedances can be used t represent vltagecurrent relatins fr circuit elements in the frequency dmain in the same way that Ohm s Law applied t resistrs in the time dmain (the relatin = in the frequency dmain crrespnds exactly t the relatin v( t ) = R i( t ) in the time dmain). Thus, ndal analysis and mesh analysis apply t frequency dmain circuits in exactly the same way as t time dmain resistive circuits, with the fllwing mdificatins: The circuit excitatins and respnses are represented by phasrs Phasr representatins f nde vltages and mesh currents are used mpedances are used in the place f resistances Applicatin f ndal and mesh analysis t frequencydmain circuit analysis is illustrated in the fllwing examples. Example 4: Use ndal analysis t determine the current i(t) in the circuit f example 3. The desired frequencydmain circuit was previusly determined in Example 3. dal analysis f the frequencydmain circuit prceeds exactly as was dne in the case f resistive circuits. The reference vltage, R = 0, and ur single nde vltage, A, fr this circuit are defined n the circuit belw. 5 0 Applying KCL in phasr frm at nde A prvides: 5 0 Ω A A ( 4 j4 ) Ω A j4ω = 0 Slving fr gives A = 3. 9. 3. By the definitin f impedance, the desired current A A 3. 9. 3 phasr = = = 0. 98 78. 7 s that i ( t ) = 0. 98cs( t 78. 7 ), which is j4ω 4 90 cnsistent with ur result btained via circuit reductin in Example 3. Example 5: Use mesh analysis t determine the current i(t) in the circuit f examples 3 and 4. www.digilentinc.cm page 9 f 8
.7.4: Direct frequency dmain circuit analysis The desired frequencydmain circuit was previusly determined in Example 3. Mesh analysis f the frequencydmain circuit prceeds exactly as fr resistive circuits. The figure belw shws ur chice f mesh lps; the series resistrcapacitr cmbinatin has been cmbined int a single equivalent resistance in the figure belw, fr clarity. 5 0 KL arund the mesh lp prvides: 5 0 ( 4 j4 )( ) = KL arund the mesh lp prvides: ( 4 j4 )( ) j4 = 0 0 The secnd equatin abve can be simplified t prvide: = ( j ). Using this result t eliminate in the mesh equatin fr lp and simplifying prvides: ( 6 j4 ) 5 0 = ( j4 4 ) j s that = 0. 98 78. 7. The mesh current is simply the desired current, s in the time dmain, i ( t ) = 0. 98cs( t 78. 7 ) which is cnsistent with ur results frm examples 3 and 4. mprtant result: dal and mesh analysis methds apply t phasr circuits exactly as they apply t resistive circuits in the time dmain. mpedances simply replace resistances, and quantities f interest becme cmplex valued. www.digilentinc.cm page 0 f 8
.7.4: Direct frequency dmain circuit analysis Superpsitin: The extensin f superpsitin t the frequency dmain is an extremely imprtant tpic. Several cmmn analysis techniques yu will encunter later in this curse and in future curses (frequency respnse, Furier Series, and Furier Transfrms, fr example) will depend heavily upn the superpsitin f sinusidal signals. n this subsectin, we intrduce the basic cncepts invlved. n all f ur steadystate sinusidal analyses, we have required that the circuit is linear. (The statement that the steady state respnse t a sinusidal input is a sinusid at the same frequency requires the system t be linear. nlinear systems d nt necessarily have this characteristic.) Thus, all phasr circuits are linear and superpsitin must apply. Thus, if a phasr circuit has multiple inputs, we can calculate the respnse f the circuit t each input individually and sum the results t btain the verall respnse. t is imprtant t realize, hwever, that the final step f summing the individual cntributins t btain the verall respnse can, in general, nly be dne in the time dmain. Since the phasr representatin f the circuit respnse implicitly assumes a particular frequency, the phasr representatins cannt be summed directly. The time dmain circuit respnse, hwever, explicitly prvides frequency infrmatin, allwing thse respnses t be summed. n fact, because the frequencydmain representatin f the circuit depends upn the frequency f the input (in general, the impedances will be a functin f frequency), the frequency dmain representatin f the circuit itself is, in general, different fr different inputs. Thus, the nly way in which circuits with multiple inputs at different frequencies can be analyzed in the frequency dmain is with superpsitin. n the special case in which all inputs share a cmmn frequency, the circuit respnse can be determined by any f ur previus analysis techniques (circuit reductin, ndal analysis, mesh analysis, superpsitin, etc.) n this case, if superpsitin is used, the circuit respnse t individual inputs can be summed directly in the frequency dmain if desired. Examples f the applicatin f superpsitin t analysis f frequencydmain circuits are prvided belw. mprtant result: n the case f multiple frequencies existing in the circuit, superpsitin is the nly valid frequencydmain analysis apprach. Superpsitin applies directly in the frequency dmain, insfar as cntributins frm individual surces can be determined by killing all ther surces and analyzing the resulting circuit. n general, hwever, superimpsing (summing) the cntributins frm the individual surces must be dne in the time dmain. Superpsitin f respnses t individual surces can be summed directly in the frequency dmain (e.g. additin f the phasrs representing the individual respnses) is nly apprpriate if all surces have the same frequency. n this case (all surce having the same frequency) any f ur ther mdeling appraches are als valid. www.digilentinc.cm page f 8
.7.4: Direct frequency dmain circuit analysis Example 6: Determine the vltage v(t) acrss the inductr in the circuit belw. H 3 Since tw different input frequencies are applied t the circuit, we must use superpsitin t determine the respnse. The circuit t the left belw will prvide the phasr respnse t the current surce; the frequency is ω = 9 rad/sec and the vltage surce is killed. The circuit t the right belw will prvide the phasr respnse t the vltage surce; the frequency is ω = 3 rad/sec and the current surce is killed. 6 0 j3 j 4 30 T determine the vltage phasr resulting frm the current surce ( in the circuit t the left abve), we nte that the inductr and the 3Ω resistr frm a current divider. Thus, the current thrugh the inductr resulting frm the current surce is 3Ω 3 0 6 0 6 = 6 0 = = 45 ( 3 j3 ) Ω 3 45. The vltage phasr can then be determined by multiplying this current times the inductr s impedance: 6 6 = j3ω 45 = 3 90 45 = 9 45 and the timedmain vltage acrss the inductr due t the current surce is: v ( t ) = 9 cs( 9t 45 ) T determine the vltage phasr resulting frm the vltage surce ( in the circuit t the right abve), we nte that the inductr and the 3Ω resistr nw frm a vltage divider. Thus, the vltage can be readily determined by: jω 90 4 30 4 = 4 30 = = 0 6 ( 3 j ) Ω 0 8. 4 0. www.digilentinc.cm page f 8
.7.4: Direct frequency dmain circuit analysis S that the timedmain vltage acrss the inductr due t the vltage surce is: 4 v ( t ) = cs( 3t 0. 6 ) 0 The verall vltage is then the sum f the cntributins frm the tw surces, in the time dmain, s: And v( t ) = v ( t ) v( t ) 4 v ( t ) = 9 cs( 9t 45 ) cs( 3t 0. 6 ) 0 Example 7: Determine the vltage v(t) acrss the inductr in the circuit belw. H 3 This circuit is essentially the same as the circuit f Example 6, with the imprtant difference that the frequency f the vltage input has changed the vltage surce and current surce bth prvide the same frequency input t the circuit, 9 rad/sec. We will first d this prblem using superpsitin techniques. We will then use ndal analysis t slve the prblem, t illustrate that multiple inputs at the same frequency d nt require the use f superpsitin. ndividually killing each surce in the circuit abve results in the tw circuits shwn belw. te that the impedance f the inductr is nw the same in bth f these circuits. 6 0 4 30 The tw circuits shwn abve will nw be analyzed t determine the individual cntributins t the inductr vltage; these results will then be summed t determine the verall inductr vltage. www.digilentinc.cm page 3 f 8
.7.4: Direct frequency dmain circuit analysis The circuit t the left abve has been analyzed in Example 6. Therefre, the vltage phasr is the same as determined in Example 6: = 9 45 The vltage in the circuit t the right abve can be determined frm applicatin f the vltage divider frmula fr phasrs: j3ω 3 90 4 30 = 4 30 = = 75 ( 3 j3) Ω 3 45 Since bth inputs have the same frequency, we can superimpse the phasr results directly (we culd, f curse, als determine the individual time dmain respnses and superimpse thse respnses if we chse): = = 9 45 75 = 5. 4 50. 3 S that the time dmain inductr vltage is v ( t ) = 5. 4cs( 9t 50. 3 ). tice that the circuit respnse has nly a single frequency cmpnent, since bth inputs have the same frequency. The superpsitin apprach prvided abve is entirely valid. Hwever, since bth surces have the same input, we can chse any f ur ther analysis appraches t perfrm this prblem. T emphasize this fact, we chse t d this prblem using ndal analysis. The frequencydmain circuit, with ur definitin f reference vltage and independent nde, is shwn in the figure belw. 6 0 4 30 KCL at nde A prvides: 0 6 0 = j3ω A A 4 30 3Ω Slving the abve equatin fr prvides A = 5. 4 50. 3 s that the inductr vltage as a functin f time is: v ( t ) = 5. 4cs( 9t 50. 3 ) A Which is cnsistent with ur result using superpsitin. Thévenin s & rtn s Therems, Surce Transfrmatins, and Maximum Pwer Transfer www.digilentinc.cm page 4 f 8
.7.4: Direct frequency dmain circuit analysis Applicatin f Thévenin s and rtn s Therems t frequency dmain circuits is identical t their applicatin t time dmain resistive circuits. The nly differences are: the pen circuit vltage (v c ) and shrt circuit current (i sc ) determined fr resistive circuits is replaced by their phasr representatins, OC and SC The Thévenin resistance, R TH, is replaced by a Thévenin impedance, TH. Thus, the Thévenin and rtn equivalent circuits in the frequency dmain are as shwn in Figure 3. TH OC SC TH (a) Thévenin circuit (b) rtn circuit Figure 3. Thévenin and rtn equivalent circuits. Since Thévenin s and rtn s Therems bth apply in the frequency dmain, the appraches we used fr surce transfrmatins in the time dmain fr resistive circuits translate directly t the frequency dmain, with impedances substituted fr resistances and phasrs used fr vltage and current terms. n rder t determine the lad necessary t draw the maximum pwer frm a Thévenin equivalent circuit, we must rederive the maximum pwer result btained previusly fr resistive circuits, substituting impedances fr admittances and using phasrs fr surce terms. We will nt derive the gverning relatinship, but will simply state that, in rder t transfer the maximum pwer t a lad, the lad impedance must be the cmplex cnjugate f the Thévenin impedance f the circuit being laded. Thus, if a Thévenin equivalent circuit has sme impedance TH with a resistance R TH and X a reactance TH, the lad which will draw the maximum pwer frm this circuit must have resistance R TH and a reactance X TH. The apprpriate laded circuit is shwn in Figure 4 belw. = R TH Th jx TH OC L = R Th jx TH Figure 4. Lad impedance t draw maximum pwer frm a Thévenin circuit. Example 8: Determine the Thévenin equivalent circuit seen by the lad in the circuit belw www.digilentinc.cm page 5 f 8
.7.4: Direct frequency dmain circuit analysis n the circuit belw, we have used the input frequency, ω = rad/sec, t cnvert the circuit t the frequency dmain. j 0 L Remving the lad and killing the surce allws us t determine the Thévenin resistance f the circuit. The apprpriate circuit is: TH The parallel cmbinatin f tw, Ω resistrs have an equivalent resistance f Ω. This impedance, in series with the jω impedance, results in a Thévenin impedance TH = ( j ) Ω. Replacing the surce, but leaving the lad terminals pencircuited, as shwn in the figure belw, allws us t determine the pencircuit vltage. OC j 0 OC Since there is n current thrugh the inductr, due t the pencircuit cnditin, OC is determined frm a simple resistive vltage divider frmed by the tw, Ω resistrs. Thus, the pencircuit vltage is: www.digilentinc.cm page 6 f 8
.7.4: Direct frequency dmain circuit analysis Ω OC = 0 = 0. Ω Ω The resulting Thévenin equivalent circuit is shwn belw: 0 Example 9: Determine the rtn equivalent circuit f the circuit f example 8. Since we determined the Thévenin equivalent circuit in Example 8, a surce transfrmatin can be used t determine the rtn equivalent circuit. Cnsistent with ur previus surce transfrmatin rules, the shrtcircuit current, SC, is equal t the pencircuit vltage divided by the Thévenin impedance: SC OC 0 0 = = = = 45 ( j) Ω 45 TH Since the impedance desn t change during a surce transfrmatin, the rtn equivalent circuit is therefre as shwn belw: 45 www.digilentinc.cm page 7 f 8
.7.4: Direct frequency dmain circuit analysis Example 0: Determine the lad impedance fr the circuit f Example 8 which will prvide the maximum amunt f pwer t be delivered t the lad. Prvide a physical realizatin (a circuit) which will prvide this impedance. The maximum pwer is delivered t the lad when the lad impedance is the cmplex cnjugate f the Thévenin impedance. Thus, the lad impedance fr maximum pwer transfer is: L = ( j ) Ω And the laded Thévenin circuit is: (j) 0 (j) T implement this lad, let us lk at a parallel RC cmbinatin. With the frequency ω = rad/sec, the frequency dmain lad lks like: R j C L Cmbining parallel impedances results in: L ( R ) j = C R j C Ω = R j R 4C R 4C C Ω Setting R = Ω and C = 0.5F makes f ur lad is as shwn belw: L = ( j ) Ω, as desired, s the physical implementatin www.digilentinc.cm page 8 f 8