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TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC697AP, TC74HC697AF TC74HC697AP/AF Synchronous Presettable 4-Bit Binary Up/Down Counter with Output Register (multiplexed 3-state outputs) The TC74HC697A is high speed CMOS UP/DOWN COUNTERS fabricated with silicon gate C 2 MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It counts on the rising edge of the Counter Clock (CCK) input when counter mode is selected. If the up/down ( U/ D ) input is held high, the internal counter counts up. Conversely, if U/ D is held low, it counts down. The internal counters outputs are latched into the output registers on the rising edge of the Register Clock (RCK) input. The outputs (QA~QD) are selected as either internal counter or registered outputs by the output select ( R/ C ) input. When high, the outputs are counter outputs and when low, they are registered outputs. Two enable ( ENP, ENT ) inputs and a carry ( RCO ) output are provided to enable cascading of the counters. This facilitates easy implementation of n-bit counters without using external gates. All inputs are equipped with protection circuits agait static discharge or traient excess voltage. Features High speed: f max = 38 MHz (typ.) at V CC = V Low power dissipation: I CC = 4 μa (max) at Ta = 2 C High noise immunity: V NIH = V NIL = 28% V CC (min) Outputs drive capability: 1 LSTTL loads for QA~QD 10 LSTTL loads for RCO Symmetrical output impedance: I OH = I OL = 6 ma (min) for QA~QD I OH = I OL = 4 ma (min) for RCO Balanced propagation delays: Wide operating voltage range: V CC (opr) = 2 to 6 V Pin and function compatible with 74LS697 TC74HC697AP TC74HC697AF Weight DlP-P-300-2.4A SOP-P-300-1.27A : 1.30 g (typ.) : 0.22 g (typ.) Start of commercial production 1988-11 1

Pin Assignment IEC Logic symbol Block Diagram 2

Truth Table Inputs Outputs CCLR LOAD ENP ENT CCK U/ D RCK R/ C G QA QB QC QD X X X X X X X X H Z Z Z Z Z Function L X X X X X X L L L L L L Clear Counter H L X X X X L L a b c d Load Counter H H H X X X L L H H X H X X L L No Change No Count H H L L H X L L Count Up Count H H L L L X L L Count Down Count H X X X X X L L No Change No Count X X X X X X H L a b c d Load Register X X X X X X H L No Change No Count X: Don t care Z: High impedance a~d: The level of steady state inputs at inputs A through D respectively. a ~d : The level of steady state outputs at internal counter outputs QA through QD respectively. RCO = ( UP QA QB QC QD ENT+ UP QA QB QC QD ENT ) 3

Timing Chart 4

System Diagram

Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range V CC 0. to 7 V DC input voltage V IN 0. to V CC + 0. V DC output voltage V OUT 0. to V CC + 0. V Input diode current I IK ± ma Output diode current I OK ± ma DC output current ( RCO ) (QA~QD) I OUT ±2 ±3 ma DC V CC /ground current I CC ±7 ma Power dissipation P D 00 (DIP) (Note 2)/180 (SOP) mw Storage temperature T stg 6 10 C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditio (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ( Handling Precautio / Derating Concept and Methods ) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 00 mw in the range of Ta = 40 to 6 C. From Ta = 6 to 8 C a derating factor of 10 mw/ C shall be applied until 300 mw. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage V CC 2 to 6 V Input voltage V IN 0 to V CC V Output voltage V OUT 0 to V CC V Operating temperature T opr 40 to 8 C 0 to 1000 (V CC = V) Input rise and fall t r, t f 0 to 00 (V CC = V) 0 to 400 (V CC = V) Note: The operating ranges must be maintained to eure the normal operation of the device. Unused inputs must be tied to either V CC or GND. 6

Electrical Characteristics DC Characteristics Characteristics Symbol Test Condition Ta = 2 C V CC (V) Ta = 40 to 8 C Min Typ. Max Min Max Unit High-level input voltage V IH 1.0 3.1 4. 1.0 3.1 4. V Low-level input voltage V IL 0.0 1.3 1.80 0.0 1.3 1.80 V High-level output voltage V OH V IN = V IH or V IL RCO I OH = μa I OH = 4 ma I OH =.2 ma 1.9 4.4.9 4.18.68 4..80 1.9 4.4.9 4..63 V QA~QD I OH = 6 ma I OH = 7.8 ma 4.18.68 4..80 4..63 Low-level output voltage V OL V IN = V IH or V IL RCO I OL = μa I OL = 4 ma I OL =.2 ma 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 0.1 0.1 0.33 0.33 V QA~QD I OL = 6 ma I OL = 7.8 ma 0.17 0.18 0.26 0.26 0.33 0.33 3-state output off-state current Input leakage current Quiescent supply current I OZ V IN = V IH or V IL V OUT = V CC or GND ±0. ±.0 μa I IN V IN = V CC or GND ±0.1 ±1.0 μa I CC V IN = V CC or GND 4.0 40.0 μa 7

Timing Requirements (input: t r = t f = 6 ) Characteristics Symbol Test Condition Ta = 2 C Ta = 40 to 8 C V CC (V) Typ. Limit Limit Unit Minimum pulse width (CCK, RCK ) t W (L) t W (H) 7 1 9 19 16 Minimum pulse width ( CCLR ) t W (L) 7 1 9 19 16 Minimum set-up ( LOAD, ENT, ENP ) t s 10 30 190 38 32 Minimum set-up (A, B, C, D) t s 0 10 9 6 11 Minimum set-up ( U/ D ) t s 100 17 12 2 21 Minimum set-up (CCK-RCK) t s 100 17 12 2 21 Minimum hold (A, B, C, D) t h 0 0 Minimum hold t h 0 0 0 0 Minimum removal t rem 4 Clock frequency f 2 MHz 24 AC Characteristics (C L = 1 pf, V CC = V, Ta = 2 C, input: t r = t f = 6 ) Characteristics Symbol Test Condition Min Typ. Max Unit Output traition ( RCO ) t TLH t THL 4 8 (CCK- RCO ) 24 41 (ENT- RCO ) 23 ( CCLR - RCO ) 23 38 Maximum clock frequency f max 2 38 MHz 8

AC Characteristics (input: t r = t f = 6 ) Characteristics Output traition (Qn) Output traition ( RCO ) (CCK-Q) (RCK-Q) ( R/ C -Q) ( CCLR -Q) (CCK- RCO ) ( ENT - RCO ) ( CCLR - RCO ) Symbol Test Condition Ta = 2 C CL (pf) t TLH t THL 0 0 0 10 0 10 0 10 0 10 0 0 0 V CC (V) Ta = 40 to 8 C Min Typ. Max Min Max 2 7 6 30 8 7 90 26 19 103 23 82 24 18 9 22 60 19 14 73 24 18 89 26 102 24 108 23 63 18 14 98 23 60 12 10 7 1 19 39 33 23 47 40 180 36 2 44 37 14 2 18 37 19 39 33 23 47 40 23 47 40 27 23 2 44 37 7 1 9 19 16 24 49 42 9 0 22 4 38 27 47 180 36 230 46 39 24 49 42 9 0 9 0 170 34 27 47 Unit 9

Characteristics Output enable ( G-Q) Output disable ( G-Q) Maximum clock frequency Symbol t pzl t pzh R L = 1 kω Test Condition Ta = 2 C CL (pf) 0 10 t plz R L = 1 kω 0 t phz f max 0 V CC (V) TC74HC697AP/AF Ta = 40 to 8 C Min Typ. Max Min Max Input capacitance C IN 10 10 pf Output capacitance C OUT pf 2 4 1 12 8 16 32 17 14 11 38 2 11 23 1 26 11 23 4 24 14 2 19 39 33 14 2 Unit MHz Power dissipation capacitance C PD (Note) 72 pf Note: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: I CC (opr) = C PD V CC f IN + I CC 10

Package Dimeio Weight: 1.30 g (typ.) 11

Package Dimeio Weight: 0.22 g (typ.) 12

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