Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC
Dynamic Logic Introduction Digital IC EE141 2
Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Dynamic logic cascade solution Static or Dynamic Digital IC 3
first glance of dynamic logic Basic components PDN,just like CMOS and pseudo-nmos Clock control transistors, seperate circuit to two phases Dynamic logic s two phases precharge evaluation Digital IC 4
Dynamic CMOS Static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors Digital IC 5
Dynamic Gate In 1 In 2 In 3 M p PDN M e C L Out Two phase operation Precharge ( = 0) Evaluate( = 1) B M p M e off on off on 1 Out ((B)+C) C Digital IC 7
Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L Digital IC 8
Dynamic Logic Dynamic gates uses a clocked pmos pullup Two modes: precharge and evaluate 2 1 2/3 4/3 1 1 Static Pseudo-nMOS Dynamic Precharge Evaluate Precharge Digital IC Slide 9
The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. precharge transistor inputs f inputs f foot footed unfooted Digital IC Slide 10
Logical Effort Inverter NND2 NOR2 unfooted 1 1 g d = p d = B 1 2 2 g d = p d = 1 1 B 1 g d = p d = footed 1 1 1 3 2 B 3 2 B 2 g d = g d = 2 p d = 3 p d = 2 g d = p d = Digital IC Slide 11
Logical Effort Inverter NND2 NOR2 unfooted 1 1 g d = 1/3 p d = 2/3 B 1 2 2 g d = 2/3 p d = 3/3 1 1 B 1 g d = 1/3 p d = 3/3 footed 1 1 1 3 2 B 3 2 B 2 g d = 2/3 g d = 3/3 2 p d = 3/3 3 p d = 4/3 2 g d = 2/3 p d = 5/3 Digital IC Slide 12
Monotonicity Dynamic gates require monotonically rising inputs during evaluation 0 -> 0 0 -> 1 1 -> 1 But not 1 -> 0 violates monotonicity during evaluation Precharge Evaluate Precharge Output should rise but does not Digital IC Slide 13
Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! = 1 X Precharge Evaluate X Precharge Digital IC Slide 14
Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! = 1 X Precharge Evaluate X Precharge X monotonically falls during evaluation should rise but cannot Digital IC Slide 15
Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Dynamic logic cascade solution Digital IC 16
Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Non-ratioed sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (C out ) Digital IC 17
Properties of Dynamic Gates # Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) No glitching higher transition probabilities extra load on # PDN starts to work when the input signals exceed V Tn V M, V IH and V IL equal to V Tn low noise margin (NM L ) # Needs a precharge/evaluate clock Digital IC 18
4-NND dynamic logic VTC Digital IC 19
4-NND dynamic logic V TC Small load capacity symmetry of noise margin Small delay Fewer transistors Digital IC 20
Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Charge-leakage Charge-sharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 21
Issues in Dynamic Design 1: Charge Leakage CLK M p Out C L M e Leakage sources V Out Precharge Evaluate Dominant component is subthreshold current Digital IC 22
Solution to Charge Leakage M p M kp Keeper Width:min Length:L B C L Out Option! M e Same approach as level restorer for pass-transistor logic Digital IC 23
Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Charge-leakage Charge-sharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 24
Issues in Dynamic Design 2: Charge Sharing M p C L Out Charge stored originally on C L is redistributed (shared) over B=0 C C L and C leading to reduced M e C B robustness Could we move it to there? Digital IC 25
Charge Sharing Dynamic gates suffer from charge sharing B = 0 x C x C Charge sharing noise x V x V Digital IC Slide 26
Charge Sharing Dynamic gates suffer from charge sharing B = 0 x C x C Charge sharing noise x C V V V x DD Cx C Digital IC Slide 27
Solution to Charge Redistribution M p M kp Out B M e Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) Digital IC 28
Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Charge-leakage Charge-sharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 29
Issues in Dynamic Design 3: Backgate Coupling =0 M p C L1 Out1 =1 C L2 Out2 =0 In B=0 M e 3 Dynamic NND 2 1 Static NND Out1 0 In Out2-1 Digital IC 0 2 4 6 30 Time, ns
Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Charge-leakage Charge-sharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 31
Issues in Dynamic Design 4: Clock Feedthrough Coupling between Out and M p C L Out input of the precharge device due to the gate to drain capacitance. B So voltage of Out can rise above M e V DD. The fast rising (and falling edges) of the clock couple to Out. Digital IC 32
Clock Feedthrough Out 2.5 Clock feedthrough In 1 In 2 1.5 In 3 In 4 0.5 In & Out -0.5 0 0.5 Time, ns 1 Clock feedthrough Digital IC 33
Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Charge-leakage Charge-sharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 34
Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Charge-leakage Charge-sharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 35
Cascading Dynamic Gates V In M p Out1 M p Out2 In M e M e Out1 V Tn Out2 V Only 0 1 transitions allowed at inputs! Not 1 0! Digital IC 36 t
Domino Logic In 1 In 2 M p PDN 1 1 1 0 Out1 0 0 0 1 In 4 M p M kp PDN Out2 In 3 In 5 M e M e Digital IC 37
Domino Gates Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs Precharge Evaluate Precharge domino ND W W X Z X B C Z dynamic NND static inverter B W H C X H X Z = B C Z Digital IC Slide 38
Why Domino? In i In j PDN In i PDN In i PDN In i PDN In j In j In j Like falling dominos! Digital IC 39
Designing with Domino Logic V DD V DD V DD M p Out1 M p M r Out2 In 1 In 2 PDN In 4 PDN In 3 Can be eliminated! M e M e Inputs = 0 during precharge Digital IC 40
Footless Domino V DD V DD V DD M p Out 1 M p Out 2 M p Out n 0 1 0 1 0 1 In 1 1 0 In 2 1 0 In 3 In n 1 0 1 0 The first gate in the chain needs a foot switch Precharge is rippling short-circuit current solution is to delay the clock for each stage Digital IC 41
np-cmos In 1 In 2 In 3 M p PDN M e 1 1 1 0 Out1 In 4 In 5 M e PUN M p 0 0 0 1 Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN Digital IC 42
Domino Summary Domino logic is attractive for high-speed circuits 1.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise Widely used in high-performance microprocessors Digital IC Slide 43
Some circuits pitfalls Faults Introduction Digital IC 44
Outline Circuit Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution ll these pitfalls have caused failures in real chips Digital IC Slide 45
Bad Circuit 1 D0 D1 S X Symptom Mux works =1 when selected =1 but D=1. S Digital IC Slide 46
Bad Circuit 1 D0 D1 S X Symptom Mux works =1 when selected =1 but D=1. S Principle: Threshold drop X never rises above V DD -V t V t is raised by the body effect = V + γ( - 2Φ + V The threshold drop is most serious as V t becomes a greater fraction of V DD. V t t0 F SB - 2Φ F ) Digital IC Slide 47
Bad Circuit 1 D0 D1 S X Symptom Mux works =1 when selected =1 but D=1. S Principle: Threshold drop X never rises above V DD -V t V t is raised by the body effect V t = V t0 + γ( - 2Φ F + V SB - 2Φ F ) The threshold drop is most serious as V t becomes a greater fraction of V DD. Digital IC Slide 48
Bad Circuit 1 D0 D1 S X Symptom Mux works =1 when selected =1 but D=1. S Principle: Threshold drop X never rises above V DD -V t V t is raised by the body effect V t = V t0 + γ( - 2Φ F + V SB - 2Φ F ) The threshold drop is most serious as V t becomes a greater fraction of V DD. Solution: Use transmission gates, not pass transistors Digital IC Slide 49
Bad Circuit 2 D X Q Symptom Load a 0 into Q Set f = 0 Eventually Q spontaneously flips to 1 Digital IC Slide 50
Bad Circuit 2 D X Q Symptom Load a 0 into Q Set f = 0 Eventually Q spontaneously flips to 1 Principle: Leakage X is a dynamic node holding value as charge on the node Eventually subthreshold leakage may disturb charge Digital IC Slide 51
Bad Circuit 2 D X Q Symptom Load a 0 into Q Set f = 0 Eventually Q spontaneously flips to 1 Principle: Leakage X is a dynamic node holding value as charge on the node Eventually subthreshold leakage may disturb charge Digital IC Slide 52
Bad Circuit 3 0 1 X Symptom Precharge gate (=0) Then evaluate Eventually spontaneously flips to 1 Digital IC Slide 53
Bad Circuit 3 0 1 X Symptom Precharge gate (=0) Then evaluate Eventually spontaneously flips to 1 Principle: Leakage X is a dynamic node holding value as charge on the node Eventually subthreshold leakage may disturb charge Solution: Digital IC Slide 54
Bad Circuit 3 0 1 X Symptom Precharge gate (=0) Then evaluate Eventually spontaneously flips to 1 Principle: Leakage X is a dynamic node holding value as charge on the node Eventually subthreshold leakage may disturb charge Solution: 0 1 X Digital IC Slide 55
Bad Circuit 4 B X Symptom When only one input is true, = 0. Digital IC Slide 56
Bad Circuit 4 B X Symptom When only one input is true, = 0. Principle: Ratio Failure nmos and pmos fight each other. If the pmos is too strong, nmos cannot pull X low enough. Solution: Digital IC Slide 57
Bad Circuit 4 B X Symptom When only one input is true, = 0. Principle: Ratio Failure nmos and pmos fight each other. If the pmos is too strong, nmos cannot pull X low enough. Solution:Check that ratio is satisfied in all corners Digital IC Slide 58
Bad Circuit 5 B X Z Symptom Precharge gate while = B = 0, so Z = 0 Set f = 1 rises Z is observed to sometimes rise Digital IC Slide 59
Bad Circuit 5 B X Z Symptom Precharge gate while = B = 0, so Z = 0 Set f = 1 rises Z is observed to sometimes rise Principle: Charge Sharing If X was low, it shares charge with X C Z B C x Digital IC Slide 60
Bad Circuit 5 B X Z Symptom Precharge gate while = B = 0, so Z = 0 Set f = 1 rises Z is observed to sometimes rise Principle: Charge Sharing If X was low, it shares charge with Solutions: Limit charge sharing Safe if C >> C X Or precharge node X too C V V V x DD Cx C X B Z C C x Digital IC Slide 61
Summary Static CMOS gates are very robust Logic effect/fan-in relate to the delay/power evalutation Other circuits suffer from a variety of pitfalls Pseodu NMOS logic Pass transistor cascade problem,restorer(keeper),some pass logic Dynamic logic Characteristic Cascade issue Domino logic Some pitfalls of dynamic logic Digital IC Slide 62