4 8 6 IM ES9 ipolar Fujitsu VP IM 9S Pulsar 4 IM 9 IM RY6 D yber 5 IM 48 IM RY4 IM 8 pache Fujitsu M8 IM 7 Merced IM 6 IM Vacuum Pentium II(DSIP) 95 96 97 98 99 NTT Fujitsu M-78 Year of announcement IM RY5 MOS Jayhawk(dual) IM RY7 Prescott T-Rex Mckinley Squadrons IM GP IM 9 Pentium 4 9 8 7 6 5 4 Radio Receive for Mesh Maintenance - 6 m Typical urrent Draw sec Heartbeat beats per sample Sampling and Radio Transmission 9-5 m Low Power Sleep. -.5 m Heartbeat - m 4 6 8 Time (seconds) Digital Integrated ircuits EES http://robertdick.org/eecs/ Teacher: Robert Dick Office: 47-E EES Email: dickrp@umich.edu Phone: 74 76 9 ellphone: 847 5 84 HW engineers SW engineers GSI: Office: Email: urrent (m) Shengshou Lu 75 luss@umich.edu Review When are the advantages and disadvantages of fixed-voltage charging? When are the advantages and disadvantages of fixed-current charging? In what situation is each of the following models important? Ideal.. R. RL. What are di /dt effects? Under what circumstances do they cause the most trouble? Power density (Watts/cm ) Derive and explain. Robert Dick Digital Integrated ircuits Rent s rule Fringe vs. parallel plate capacitance T = ak p T : Number of terminals. a: verage number of terminals per block. k: Number of blocks within chip. p: Rent s exponent,, generally around.7. Plot of total for different gap ratios. 4 Robert Dick Digital Integrated ircuits 5 Robert Dick Digital Integrated ircuits Inter-wire capacitance Impact of inter-wire capacitance 6 Robert Dick Digital Integrated ircuits 7 Robert Dick Digital Integrated ircuits
Wire resistance Interconnect resistance R = ρl HW. onsider fixed-height, fixed-ρ square material, i.e., L/W =. R = ρ H. Material ρ (Ω m) 8 Silver.6 opper.7 Gold. luminum.7 Tungsten 5.5 8 Robert Dick Digital Integrated ircuits 9 Robert Dick Digital Integrated ircuits Reducing resistance Silicides Higher interconnect aspect ratios Material selection opper Silicides arbon nanotubes Structural changes More interconnect layers -D integration Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Resistances Multi-layer interconnect Material Sheet resistance (Ω/ ) n- or p-well diffusion,,5 n + or p + diffusion 5 5 silicided n + or p + diffusion 5 doped polysilicon 5 doped silicides polysilicon 4 5 luminum.5. Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits
Side view of interconnect Interconnect summary It is important to know which interconnect model to use in which situation. Ideal.. R. RL. di /dt effects are particularly important in power delivery networks. apacitive coupling complicates design. u and silicides can be used to reduce resistance. 4 Robert Dick Digital Integrated ircuits 5 Robert Dick Digital Integrated ircuits Delay modeling Elmore delay Single-node lumped model inaccurate. Full detailed accurate model intractable for manual analysis and slow for automated analysis. Elmore delay model permits rapid analysis with often adequate accuracy. Problem definition Goal: Determine τ for R path. Note: Source node is implicit. i : Self-capacitance of node i. R ii : Path resistance from source to node i. R ik : Shared resistance from source to both nodes i and k. N τ i = k R ik k= Derive and explain. 7 Robert Dick Digital Integrated ircuits 8 Robert Dick Digital Integrated ircuits Special case: R chains onsider π network. τ n = n i= i i j= R j. Use homogeneous discretization. N i= i = τ = N k= R nk = L N c L N(N + ) r N = rcl N + N What if N? τ rcl /. Underlying continuous physical model cr δv δt = δ V δx 9 Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits
Response to step function over time and space Power delivery network considerations IR drop. di/dt effects. Location of parasitic inductance. Methods to correct power delivery network non-idealities. Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Simplifying assumptions Elmore delay summary Ignore wire R delay when wire delay does not much exceed that of the driving gate, i.e., tp,gate L crit.8rc Ignore wire R when rise time greater than R delay. Ignore for high-resistance wires: R >.. Ignore when time of flight is large compared to rise or fall time: t rise,fall <.5t flight. Pick simplest model for intended purpose:, R, or RL. apacitive coupling complicates timing analysis. Transition direction impacts magnitude in simplified ground-cap model. Learn Elmore delay. It is a good first-order approximation of network delay. Robert Dick Digital Integrated ircuits 4 Robert Dick Digital Integrated ircuits Static MOS design styles and components Transistor sizing review Logic gates MUX DEMUX Encoder Decoder Goal: equal τ for worst-case pull-up and pull-down paths. Observations dding duplicate parallel path halves resistance. dding duplicate series path doubles resistance. Doubling width halves resistance. onsider logic gate examples. 6 Robert Dick Digital Integrated ircuits 7 Robert Dick Digital Integrated ircuits
MOS transmission gate (TG) Other TG diagram 9 Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits Multiplexer (MUX) definitions MUX functional table lso called selectors n inputs n control lines One output I I Robert Dick Digital Integrated ircuits Robert Dick Digital Integrated ircuits MUX truth table MUX using logic gates I I I I I Robert Dick Digital Integrated ircuits 4 Robert Dick Digital Integrated ircuits
MUX using TGs MUX I I D : D I I 5 Robert Dick Digital Integrated ircuits 6 Robert Dick Digital Integrated ircuits Hierarchical MUX implementation lternative hierarchical MUX implementation I I I I 4 I 5 I 6 I 7 4: mux S S 4: mux S S 8: mux : mux S I I I I 4 I 5 I 6 S S S S S I 7 S 7 Robert Dick Digital Integrated ircuits 8 Robert Dick Digital Integrated ircuits MUX examples MUX examples I I : m ux I I I 4: m ux = I + I = I + I + I + 9 Robert Dick Digital Integrated ircuits 4 Robert Dick Digital Integrated ircuits
MUX examples MUX properties I I I I 4 I 5 I 6 I 7 8: m ux n : MUX can implement any function of n variables n : can also be used Use remaining variable as an input to the MUX = I + I + I + + I 4 + I 5 + I 6 + I 7 4 Robert Dick Digital Integrated ircuits 4 Robert Dick Digital Integrated ircuits MUX example Truth table F (,, ) = (,, 6, 7) = + + + F 4 Robert Dick Digital Integrated ircuits 44 Robert Dick Digital Integrated ircuits Lookup table implementation MUX example 4 8: MUX 5 6 7 S S S F Therefore, F (,, ) = (,, 6, 7) = + + + F = F = F = F = 45 Robert Dick Digital Integrated ircuits 46 Robert Dick Digital Integrated ircuits
Truth table Lookup table implementation F F= S 4: MUX S F 47 Robert Dick Digital Integrated ircuits 48 Robert Dick Digital Integrated ircuits summary Examples Logic gate, transmission gate, and pass transistor design each have applications. MUX-based design provides a good starting point for transmission gate and pass transistor based design. Instead of flying through a bunch of slides, let s try examples. f (a) = a. f (a) = a f (a, b) = ab f (a, b) = ab (heck Figure 6- in J. Rabaey,. handrakasan, and. Nikolic. Digital Integrated ircuits: Design Perspective. Prentice-Hall, second edition,!) f (a, b, c) = ab + bc (try both ways). Derive and explain. 49 Robert Dick Digital Integrated ircuits 5 Robert Dick Digital Integrated ircuits Upcoming topics assignment lternative logic design styles. Latches and flip-flops. Memories. October: Read sections 4.4., 4.4.4, and 9.. in J. Rabaey,. handrakasan, and. Nikolic. Digital Integrated ircuits: Design Perspective. Prentice-Hall, second edition,. 4 October: Read sections 6.. and 6.. in J. Rabaey,. handrakasan, and. Nikolic. Digital Integrated ircuits: Design Perspective. Prentice-Hall, second edition,. 5 October: Lab. 9 October:. 5 Robert Dick Digital Integrated ircuits 5 Robert Dick Digital Integrated ircuits