Introduction to CMOS VLSI Design Lecture 9: Combinational Circuits David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh
Outline q ubble Pushing q Compound Gates q Logical Effort Example q Input Ordering q symmetric Gates q Skewed Gates q est P/N ratio Slide
Example module mux(input s, d0, d, output y); assign y s? d : d0; endmodule ) Sketch a design using ND, OR, and NOT gates. Slide 3
Example module mux(input s, d0, d, output y); assign y s? d : d0; endmodule ) Sketch a design using ND, OR, and NOT gates. D0 S D S Slide
Example ) Sketch a design using NND, NOR, and NOT gates. ssume ~S is available. Slide 5
Example ) Sketch a design using NND, NOR, and NOT gates. ssume ~S is available. D0 S D S Slide 6
ubble Pushing q Start with network of ND / OR gates q Convert to NND / NOR + inverters q Push bubbles around to simplify logic Remember DeMorgan s Law (a) (b) (c) D (d) Slide 7
Example 3 3) Sketch a design using one compound gate and one NOT gate. ssume ~S is available. Slide 8
Example 3 3) Sketch a design using one compound gate and one NOT gate. ssume ~S is available. D0 S D S Slide 9
Compound Gates q Logical Effort of compound gates unit inverter OI OI g+ C + C D C C D D E C Complex OI g g g( ) + C + DgE 6 C C C D C D C D E 6 3 6 E 6 D C g 3/3 g 6/3 g g p 3/3 g 6/3 g g g C 5/3 g C g C p 7/3 g D g D p g E p Slide 0
Compound Gates q Logical Effort of compound gates unit inverter OI OI g+ C + C D C C D D E C Complex OI g g g( ) + C + DgE 6 C C C D C D C D E 6 3 6 E 6 D C g 3/3 g 6/3 g 6/3 g 5/3 p 3/3 g 6/3 g 6/3 g 8/3 g C 5/3 g C 6/3 g C 8/3 p 7/3 g D 6/3 g D 8/3 p /3 g E 8/3 p 6/3 Slide
Example q The multiplexer has a maximum input capacitance of 6 units on each input. It must drive a load of 60 units. Estimate the delay of the NND and compound gate designs. Slide
Example q The multiplexer has a maximum input capacitance of 6 units on each input. It must drive a load of 60 units. Estimate the delay of the NND and compound gate designs. D0 S D S D0 S D S H 60 / 6 0 N Slide 3
NND Solution D0 S D S Slide
NND Solution P + G ( / 3) g( / 3) 6 / 9 F GH 60 / 9 ˆ N f F. D Nfˆ + P.τ D0 S D S Slide 5
Compound Solution D0 S D S Slide 6
Compound Solution P + 5 G (6/3) g() F GH 0 ˆ N f F.5 D Nfˆ + P τ D0 S D S Slide 7
Example 5 q nnotate your designs with transistor sizes that achieve this delay. Slide 8
Example 5 q nnotate your designs with transistor sizes that achieve this delay. 8 8 8 8 8 8 8 8 5 5 5 5 0 0 6 6 6 60 * (/3) /. 50 6 60 * /.5 36 6 0 0 6 Slide 9
Input Order q Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? If arrives latest? x 6C C Slide 0
Input Order q Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? τ If arrives latest?.33τ x 6C C Slide
Inner & Outer Inputs q Outer input is closest to rail () q Inner input is closest to output () q If input arrival time is known Connect latest input to inner terminal Slide
symmetric Gates q symmetric gates favor one input over another q Ex: suppose input of a NND gate is most critical q g q g Use smaller transistor on (less capacitance) oost size of noncritical input So total resistance is same reset q g total g + g q symmetric gate approaches g on critical input q ut total logical effort goes up reset /3 Slide 3
symmetric Gates q symmetric gates favor one input over another q Ex: suppose input of a NND gate is most critical Use smaller transistor on (less capacitance) oost size of noncritical input So total resistance is same q g 0/9 q g reset q g total g + g 8/9 q symmetric gate approaches g on critical input q ut total logical effort goes up reset /3 Slide
Symmetric Gates q Inputs can be made perfectly symmetric Slide 5
Skewed Gates q Skewed gates favor one edge over another q Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / q Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. Slide 6
Skewed Gates q Skewed gates favor one edge over another q Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / q Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge..5 / 3 5/6.5 /.5 5/3 Slide 7
HI- and LO-Skew q Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. q Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nmos) LO-skew gates favor falling output (small pmos) q Logical effort is smaller for favored direction q ut larger for the other direction Slide 8
Catalog of Skewed Gates Inverter NND NOR unskewed /3 /3 /3 5/3 5/3 5/3 HI-skew / 5/6 5/3 5/ LO-skew /3 /3 Slide 9
Catalog of Skewed Gates Inverter NND NOR unskewed /3 /3 /3 5/3 5/3 5/3 HI-skew / 5/6 5/3 5/ / / LO-skew /3 /3 Slide 30
Catalog of Skewed Gates Inverter NND NOR unskewed /3 /3 /3 5/3 5/3 5/3 HI-skew / 5/6 5/3 5/ 3/ / / 3/ 3 9/ LO-skew /3 /3 3/ 3/ Slide 3
symmetric Skew q Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input reset reset /3 Slide 3
est P/N Ratio q We have selected P/N ratio for unit rise and fall resistance (µ -3 for an inverter). q lternative: choose ratio for least average delay q Ex: inverter Delay driving identical inverter t pdf t pdr t pd Differentiate t pd w.r.t. P Least delay for P P Slide 33
est P/N Ratio q We have selected P/N ratio for unit rise and fall resistance (µ -3 for an inverter). q lternative: choose ratio for least average delay q Ex: inverter Delay driving identical inverter t pdf (P+) t pdr (P+)(µ/P) t pd (P+)(+µ/P)/ (P + + µ + µ/p)/ Differentiate t pd w.r.t. P Least delay for P µ P Slide 3
P/N Ratios q In general, best P/N ratio is sqrt of equal delay ratio. Only improves average delay slightly for inverters ut significantly decreases area and power Inverter NND NOR fastest. P/N ratio Slide 35
P/N Ratios q In general, best P/N ratio is sqrt of that giving equal delay. Only improves average delay slightly for inverters ut significantly decreases area and power Inverter NND NOR fastest. P/N ratio.5 0.8 0.98 /3 /3 /3 3/ Slide 36
Observations q For speed: NND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input q For area and power: Many simple stages vs. fewer high fan-in stages Slide 37